design for manufacturability and yield · 2013-06-03 · system-on-chip test architectures ch. 9 -...

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System-on-Chip Test Architectures Ch. 9 - Design for Manufacturability and Yield - P. 1

Chapter 9Chapter 9

Design for Manufacturability and YieldDesign for Manufacturability and Yield

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What is this chapter about?What is this chapter about?

� Introduce Design for Manufacturability (DFM) and related concepts

� Focus on:

� Design for Yield (DFY) and yield models

� Photolithography

� Relationship between DFM, DFY, DFT

� Design for Excellence (DFX)

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Design for Manufacturability & YieldDesign for Manufacturability & Yield

� Introduction

� Yield

� Components of Yield

� Lithography

� DFM and DFY

� Variability

� Metrics for DFX

� Concluding remarks

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IntroductionIntroduction

� In the 1960s all aspects of IC design and manufacture could be confined to a single organization

� Through the 1980s specialized fabs were common for individual products

� Throughout this time technology followed Moore’s law, with ever increasing integration

� Increased integration came with increasing costs

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DisaggregationDisaggregation

� Rising manufacturing costs led to ecosystem with specialized fabs fed by fabless semiconductor companies

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YieldYield

� Difficulty lies in separating good from bad

� Competing definitions of “good”� Ideal: works in customer’s application

– Can’t measure this until it’s too late!

� Example ambiguity: high leakage from defects and/or fast transistors

� Practical definition “passes the tests we apply”

chipstotal

chipsgoodYield =

partsall

rejectsfalseescapestestpartsgoodYieldMeasured

−+=

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Components of YieldComponents of Yield

� Systemic problems (foundry)

� Related to processing, managed by

foundry

� Kinds: spatial across wafer, layer-specific,

machine-specific,etc.

� Example: Oxide problems due to

deposition

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� Parametric variations (foundry, IP vendor)� Designs characterized over parametric window

(“slow/typ/fast”)

� Foundry process must remain within this window

� Example parameters:

– Channel length/width variation

– nMOS to pMOS length ratio variation

– Effective gate oxide thickness variation

– Doping variation - threshold voltage and diffusion resistance

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� Parametric variations (foundry, IP vendor)

� Defect-related yield (foundry, IP vendor, design team)

� Susceptibility to shorts and opens

� Caused by particles, cracks, voids,

scratches, missing vias, etc.

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� Design-related yield (IP vendor, design team)� Increasingly important issue

� Examples: optical, physical/mechanical, electrical

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� Design-related yield (IP vendor, design team)

� Test-related yield (test vendor)� Examples: overkill from guardbanding, test escapes

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� Test-related yield (test vendor)

� DFY concerned with all of these

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Yield modelsYield models

Yield = systematic yield

* parametric yield

* defect yield

* design yield

* test yieldAD

S eYY−⋅=

Poisson

α

α

+

=AD

YY S

1

1

Negative Binomial

( )nSAD

YY+

=1

1

Bose-Einstein

2

1

−=

−

AD

eYY

AD

S

Murphy

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Origins of ModelsOrigins of Models

� Poisson Model

� Defects are events from a random process with a uniform defect density

� Murphy Model

� Defect density is not uniform, approximate Gaussian with a triangle distribution

� Bose-Einstein Model

� Some layers more susceptible than others to defects, density uniform per layer

� Negative Binomial Model

� Defects tend to cluster together

AD

S eYY−⋅=

Poisson

α

α

+

=AD

YY S

1

1

Negative Binomial

( )nSAD

YY+

=1

1

Bose-Einstein

2

1

−=

−

AD

eYY

AD

S

Murphy

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Yield and RepairYield and Repair

� Four classes of yield:

� Systematic problems (foundry)

– Mild cases can be helped by repair


– Mainly covered by design margin

– Local extreme cases (e.g. weak cells) can be helped by repair


– Most can be fixed with repair


– Covered by improved design practice

� Repair mainly addresses #3 (defects) at 90nm and

above

� At 65nm and below, variability also important

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Repairable MemoryRepairable Memory

� Memory fails more than logic

� Repairable memory improves yield

( )ADerepairP

yieldbaserepairPY

−−⋅=

−⋅=∆

1)(

)_1()(

( )( ) nADnADDAA

nn

n

eerepairPe

yieldbaseyieldrepairY

r −−+−−−⋅+=

−=∆

1)(

__

)(

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Potential Yield ImprovementPotential Yield Improvement

Even at high overhead, significant yield improvementis possible

0.25

0.5

0.75

11.25

5%

10%15%

20%25%

0%

1%

2%

3%

4%

5%

6%

7%

Defect Density

Test Overhead

Yield Improvement

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PhotolithographyPhotolithography

� Decreasing feature size not accompanied by decreasing wavelength of light used

� 193nm and 157nm wavelengths most common in current technology

� Printing of features at 65nm, 45nm, and below uses off axis illumination, immersion lithography and more

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Lithography Basics (Lithography Basics (RayleighRayleigh Equation)Equation)

illum. λλλλ

Pmin = 1 ----λλλλ

NA

mask

lens

image

R = k1 ----

k1 min=0.5

λλλλ

NA

sinθθθθm = m ------λλλλ

P

P = m ----λλλλ

sinθθθθ

Rmin = 0.5 ----λλλλ

NA

1) resolution is controlled by λ and NA

2) improving resolution by increasing NA hurts DOF

3) k = 0.5 resolution limit is real physical barrier Courtesy L. Liebmann

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� DRC moving beyond simple distance metrics to shape-based approaches

SRAF SRAF –– Sub Resolution Assistance FeaturesSub Resolution Assistance Features

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Example shapeExample shape--based problem layoutbased problem layout

Feature will be a problem acrossa wide range ofgeometries

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DFM and DFYDFM and DFY

� Uniformity is good for manufacturing

� Example: arrays of bit cells

� Non-uniformity creates value

� Example: standard cells with different

layout

� DFM Challenge:Maintain manufacturability (enough uniformity) while allowing value (enough non-uniformity)

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Uniformity in PolysiliconUniformity in Polysilicon

� Compare SRAM array (left) with pre-DFM standard cell (right)� Uniform direction

� Uniform shapes

� Uniform spacing

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DFM is SubtleDFM is Subtle

� Major problems found early in a process generation

� Addressed by design rules

� Minor changes in layout cause significant changes in manufacturability and yield

� Examples: moving a wire a few nanometers, adding extra overlap around a contact, doubling a via

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Lithography SimulationLithography Simulation

� Simulate manufacturing process to identify problem areas (“hot spots”)

� Several commercial solutions available

� Sensitive process information can be encrypted

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Some DFM ChallengesSome DFM Challenges

� Forbidden pitches

� Caused by inability to place SRAF due to

conflict with neighboring shapes

� Shape-based problems, distance-based rule decks

� Complex rules built out of need to avoid

certain shapes combined with need to

express constraints in standard DRC terms

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DRC Spacing ExampleDRC Spacing Example

� DRC is yes/no� Silicon is continuous� DFM recommendations and waivers attempt to compensate

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Spacing

Rela

tive D

efe

ct P

robability

Waiver spacing

Minimum spacing

Recommended spacing

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Quantifying DFM: Critical AreaQuantifying DFM: Critical Area

� Critical area measures the area where the center of a fixed size circular defect can land and cause a short or an open

� Can be weighted by size distribution (typically 1/x3)

2.0um

0.4um

0.5um

0.1um

critical area = 2um x 0.1um

0.5um

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0.1 0.15 0.2 0.25 0.3 0.35 0.4

Spacing

Rela

tive D

efe

ct

Pro

bab

ilit

y

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Weighted Critical AreaWeighted Critical Area

� Combine critical area and defect distribution into single value

� Integrate area under yellow curve for total value

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

0 100 200 300 400 500

separation (nm)

A.U

.

defect density

critical area

weighted critical area

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More open space

=Fewer shorts

Double contacts

=Fewer opens

Yield variation over timeYield variation over time

At any time, one or the other could be better

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Process improved continuallyProcess improved continually

� Fab engineers use a Pareto chart to find key problems

� Over time, systematic problems will be fixed, leaving random (defect-related) yield to dominate

0

2

4

6

8

10

12

Bridge

M2

Contact

Fail

Bridge

M1

Open

Poly

Bridge

Poly

Open V1 Bridge

M4

Bridge

M3

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VariabilityVariability

� Historically, test concerned with defects, validation concerned with design variation

� Process variability occupies a middle ground

� Small variation: expected

� Medium variation: needs to be tolerated by

design (margin)

� Large variation: needs to be found by test

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Sources of variabilitySources of variability

� Accounted for by standard device model � Lot-to-Lot

� Wafer-to-Wafer

� Die-to-Die

� More complex effects, sometimes included in model� Within Die examples

– Length variability

– Oxide variability

– Implant variability

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Example: Leakage and Gate LengthExample: Leakage and Gate Length

� Longer gate leads to higher Vt

� Small change in Vt (<100mV) leads to large change in Ioff (10X) with small change in performance (10%)

IOFFH

IOFFL

IDS

VTL VTH VG

Low VT

High VT

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Finding variability at wafer levelFinding variability at wafer level

� Reticle based variability� 2x2 reticle

� Patterning issue – likely sources masks, lithography

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� Chemical/physical aspects of process optimized for middle distance from center, can cause variability issues at center and edges� Examples include etch, polishing

Variability across a waferVariability across a wafer

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Radial variabilityRadial variability

� Starts in one region and works outwards� May be related to position in equipment

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Variability versus defectivityVariability versus defectivity

� Outliers and discontinuities may be defect related

likely defects

questionable

likely variability

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DFX DFX –– Design For ExcellenceDesign For Excellence

� DFX = multidimensional optimization

� DFX can be

� DFT: testability

� DFM: manufacturability

� DFY: yield

� DFR: reliability

� Optimization requires quantification

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Quantified Tradeoffs Quantified Tradeoffs –– DFM MetricsDFM Metrics

� Simple but effective

� Recommended rule classes

� No effect on area: implement all

� Affects area

– Find intermediate value point

� Example: contact-poly spacing

� Minimum DRC value: 80nm (0 credit)

� Recommended DRC value: 120nm (full credit)

� 80% of yield benefit achieved: 90nm (half credit)

� Sum and score across instances

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Example DFM Rules and MetricExample DFM Rules and Metric

0.05 on 4 0.05 on 4 0.05 on 4 0.05 on 4 sidessidessidessides



.1.1.1.14. Maximize contact 4. Maximize contact 4. Maximize contact 4. Maximize contact overlapoverlapoverlapoverlap

0.25 spacing0.25 spacing0.25 spacing0.25 spacing0.2 spacing0.2 spacing0.2 spacing0.2 spacing0.15 spacing0.15 spacing0.15 spacing0.15 spacing.2.2.2.23. Reduce critical area 3. Reduce critical area 3. Reduce critical area 3. Reduce critical area for poly gatesfor poly gatesfor poly gatesfor poly gates

Jog <0.05Jog <0.05Jog <0.05Jog <0.05Jog > 0.05Jog > 0.05Jog > 0.05Jog > 0.05Jog > 0.1Jog > 0.1Jog > 0.1Jog > 0.1.3.3.3.32. 2. 2. 2. Avoid jogs in polyAvoid jogs in polyAvoid jogs in polyAvoid jogs in poly

0.150.150.150.150.10.10.10.10.050.050.050.05.4.4.4.41. Increase line end 1. Increase line end 1. Increase line end 1. Increase line end

100%100%100%100%50%50%50%50%0%0%0%0%

ScoringScoringScoringScoringWeightWeightWeightWeightRuleRuleRuleRule

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3A

3B

1A1B

2B

2A 4A

4B

Metric in practiceMetric in practice

� Example rules:1. Line ends

2. Jogs

3. Spacing

4. Contact overlap

� Key:A=bestB=partial

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3A

3B

1A1B

2B

2A 4A

4B

1C

1C

4C

Improved LayoutImproved Layout� Metric improves for

1. Line ends

2. Jogs

3. Spacing

4. Contact overlap

� Some locations

cannot be

improved (“C”)

without increasing

area

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Concluding RemarksConcluding Remarks� Yield is a complex function of many

variables

� Repair can improve yield for some structures

� Photolithography and related challenges influence DFM rules

� Effective DFM more complicated than design rule checking allows

� Metrics can be developed to improve manufacturability

� Multidimensional optimization is the key to effective Design For Excellence (DFX)

design for manufacturability and yield · 2013-06-03 · system-on-chip test architectures ch. 9 -...

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