design for test of digital systems tddc33tddc33/lecture/tddc33_10_le3.pdf · making electronic...

Design for Test of Digital Systems TDDC33

Erik LarssonDepartment of Computer Science

Course Outline

! Introduction; Manufacturing, Wafer sort, Final test, Board and System Test, Defects, and Faults

! Test generation; combinational and sequential test generation! Design-for-Test techniques; test point insertion, scan, enhanced

scan! Built-In Self-Test; Logic BIST and memory BIST! System Chip Test; test architectures, test planning, test

scheduling, and test data compression, power constraints! System Chip Test; test data compression, test scheduling! System Test and Boundary Scan! Diagnosis; scan-chain and logic diagnosis

Note!

! Invited lecture by Dr. Thomas Granlund, SAAB, on Thursday (September 30)at 09:15 at Alan Turing (hence, lecture on October 1 cancelled)

! Lab on Wednesday (September 29) and Thursday (September) moved to Monday (September 27) at 17-21 (SU2, SU3).

3

Making electronic products

Salt

Seed

45

Making fault free electronic products

ok?

Test Preparation Production Test In-Field Test

ok?ok?

ok?

ok?

May 8, 2008 52

Testing

Device under test00101000110000

Test stimuli (TS)!

Compare

Automatic Test Equipment (ATE) !

Pass/fail

Expected responses (ER)!10110011101010

01110110100101

Produced responses (PR)!

25

Deterministic Test Generation

A basic ATPG (automatic test-pattern generation) algorithm 1. activate a fault. If stuck at 1, set the pin or node to '0‘ (the

opposite value of the fault) 2. work backward from the fault origin to the PIs (primary inputs)

by recursively justifying signals at the output of logic cells 3. work forward from the fault origin to a PO (primary output),

setting inputs to gates on a sensitized path to their enabling values. Propagate the fault until the D-frontier reaches a PO.

4. work backward from the PO to the PIs recursively justifying outputs to generate the sensitized path.

D-notation

! Five-valued algebra (0,1,X,D,D’)! D=1/0 ! D’=0/1

! Stuck-at 0 on A ->! Line A = D! To propagate D (fault effect) to

Z (check table) set B=1

OR 0 1 D D’ X

0 0 1 D D’ X

1 1 1 1 1 1

D D 1 D 1 X

D’ D’ 1 1 D’ X

X X 1 X X XAND 0 1 D D’ X

0 0 0 0 0 0

1 0 1 D D’ X

D 0 D D 0 X

D’ 0 D’ 0 D’ X

X 0 X X X X

ANDA

B

Z

D-AlgorithmOR

NORA

Z

BAND

NOR

AND

UW

X

Y

F

H

G

Stuck-at 0

1 Operation Gate A B X Y W U F G H Z

2 Initialization x x x x x x x x x x

3 Provoke G1 0 0 D x x x x x x x

4 D-drive G2 0 0 D x 1 x D x x x

5 D-drive G3 0 0 D x 1 0 D D’ x x

6 D-drive G5 0 0 D x 1 0 D D’ 0 D’

7 Justification H=0 0 0 D x 1 0 ! D’ 0 D’

8 Justification H=0 0 0 D 0 1 0 D D’ 0 D’

G1G2

G3

G4

G5

Tests

! Good IC that pass test -> OKBad IC that fail test -> OK

! Bad IC that pass test -> test escapeGood IC that fail test -> yield loss

10

TestTest

Pass Fail

IC

Good OK Yield loss

ICBad Test

esc. OK

51

Commercial ATPG Tools

! Test generation is time consuming! Commercial ATPG tools are often for combinational circuits! Commercial tools usually make use of a random test generation

for 60-80% of the faults (easy to detect) and deterministic test generation for the remaining part (hard to detect)

! Hard to detect/test parts are a main obstacle! Modify the design such that test generation becomes easier! Main problems in test generation:

! Set values of internal nodes/lines

! Propagate values of internal nodes/lines

! Improve: ! Observability

! Controllability

Design for performance and design for low-power are common to reach high performance and/or low power. Possible to design-for-test such that design becomes easy to test?

Obstacle? OR

NORA

Z

BAND

NOR

AND

UW

X

Y

F

H

G

Stuck-at 0

1 Operation Gate A B X Y W U F G H Z

2 Initialization x x x x x x x x x x

3 Provoke G1 0 0 D x x x x x x x

4 D-drive G2 0 0 D x 1 x D x x x

5 D-drive G3 0 0 D x 1 0 D D’ x x

6 D-drive G5 0 0 D x 1 0 D D’ 0 D’

7 Justification H=0 0 0 D x 1 0 ! D’ 0 D’

8 Justification H=0 0 0 D 0 1 0 D D’ 0 D’

G1G2

G3

G4

G5

Design for Test

! Test point insertion! Test synthesis! Scan technique

13

Ad hoc DFT approaches

! Insert test points! Avoid asynchronous set/reset for storage elements! Avoid combinational feedback loops! Avoid redundant logic! Avoid asynchronous logic! Partition a large circuit into small blocks

14

Test Point Insertion

ANDA

L

B

NOT

OR

NOTE

F

C K

H

G1

G2

AND

G3

G4

G5

G

X

XXX

X

Stuck-at 1


ANDA

L

B

NOT

OR

NOTE

F

C K

H

G1

G2

AND

G3

G4

G5

G

Stuck-at 1

observation point

X

XXX

D’

X

15


ANDA

L

B

NOT

OR

NOTE

F

C K

H

G1

G2

G4

G5

G

0-control point

AND

G3Stuck-at 10

X

XXX

X


18

0-controllability 1-controllability

Original Observation

OP

CPCP

1/0-controllability

CP1

MUX

0

1

CP2


19

DEMUX

REG

CP1CP2..CPN

X1 X2 Xn

N=2n

....MUX

PO

SELECT

Normal functionaloutputs

Observationtest point

n/

n/

n/

DEMUX

Normal primary inputs

SELECT

Normal functional

inputs

Controltest point

REG

n/

n/

n/

n/


! Test Points! Adds new PI and PO

! Benefits:! Improves:

! Observability! Controllability

! Costs:! Additional primary input/output

! Solution:! Testability Analysis

Testability Analysis! Guide test generation algorithm! Predict hard to test areas in a circuit! Sandia Controllability/Observability Analysis Program (SCOAP)

Goldstein L. H. Controllability/observability analysis of digital circuits, IEEE Transactions on Circuits and Systems, Vol. CAS-26, No. 9, 1980, pages 683-.693

! Controllability: Effort to control a value! CC0 - combinational 0-controllability (see lecture 2)! CC1 - combinational 1-controllability (see lecture 2)

! SC0 - sequential 0-controllability (measure sequential depth (nr ff)! SC1 - sequential 1-controllability (measure sequential depth (nr ff)

! Observability: Effort to observe a value! CO – combinational observability (see lecture 2)! SO – sequential observability (measure sequential depth (nr ff)

Test Synthesis

! Test points changes the design without significantly impacting the functionality

! Synthesis is the transformation of a design from high-level to a more.

! Synthesis involves: ! Allocation! Binding

! Scheduling

! Synthesis commonly uses performance and power-consumption objectives,

! However, testability of a design can be improved by synthesis

22

Test Synthesis

! Z=X+X+X

23

+

+

X X X

Z

+

REG

X X

Z

MUX

Clockcycle

Clockcycle

Performance versus testability

Design for Test

! Test point insertion! Test synthesis! Scan technique

24

Sequential -> Combinational

! Problem: ATPG works for combinational logic while most ICs are sequential

! Solution: Provide a test mode in which flip flops can be accessed directly

! Register provide virtual primary inputs/primary outputs

Combinational logic

PI PO

Flip flops

1. Write flip flops2. Stimulus at inputs3. Normal cycle

launch/capture4. Observe output5. Read flip flops

Combinational logic

PI PO

Flip flops

Scan Design Concept

! Replace flip flop (FF) with scan flip flop (SFF): extra multiplexer on data input

! Connect SFFs to form one or more scan chains! Connect multiplexer control signal to scan enable

FFMUX

CLK

SE

Q

SO

DSI

FF

CLKQ

D

SFF

SE: Scan enableSI: Scan inputSO: Scan output

Circuit without Scan

FF

Combinational logic

FF

Combinational logic

Combinational logic

FF

FF

Clock

FF

FF

Flow of data

Circuit with Scan

FF

Combinational logic

MUXFFMUX

Combinational logic

Combinational logic

FFMUX

FFMUX

Scan enable

ClockScan Input Scan Output

FFMUX

FFMUX

Circuit with Scan

FF

Combinational logic

MUXFFMUX

Combinational logic

Combinational logic

FFMUX

FFMUX

Scan enable

ClockScan Input Scan Output

FFMUX

FFMUX

Sequential -> Combinational

! Circuit can be in two modes: Functional mode and Test mode! In Test mode test data can be shifted in and shifted out! Test mode adds virtual PI and PO such that test data can be

directly applied to combinational logic! ATPG for combinational logic works also for sequential

1. Write flip flops2. Stimulus at inputs3. Normal cycle

launch/capture4. Observe output5. Read flip flops

Combinational logic

PI PO

Flip flops

Combinational logic

PI PO

Flip flops

Test Application

31

Device under test00101000110000

Test stimuli (TS)!

Compare

Automatic Test Equipment (ATE) !

Pass/fail

Expected responses (ER) !10110011101010

01110110100101

Produced responses (PR)!

Test Application

32

Combinational logic

Stimuli Responses

Clock 5 4 3 2 1 5 4 3 2 1

Scan Test Application - first attempt

Scan chain 1 (6 FFs)

SE

SI SO

A[0:4] Z[0:2]

Combinational logic

SE: 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 SI:

A[0:4]

stimulus response stimulus response stimulus response

Shift-in Shift-in Shift-in Shift-outShift-outShift-out

Capture Capture Capture

Test time=number of patterns *(shift-in + capture + shift-out)=3*(6+1+6)=39

Scan Test Application - second attempt


SE

SI SO

A[0:4] Z[0:2]

Combinational logic

SE: 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 SI:

A[0:4]

stimulus resp/stim res/stim response

Shift-in Shift-in/out Shift-outShift-in/outCapture Capture Capture

Test time=number of patterns *(shift-in + capture) + shift-out=3*(6+1)+6=27

Scan Test Application



SE

SI[0:1] SO[0:1]

A[0:4] Z[0:2]

Scan in test pattern iFor i=1 to N-1 do Apply/capture test pattern i scan out test pattern i and scan

in test pattern i+1EndApply/capture test pattern NScan out test pattern N

Scan Benefits and Costs

Scan Benefits! Automatic scan insertion! ATPG ! High fault coverage! Short test development time

EDA tools ! For scan insertion (converting

flip flops to scan flip flops)! Connection! Partial scan selection

! Scan stiching

Scan Costs! Silicon area - Mux, scan

chain, scan enable! Performance reduction -

Multiplexer in time-critical path! IC pins - Scan-in (SI), scan-

out (SO), scan_enable (SE)! Test time - Serial shifting is

slow

Scan approaches

! Muxed D-scan, Clocked-scan, Level-sensitive scan design (LSSD), Random Access Scan (RAS):

! First report by A. Kobayashi, et al., A flip-flop circuit suitable for FLT, Annual Meeting of the Institute of Electronics, Information and Communication Engineers, Manuscript 892, p. 962, 1963 (in Japanese).

! T. W. Williams and J. B. Angell, Enhancing testability of large scale integrated circuits via test points and additional logic, IEEE Transactions on Computers, Vol. C-22, No. 1, pp. 46-60, 1973.

! E. B. Eichelberger and T. W. Williams, A logic design structure for LSI testability, Proceedings of the 14th Design Automation Conference, pp. 462-468, 1977.

! H.Ando, "Testing VLSI with Random Access Scan," COMPCON80, pp.50-52, 1980.

Level-sensitive scan design (LSSD)

! MuxScan and clocked-scan are used for edge-trigged flip-flop designs.

! LSSD scan cells are used for latch-based designs! LSSD let separate clock phases drive scan elements! Advantage of LSSD is that it is race-free. The disadvantage is

that it requires additional clock routing.


L1L1

L2L2

DCLK

SI A

B

CLKABDSIL1L2

D1 D2

T1 T2 D1 T2

T2


X1

X2X3

Y1

Y2

Combinational logic

L1DCLKSIA

L1L1

BL2

L1DCLKSIA

L1L1

BL2

L1DCLKSIA

L1L1

BL2

SI

AB

CLK

SO

Random Access Scan

! H.Ando, "Testing VLSI with Random Access Scan," COMPCON80,. pp.50-52 (1980)

Scan Design Rules

42

Design style Scan Design Rule Recommended Solution

Tristate buses Avoid during shift Fix bus contention during shift

Bidirectional I/O ports Avoid during shift Force to input or output mode during shift

Gated clocks Avoid during shift Enable clocks during shift

Derived clocks Avoid Bypass clocks

Combinational feedback loops

Avoid Break the loop

Asynchronous set/reset Avoid Use external pins

Clocks driving data Avoid Block clocks to the data portion

Floating buses Avoid Add bus keepers

Floating inputs Not recommended Tie to Vdd or ground

Cross-coupled NAND/NOR gates

Not recommended Use standard cells

Non-scan storage elements Not recommended for full-scan designs Initialize to known states, bypass, or make transparent

Scan Design Flow

1. For a circuit, check scan design rules and repair2. Scan Cell Insertion3. Scan Cell Ordering4. Scan Verification

43

Delay Test

! Stuck-at-fault test consist of one vector. Each vector applied at slow speed (DC-scan).

! Timing related faults need two vectors and they are to be applied on consecutive clock cycles (at normal clock speed) (AC-scan)

! At test: ! Vector V1 is applied to set the circuit in its state! Vector V2 is applied

! Response is captured

! Three approaches: ! Launch-on-capture

! Launch-on-shift! Enhanced scan

Launch on shift (LOS) and launch on capture (LOC)! Launch on capture (broadside or double capture)

! shift in test stimuli (usually at low speed). For an n-bit shift register, shift in n bits.

! apply a capture to create transition! apply another capture cycle to capture the response

! Launch on shift (skewed load) ! shift in test stimuli (usually at low speed). For an n-bit shift register,

shift in n-1 bits at low speed. ! The final bit is shifted at high speed and then a capture is applied in

high speed.

45

LOS and LOC

46

DC scan

LOC

LOS

SE

CLK

SE

CLK

SE

CLK

Enhanced Scan

FFMUX

CLK

SE

Q

SO

DSI

SFF

SE: Scan enableSI: Scan inputSO: Scan output

CLK

SE

QDSI

SFF

CLK

SE

QDSI

SFF LAQ

CD

SO

UPDATE

Enhanced Scan

Combinational logic

CLK

D

SISE

SFF LA

UPDATE

CLK

SISE

SFF LAQ

CLK

SISE

SFF LAQ

SO

CLK

D DQ

PI PO

References

! A. Kobayashi, et al., A flip-flop circuit suitable for FLT, Annual Meeting of the Institute of Electronics, Information and Communication Engineers, Manuscript 892, p. 962, 1963 (in Japanese).

! T. W. Williams and J. B. Angell, Enhancing testability of large scale integrated circuits via test points and additional logic, IEEE Transactions on Computers, Vol. C-22, No. 1, pp. 46-60, 1973.

! E. B. Eichelberger and T. W. Williams, A logic design structure for LSI testability, Proceedings of the 14th Design Automation Conference, pp. 462-468, 1977.

! H.Ando, "Testing VLSI with Random Access Scan," COMPCON80, pp.50-52, 1980. J. Savir and S. Patil, "Broad-Side Delay Test," IEEE Trans. Computer-Aided Design, Vol. 13, No. 8, pp. 1057-1064, Aug. 1994.

! J. Savir and S. Patil, "On Broad-Side Delay Test,"IEEE Trans. Very Large Scale Integration Systems, Vol. 2, No. 3, pp. 368- 372, Sep. 1994.

! Dervisoglu, B. I. and Stong, G. E., “Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement”, Proceedings of the IEEE International Test Conference on Test, 1991, pages 365--374.

49

Summary

! DfT – design for test – makes a design easier to test. It can be to ease test generation and/or to ease test application (application of test vectors).

! Test point insertion aims at improving controllability and observability of a design. Improving controllability and observability makes it easier to generate test vectors.

! Scan technique adds a test mode to the circuit. In test mode, the circuit behaves as if it was combinational. In normal mode, the design behaves as normal. The advantage is that it eases test generation (ATPG for combinational circuits can be used). It also makes it easier to apply vectors.

design for test of digital systems tddc33tddc33/lecture/tddc33_10_le3.pdf · making electronic...

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