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DESIGN GUIDELINES FOR THE FABRICATION AND TESTING OF HIGH
SPEED INTERGRATED CIRCUITS
Final Report
Derek Ho
System-On-Chip Research LaboratoryThe University of British Columbia
August 13, 2004
ii
ABSTRACT
“Design Guidelines for the Fabrication and Testing of High-speed Integrated Circuits”
By Derek Ho
This document contains design guidelines for high-speed integrated circuits (ICs) testing
and fabrication for the System-on-Chip Research Laboratory at UBC. The guidelines help
the IC developer to greatly increase the chance of producing a successful IC.
The importance of proper test measurements cannot be overemphasized. There is no
reason for fabricating a chip if it is not to be tested. Non-ideal physical characteristics can
occur to hamper the circuit in the sophisticated CMOS fabrication process involving
printing, masking, etching, implanting, and chemical vapor deposition. Proper testing
involves not only getting the right equipment, but planning which measurements are
performed; constructing the test setup properly; knowing how to conduct the tests;
knowing how to interpret the results; and last but not least, designing the circuit such that
it can be tested. Hence, a good test plan early on in the design phase is the key to
successful testing.
The IC designer must be careful in choosing between different types of chip packages. A
bare die must be handled with special techniques. Die on glass can be probe-tested, but
the probing pads must have the right pitch and signal arrangement as the probes in the
SOC lab. A fully packaged chip requires a fixture board to interface between the pins and
the probe.
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A chip does not function with improper input/output (I/O) circuits. Input circuits may
contain electrostatic discharge (ESD) protection to prevent a sudden rush of charge from
damaging the chip core. Output circuits may contain large buffers to drive an external
load, such as a wire on a printed circuit board. If a coaxial transmission line is used in
testing, the output buffers must be designed to drive 50 Ω. Only two libraries in the
CMOSP18 design kit have I/O circuits. The CMC Shared Library contains several cells
that include, for example, analog pads with ESD protection. The Virtual Silicon Library
contains buffered I/O circuits.
The parametric or functional failure of chips can occur as a result of electrostatic
discharge (ESD). Static electricity builds up on a human body or machine and can easily
damage static-sensitive internal circuits. Static discharges too small to be felt by a human
can cause permanent damage to ICs. A typical simulation technique based on the Human
Body Model is presented. The model states that ESD rise time is approximately 10ns and
the decay time is around 150ns. When the waveform is realized with physical
components, a 100-pF capacitor with an initial voltage of 2-kV can be used to drive the
IC’s input through a 1.5kΩ resistor.
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TABLE OF CONTENTS ABSTRACT......................................................................................................................... i
TABLE OF CONTENTS................................................................................................... iv
LIST OF ILLUSTRATIONS.............................................................................................. v
GLOSSARY ...................................................................................................................... vi
LIST OF ABBREVIATIONS.......................................................................................... viii
ACKNOWLEDGEMENTS............................................................................................... ix
1.0 INTRODUCTION ........................................................................................................ 1
2.0 PRE-DEVELOPMENT CONSIDERATIONS............................................................. 3 2.1 THE IMPORTANCE OF TESTING.................................................................................................... 3 2.2 SCHEDULING FOR CHIP DEVELOPMENT ................................................................................... 4 2.3 TEST PLANNING ............................................................................................................................... 6
2.3.1 The Test Plan................................................................................................................................. 6 2.3.2 Testability Checklist ...................................................................................................................... 9
3.0 CHIP INPUT/OUTPUT CONCEPTS ........................................................................ 12
4.0 CONDUCTING THE TEST....................................................................................... 18 4.1 TEST PREPARATION .......................................................................................................................18 4.2 INITIAL FUNCTIONAL TESTING ..................................................................................................18 4.3 HANDLING LOOSE DIE...................................................................................................................19 4.4 WAFER PROBING.............................................................................................................................20
5.0 ELECTROSTATIC DISCHARGE (ESD) ................................................................. 23
5.1 ESD BASICS ......................................................................................................................................23 5.2 STATIC-SAFE WORK PROCEDURES ............................................................................................24 5.3 ESD SIMULATION TECHNIQUES..................................................................................................25
6.0 CONCLUSION........................................................................................................... 27
APPENDIX A: CADENCE ENVIRONMENT TIPS ...................................................... 28
APPENDIX B: CADENCE SIMULATION TROUBLESHOOTING ............................ 31
APPENDIX C: SKILLS ACQUIRED THROUGH THE PROJECT............................... 32
REFERENCES ................................................................................................................. 34
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LIST OF ILLUSTRATIONS FIGURES Figure 1: Physical Location of Core and Ring.................................................................. 12
Figure 2: Pad and I/O Cell ................................................................................................ 13
Figure 3: PADIZ40 and PADIOZ40 Usage...................................................................... 16
Figure 4: Probe Station and DUT ..................................................................................... 20
Figure 5: ESD Simulation Circuit..................................................................................... 26
TABLES Table 1: Choosing Chip Package........................................................................................ 7
Table 2: Cell Libraries ...................................................................................................... 29
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GLOSSARY Black Box Cell
Cadence
Cellview
CMOSP18
Design Rule Check
Die
HSPICE
An abstract representation of a circuit. Analogous to software
encapsulation, only the input/output behavior and physical
dimensions are known to the developer. When a chip is fabricated,
CMC replaces this phantom with the actual implementation.
A set of CAD tools for designing digital and analog integrated
circuits.
An abstract way of presenting a certain aspect of a circuit in a
CAD tool, e.g. layout, abstract, and extracted.
A semiconductor circuit fabrication technology with a minimum
gate width of 180-nm.
A stage of integrated circuit development when a design is
analyzed against rules to verify the correctness of a design.
A semiconductor wafer cut into rectangular pieces.
A SPICE type simulator.
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Layout versus
Schematic
Netlister
Parasitics
Passivation
Ring
Synopsys
A stage of integrated circuit development when a layout of a
circuit is compared to its schematic to verify the correctness of the
layout.
A software module that builds a netlist based on a schematic or a
hardware description language.
A term for the collective unwanted resistances, capacitances, and
inductances presents in a circuit due to physical properties, instead
of as part of the designed circuit.
A layer of glass, usually Silicon Nitride, deposited on top of a die
for protection.
The outer part of the die which houses the I/O circuits,
surrounding the core.
A CAD tool for high-level synthesis and simulation of digital
circuits.
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LIST OF ABBREVIATIONS CAD Computer Aided Design CMC Canadian Microelectronics Corporation CMOS Complementary Metal Oxide Semiconductor DC Direct Current DRC Design Rule Check DUT Device Under Test ESD Electrostatic Discharge
GSG Ground-Signal-Ground IC Integrated Circuit I/O Input/Output LVS Layout Versus Schematic PCB Printed Circuit Board RFI Request For Implementation RFM Request For Manufacturing SA Spectrum Analyzer SNR Signal-to-Noise Ratio SOC System On Chip VNA Vector Network Analyzer VST Virtual Silicon Library
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ACKNOWLEDGEMENTS
I would like to thank Dr. Shahriar Mirabbasi, Assistant Professor at UBC, for providing
me with an excellent learning opportunity in analog IC development; Zaman Mollah,
MAsc candidate, for his help with Cadence; and last but not least Dr. Roberto Rosales,
SOC Test Lab Manager, for his mentoring throughout the project.
Derek Ho
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1.0 INTRODUCTION
The development of high-speed Integrated Circuits (ICs) is a sophisticated process,
within which some challenging stages are often overlooked by IC developers. This
document attempts to raise IC developers’ awareness of such stages by exposing them to
practical issues in testing, I/O, and fabrication. This document is a compilation of
otherwise scattered and unwritten techniques into a set of design guidelines which the IC
developers can use to ensure the proper operation of their circuits and high development
productivity.
The guidelines are primarily created for IC developers who already have a basic
understanding of high-speed analog circuits. However, anyone interested in testing
devices can benefit from it. This document includes many web references and
supplements as well as summarizes the relevant material found in the references. The
reader is encouraged to examine these references if further clarification is needed.
The remainder of this document is organized as follows. Section two describes important
considerations in the initial stage of IC development. Section three presents chip I/O
concepts. Section four discusses how circuit tests can be performed effectively. Section
five introduces electrostatic discharge (ESD) and how to avoid damage to an IC.
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The appendices provide additional information regarding the hands-on use of computer
aided design (CAD) tools and other experiences. Appendix-A provides tips on the
Cadence environment to facilitate efficiency. Appendix-B reviews solutions to common
Cadence problems. Appendix-C documents the skills learnt in the course of producing
the design guidelines.
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2.0 PRE-DEVELOPMENT CONSIDERATIONS Being aware of key IC testing issues and planning how a chip can be tested in the
beginning of development can contribute significantly to the success of the circuit. This
section describes the importance of testing, proposes a schedule for chip development,
and offers suggestions on test planning.
2.1 THE IMPORTANCE OF TESTING
The importance of proper test measurements cannot be overemphasized. A design is of
no value until it is tested and proven to work. Non-ideal physical characteristics can
occur to hamper the circuit in the CMOS fabrication process involving printing, masking,
etching, implanting, and chemical vapor deposition [1]. Some circuits can be verified
without physical verification. For example, digital architectural designs can be simulated
or downloaded onto a field-programmable gate array. However, proof-of-concept circuits
must be tested.
Proper testing involves obtaining the right equipment; planning the measurements to be
performed; constructing the test setup properly; knowing how to conduct the tests;
knowing how to interpret the results; and last but not least, designing for testability
(DFT). In this context, DFT refers to designing a circuit so that its inputs can be
controlled and output can be observed easily. A good test plan early on in the design
phase is the key to successful testing. Obtaining the best measurement results requires a
good understanding of measurement system components and their interactions.
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2.2 SCHEDULING FOR CHIP DEVELOPMENT
The material in this subsection is based in part on Canadian Microelectronics
Corporation’s guide to fabrication, reference [2]. The following checklist describes the
tasks associated with chip fabrication from submitting a chip to CMC to testing it when
the chip is sent back. The entire process takes several months. Beware of all deadlines.
Fabrication Checklist
Fabrication Steps Step
Completed (Tick here)
1. Register with CMC. Write down user name and password.
2. Select a Fabrication Technology and Packaging (Consult your
supervisor)
3. Choose Preferred Payment Scheme (Consult your supervisor)
4. Pick a Fabrication Run
5. Select a Design Name (Consult the SOC CAD engineer)
6. Plan Chip Testing and Design for Testability
7. Submit Request for Manufacturing (RFMR)
8. During Design, use the CMC DRC
9. Submit an RFI and Final Design Data to CMC
10. Watch for CMC's Manufacturing Check Message
11. Monitor Chip Shipping Forecast Dates, Prepare for Testing
12. Test the chip and submit a Testing Results Report to CMC
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One common reason for missing a fabrication run deadline or creating a chip which
eventually does not work is that a designer does not allow sufficient time for both layout
creation and verification. The CMC submission date is the last opportunity for submitting
a chip. If there are any problems, there is no time for feedback and repair. Designers are
encouraged to submit their chip in advance of the deadline so that there is enough time to
take corrective action if CMC finds any problems with the data or chip layout. At the
very minimum, allow a week for corrections. Important details for steps 8 and 9 of the
checklist are provided below:
8. During Design, use the CMC DRC Service
CMC has a Design Rule Check service that is accessible via the Internet to authorized
designers. Design files are uploaded and CMC authenticates the source and performs a
DRC on the design and makes the results available to the designer, typically within one
business day or less.
During chip design, the CMC DRC service should be used for information on DRC
violations, data compatibility with CMC CAD systems, and confirmation that large
design files are submitted error-free. See CMC’s fabrication service documentation,
reference [3], for instructions on using the DRC service.
9. Submit an RFI and Final Design Data to CMC
A completed Request for Implementation (RFI) form must reach CMC by the submission
deadline. The RFI documents the final design and is mandatory, whether or not an RFMR
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has been previously submitted. Since the RFI includes designer names and packaging
information and lists any intentionally violated design rules, it is an essential document
that CMC uses to qualify designs for fabrication and to contact designers when necessary.
2.3 TEST PLANNING This section discusses the planning of circuit tests (section 2.3.1) and presents a checklist
to simplify the IC developer’s work (section 2.3.2).
2.3.1 The Test Plan
A test plan should be developed early on in the design phase so that the chip can be
designed for testing. It is strongly recommended that the plan be written. Below are
guidelines for generating test plans:
1. Decide the number of Input/Output and Power pins required.
2. Decide the frequency range, voltage and current levels.
3. Decide if the design is to be packaged and fixtured or probe-tested.
4. Determine if electrostatic discharge protection is required in the I/O.
5. Design for chip diagnostics including test structures for characterization, and
access to signals of interest.
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6. Decide the type of package required based on the frequency range and the number
of pins. Table 1 on the next page helps the designer to decide what packaging
should be used.
Packaging Implications Lose/Bare die • You must know how a die can be handled.
• It can be probe-tested but the probing pads must have the
right pitch (100µm and 150µm) and signal arrangement as
the probes in the SOC lab.
• Frequency: 0 – 40 GHz.
• Total pins: 2, 6, 8, 12.
Die on glass • It can be probe-tested but the probing pads must have the
right pitch (100µm and 150µm) and signal arrangement as
the probes in the SOC lab.
• Frequency: 0 – 40 GHz.
• Total pins: 2, 6, 8, 12.
Fully packaged • A fixture board is needed to interface between the pins
and the cables. Verify that the board is available or plan to
design your own.
• Frequency: 0 – 300 MHz.
• Total pins: 12, 24, 80, 120.
Note: Please ask for only the necessary type of package.
Table 1: Choosing Chip Package
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The test plan also includes considerations regarding simulation and equipment, listed on
the next page.
• Ensure that the simulations can be verified through measurements and vice versa
by:
o Ensuring that you have included appropriate models in your chip
simulation (e.g., pad parasitics, bond wire, package, fixture, coupling,
probe inductance).
o Designing for same loads as experiments.
o Accounting for temperature and power supply variations in your
simulation.
o Simulating all the tests that you expect to perform and generating plots for
easy reference.
• Decide the type of test, identify equipments required, their cost and accessibility.
• For wafer-probing, determine the number of probes required and whether or not
the probe station is available.
• Talk to the test lab manager to identify equipments required. The three main
analog instruments are the network analyzer, spectrum analyzer, and synthesized
signal source. See CMC’s High-speed Circuit Test Guide, reference [4], for
additional information.
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2.3.2 Testability Checklist
This checklist, partial taken and adapted from [5], is intended to help designers appreciate
the requirements and pitfalls associated with designing and testing a chip using the CMC
environment. It contains a number of important issues in creating a testable device and in
obtaining access to the necessary test equipments.
Who is to perform the testing ___________________________________ When (month/year) ___________________________________ For how long (number of weeks)
[includes training, setup, building custom fixtures]
___________________________________
Level of support from staff ___________________________________ List tests to be performed: ___________________________________
___________________________________ ___________________________________ ___________________________________ ___________________________________ 1. Test and Equipment Considerations Range of Operation of I/O on your chip (please check one in each row) (From left to right, categories range from simple-moderate-difficult-very difficult) For analog functions: _<10MHz _10MHz-500MHz _500MHz -2GHz _>2GHz _0.1-10V _1-100mV | >10V _1-1000uV | >30V _<1uV | >100V For digital functions: _<20MHz _20MHz -500MHz _500MHz-1GHz _>1G Hz _0.5-10V _1-500mV _<1mV
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Tests of Interest (check any that apply) For analog functions: _ time domain _ S-Parameters _ SNR _ frequency domain other ___________________________ For digital functions: _ functional _ parametric
_ BER _ jitter
Common Test Equipment Considerations:
• How many digital pins are on the chip and what are their logic types (e.g., 20
CMOS & 8 ECL)?
• Do you know what specific test equipment is required (e.g. IMS XL60, high-
speed digital scope, logic analyzer, 81200 Bit Vector Rate Tester)?
• Can the test equipment meet your requirements in terms of logic level, number of
channels, speed, supply voltages, noise, and precision.?
• Where is the equipment that you plan to use located (available in the SOC test
lab)?
• Are you likely to have access to the test equipment during the time that you will
need it?
2. Packaging and Fixturing
• Which package is suitable (e.g., bare die, 120-pin CFP)?
• What fixturing is used to interface to the test equipment (e.g., CMC PCB-Test
Fixtures, Custom PCB)?
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3. Design and Simulation
Design Factors
• Do you know the expected external capacitive load per signal (e.g., 20pF)?
• Do you know the expected external resistive load per signal (in ohms)?
• Do you require I/O pads with controlled impedance?
• Have you included ESD protection in the I/O?
Simulation
• Have you included the appropriate models in your chip simulation (e.g., I/O pads,
bond wire, package, socket, fixture, coaxial cable, and tester) when the off-chip
frequency is higher than 20-MHz?
• Have you allowed for process, temperature and power supply variations in your
simulation?
• Have you simulated all the tests that you expect to perform?
• If you have used digital DFT, do you know your expected fault coverage?
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3.0 CHIP INPUT/OUTPUT CONCEPTS
A chip does not function with improper input and output (I/O) circuits. Input circuits may
contain electrostatic discharge (ESD) protection diodes to prevent a sudden rush of
charge from damaging the chip core. Output circuits may contain large buffers to drive
external loads, such as a wire on a printed circuit board. If a chip is to be tested, the
output buffers must be designed to drive 50 Ω. At high frequency, the characteristic
impedance of the SMA coaxial transmission line is 50 Ω. The input impedance of the test
equipments is designed to also be 50 Ω, preventing reflection. Note that there is no
voltage drop across the cable. Before proceeding to the next subsection, it is important to
clarify some terminology:
Core vs. Ring
The core is located in the centre of a chip where components implement the target
function of the circuit. The ring surrounds the core and is located in the outer part of the
chip as in figure 1. It houses the I/O circuits. In the 180-nm technology, the core is
usually powered by 1.8V while the ring is usually powered by 3.3V.
Figure 1: Physical Location of Core and Ring
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Pad vs. I/O cell
A pad is a relatively large piece of metal used for landing a bond wire or a probe. Pads
are usually of multiple layers of metal as the landing may damage the top layers. For this
reason, circuits should not be laid out under pads. An I/O cell is where buffers or other
I/O related circuits are located. Both pad and I/O cells are placed close together as in
Figure 2.
Figure 2: Pad and I/O Cell
Probing pad vs. Bonding pad
Probing pads are the landing sites for the measuring probe. They are larger and further
apart than bonding pads. The probes in the SOC lab are 100µm or 150µm apart. Bonding
pads, used for packaging, connect to a wire which leads to the IC’s pins.
Pitch
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Pitch is the distance between the centers of two pads.
Black Box Cell
A Black Box Cell is an abstract representation of a circuit. Analogous to software
encapsulation, only the input/output behavior and physical dimensions are known to the
developer. All I/O cells are in the form of black box cells. When a chip is fabricated,
CMC replaces this phantom cell with the actually implementation. To use them, please
go to Cadence’s icfb command console, choose the CMOSP18 Documentation menu, and
move to the section titled, “How to Use Black-Box Cells from VST Libraries
(vst_n18_sc_tsm_c4 and tpz973g)” under the heading, “CMOSP18: VIRTUAL
SILICON TECHNOLOGY (VST) LIBRARIES.”
The subsequence part of this section describes the I/O related circuits available with the
CMOSP18 fabrication technology. Only the CMC Shared Library (CMCShare) and the
Virtual Silicon Library (tpz973g) contain usable IO cells.
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The Virtual Silicon Library
The Virtual Silicon Library is intended for digital ICs. Below is a list of the IO cells it
contains:
• 3-State Output 66Mhz PCI Buffer Pad with Input and Limited Slew Rate, 5V-
Tolerant
• High Drive, Internal CMOS Clock Buffer
• High Drive, Internal Schmitt Trigger Clock Buffer
• Very Fast, Internal Clock Buffer
• Corner Pad
• CMOS 3-State Output Pad with Input, 5V-Tolerant
• High Drive, CMOS Input Clock Pad, 5V-Tolerant
• CMOS 3-State Output Pad with Input and Pulldown, 5V-Tolerant
• CMOS Output Pad
• High Drive, Schmitt Trigger Input Clock Pad, 5V-Tolerant
• CMOS 3-State Output Pad, 5V-Tolerant
• Input Pad With Pullup, 5V-Tolerant
• Schmitt Trigger Input Pad, 5V-Tolerant
• CMOS 3-State Output Pad with Input and Pullup, 5V-Tolerant
• CMOS 3-State Output Pad with Input, Pullup, and Limited Slew Rate, 5V-
Tolerant
• Vdd Pad
• Vss Pad
16
An application note for this library is available. It states that there are two types of pads
in the library, PADIZ40 and PADOZ40, used for inner bonding pads and outer bonding
pads respectively. The terms inner and outer refer to the physical locations of the pads in
a two row array layout within the I/O ring. The inner pads are closer to the core while the
outer pads are closer to the edge of the package. Figure 3 shows the different pads’ usage.
Figure 3: PADIZ40 and PADIOZ40 Usage
The Analog Pad Library
The CMC Shared Library contains analog pads which are physically compatible with I/O
cells from the tpz973g library and is suitable for power and input/output signals. All the
cells in the CMC shared library are designed by researchers at CMC member universities.
Some designs are not tested in the SOC lab and therefore the correct functionality is NOT
guaranteed at the time of this writing. The next page shows the useful cells in the CMC
shared library.
17
PANALOG analog pad, no ESD protection, compatible with IO cells from
tpz973g library, suitable for power or output signal
PANALOGESD analog pad with ESD protection diode pair, compatible with IO
cells from the tpz973g library, suitable for power and input/output
signals
PANALOGESDR analog pad with ESD protection diode pair and a poly resistor of
187 Ω on the signal path, compatible with IO cells from tpz973g
library, suitable for input signal if impedance acceptable
PFILL filler cell for short IO cells
PSHORT shorter version of PANALOG, wide signal path good for dedicated
core power
PSHORTESD shorter version of PANALOGESD
PSHORTESDR shorter version of PANALOGESDR
PVDDSHORT vdd pad connected to VDDRING
PVSSSHORT vss pad connected to VSSRING
ndiode/pdiode diodes used for ESD protection
If you need to design your own I/O cell, the paper in reference [6] by A. B. Dowlatabadi
presents a robust, load-insensitive pad driver, which may serve as a good reference.
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4.0 CONDUCTING THE TEST
This section advises the IC developer of the tasks to be performed upon receiving the
chip from the fabrication plant. The material is based in part on CMC’s High-speed
Circuit Test Guide, reference [4]. It is recommended that the IC developer to have a good
understanding of this material in the design stage so as to increase the chance of a
successful chip.
4.1 TEST PREPARATION
There are many considerations during the preparation phase of testing, for example, the
actions to be taken if equipments are not available. A list of tasks that take additional
development time and should be accommodated in the project schedule are provided as
follows:
• Custom parts may be built.
• Codes may be written to control instruments.
• Equipments may be purchased. Please consult with the SOC test lab manager.
4.2 INITIAL FUNCTIONAL TESTING
Rather than performing elaborate tests from the beginning for all specifications on all
chips, functional tests can be performed to verify whether or not the chips work, and if
19
so, which chips are worthy of further characterization. For amplifiers, a good starting
point is to check for gain and proper matching for each chip for the same bias. Make a
note of bias conditions and current draw for each chip and save or plot the displayed data,
especially for the chips with good performance. Save the results of the first measured
chip as a reference. If de-embedding structures are included on each chip, these should be
measured only after the best performing chip is identified.
If a chip fails a functional test, further tests may prove useful in diagnosis, such as a
closer examination of the layout. Be sure to check for opens and shorts in the layout
particularly where several metal layers are involved or metal is hidden by layers above.
4.3 HANDLING LOOSE DIE
Normal die should be handled by tweezers to prevent contamination of the die attach
surface. The brittleness of both silicon and GaAs makes the sharp edges of the chip
susceptible to damage if too much pressure is applied. A good precaution when handling
a die is to use very sharp tweezers with excellent point alignment. The surface of the die
is protected with a layer of silicon nitride passivation which provides sufficient scratch
protection.
When probing, several loose die can be mounted on a glass slide (die on glass) for ease of
handling. Alternatively, a die can be mounted on a conductive surface to provide a
reference ground plane (die on conductive glass), particularly if the die has a metal
20
backplane. Keep in mind that the devices should be characterized in an environment that
is similar to the model, for instance, using a conductive surface as opposed to glass for
mounting the loose die.
4.4 WAFER PROBING
To facilitate wafer probing, a wafer probe station and microwave probes are required.
Figure 4 shows a probe station and its various parts.
Figure 4: Probe Station and DUT
A microwave probe can be viewed as an adapter from the coaxial cables to the pads. It
can cause losses, reflections, and crosstalks. However, the tolerable level of losses or
reflections is relatively high when using the probes with, for example, a calibrated
21
network analyzer. The designer should be aware of the issues introduced by probing,
listed as follows:
• If significant signal power is radiated from the probe, the probe losses are not
typically repeatable. This is because the wafer, wafer chuck, or other conductors
are moved in relation to the probes, causing changes in the radiation impedance.
• The isolation or crosstalk between the input probe head and the output probe head
changes significantly between calibrations and measurements, due to the position
of the probe heads relative to each other and the wafer chuck. Isolation decreases
with higher frequency and closer spacing between probes.
• Crosstalk may be observed as capacitive or radiative coupling between probes,
common ground inductance in DUT, or mutual coupling between signal lines
within a probe. In practice, limiting the crosstalk between probe lines is simpler
and more accurate than attempting to correct it. The ground plane on either side of
the signal line on Ground-Signal-Ground (GSG) probes help provide greater
isolation. Typically, probe crosstalk for the GSG and SG probes are 40-dB and
20-dB respectively.
Successful gigahertz probing requires that consideration be given to layout and design
before design completion and fabrication. To facilitate probing, the design must satisfy
mechanical rules relating to spacing (pad size, pitch, and GSG depending on probe,
22
passivation window, parallel row and spacing) as well as electrical rules (probe ground,
chip grounds connected).
For general information on installing the probe head, microscope viewing, probing
procedure and issues, please see CMC’s Wafer Probing Guide (reference [7]). For
information on test equipments in the SOC lab, please contact the SOC lab manager.
23
5.0 ELECTROSTATIC DISCHARGE (ESD)
The designer should be aware of electrostatic discharge as it can potentially damage a
chip. This section starts from describing some basic concepts about ESD and moves into
how it can be avoided. Finally, a technique for simulating ESD is presented.
5.1 ESD BASICS
Basic ESD concepts are described in Hewlett-Packard’s documentations, references [8-
9], and hereby summarized. Parametric or functional failure of chips can occur as a result
of electrostatic discharge (ESD). Failures in bipolar transistors are characterized by low
breakdown voltage or high leakage current, while failures in Field-Effect Transistors are
characterized by resistive shorts. Static electricity builds up on a human body or machine
and can easily damage static-sensitive internal circuit elements. Static discharges too
small to be felt by a human can cause permanent damage to ICs. Devices such as
calibration components and DUTs can also carry an electrostatic charge. Static discharge
is often associated with people, the types of material or clothes worn, and the handling
equipment that comes into contact with semiconductor devices. A few simple precautions
can help prevent chip damage resulting from ESD.
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5.2 STATIC-SAFE WORK PROCEDURES
A partial listing of static-safe work procedures used in the SOC lab is as follows:
1. For work stations and areas: (i) Use grounded conductive mats and plates over
non-conducting surfaces (ii) Make sure conductive surfaces are grounded (iii) If
necessary, use grounded floor mats.
2. For operator clothing: (i) Use wrist grounding strap (10 MΩ ground) (ii) When
using a grounded mat, use foot-grounded straps on leather soles (iii) Control of
personal clothing may be necessary.
3. For manipulation of dice: (i) Use conductive bags and wrapping (ii) Eliminate the
use of bubble pack (iii) Use metallic tweezers. Be sure to follow point 1 and 2
immediately above.
4. For test areas: Avoid high velocity gas flow over assemblies and parts.
5. Ground yourself before you clean, inspect, or make connections to a static-
sensitive device or test port. You can, for example, grasp the grounded outer shell
of the test port briefly to discharge static from your body.
6. Discharge static electricity from a device before connecting it. Touch the device
briefly (through a resistor of at least 1MΩ) to either the outer shell of the test port
or to another exposed ground. This discharges static electricity and protects test
equipment circuitry.
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The sometimes overlooked aspects are as follows:
1. Remember to reattach ground straps after returning from breaks before handling
any susceptible parts.
2. Be sure that the wrist strap is securely attached to the wrist. Wrist straps do not
work when attached over clothing.
3. Do not wear clothing made of materials which tend to generate high electrostatic
potentials such as synthetics, wool, or silk.
4. Alligator clips or any other kind of quick-disconnect fasteners tend to fall off
easily. Please do not use them.
5. Ensure that ground cords are not tangled or knotted.
6. Do not allow wrist straps to become corroded or dirty from excessive use. They
must be cleaned or replaced regularly.
7. If wrist strap is connected to the circuit ground on the front panel of an
instrument, make sure the instrument is plugged.
5.3 ESD SIMULATION TECHNIQUES
CMC claims that pads with ESD protection are available in the CMCshare library.
However, the functionality and effectiveness of these pads have not been verified by the
SOC lab. The following describes how simulations can be performed to test ESD
protection when an IC designer decides to built an ESD protected circuit.
26
In Amerasekera and Duvvury’s book, reference [10], a simulation technique based on the
Human Body Model is presented. Figure 5 shows the schematic of the ESD simulation
circuit. The model states that ESD rise time is approximately 10-ns and the decay time is
around 150-ns. When the waveform is realized with physical components, a 100-pF
capacitor with an initial voltage of 2-kV can be used to drive the IC’s input through a 1.5-
kΩ resistor.
Figure 5: ESD Simulation Circuit
If a software simulator is used, a pulse-voltage source, vpulse in the analogLib library,
can be used in place of the capacitor. Simply use 10ns as rise time, 150ns as the fall time,
2000-V as voltage2, 1000 seconds as period, and 0 as delay. The positive terminal of the
source then connects to a 1.5-kΩ resistor, which in turn connects to the input of the IC.
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6.0 CONCLUSION
This document assembles and discusses useful guidelines that are otherwise unavailable
in a single source. It covers issues on testing planning, I/O selection, and ESD protection
of high-speed ICs. The information helps the IC developer to build circuits that work and
save time. Developers of high-speed integrated circuits can thus bring their chips up to
new performance and reliability standards.
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APPENDIX A: CADENCE ENVIRONMENT TIPS
Cadence is a powerful and sophisticated CAD tool; therefore, much knowledge is
required to use it efficiently. The inexperienced user might spend much time getting
familiar with Cadence’s way of operating. This section is designed to ease the burden on
CAD tool use, hence increasing productivity.
Important Guidelines:
• Any wire that connects to the voltage source Vdd must be labeled “Vdd!.”
Similarly, any wire that connects to the ground Gnd must be labeled “Gnd!.”
Otherwise, simulation fails.
• A device model must be supplied to Cadence for simulation. In Analog Artist
Environment Include Files, type the following path to link Cadence to the
model files.
• Spectre Model:
/CMC/kits/cmosp18/models/spectre/spectre445_mixed/mm018.scs
Use “tt” for the Type.
• SpectreS model:
/CMC/kits/cmosp18.4.5/models/spectre/icfspectre.init
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• If a cellview is to be modified, it must be copied to the users’ own library for
editing, i.e. to open in WRITE mode.
• ssh-linux.ece.ubc.ca is currently a cluster of Linux servers in the department with
the most computation power for simulations.
• To launch Cadence from different operating systems:
Linux: /CMC/cad/bin/cdslnx -t cmosp18 -w <user directory>
Unix: /CMC/cad/bin/cds -t cmosp18 -w <user directory>
Some useful cell libraries are presented in table 2.
Libraries Details analogLib Discrete Analog Component Library
vdd GLOBAL Voltage Source, initialized in Analog Artist gnd Circuit Ground vdc DC source, setup up done on schematic vpulse Pulse Width Modulated Voltage Source res Resistor cap Capacitor
tpz973g Digital Pad Library Path on Server: /CMC/kits/cmosp18/VSdir/dfII_lib/tpz973g
CMCshare Analog Pad Library pCell Programmable Transistor Cell
Used for layout (Ask the SOC CAD Engineer)
Table 2: Cell Libraries
CMC documentations on tpz973g and CMCshare can be accessed via Cadence, located at
Main Console (icfb) CMOSP18 Documentation
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Online Cadence Tutorials:
• Cadence Tutorial Web Ring
http://www.public.iastate.edu/~sampath/cadence_tutorials.htm
• Tutorial from University of Virginia
Best for beginners, covers DC, transient simulations, LVS, and layout
http://www.ee.virginia.edu/~mrs8n/cadence/tutorial1.html
• AC Analysis/ Frequency Response Simulation Tutorial
http://www.ami.ac.uk/courseware/adveda/spice/spex2/spex2.htmlh
• Detailed Layout Tutorial
http://turquoise.wpi.edu/courses/ee390x/examples/layout.html
• The only tutorial including Design Rule Check (DRC)
http://www.seas.upenn.edu/~eecad/cadence/cadence.html
• Tutorials covering the entire design flow, but with less depth
http://warga.et.tudelft.nl/cadmgr/dimos01Tutorial/
http://turquoise.wpi.edu/cds/
http://www.ee.ucla.edu/~matthews/cad_tut.htm
http://www.ee.vt.edu/~ha/cadtools/cadence/cadence.html
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APPENDIX B: CADENCE SIMULATION TROUBLESHOOTING
This appendix documents common errors or difficulties in the simulation process. The
solutions are based on the author’s experience. Note that the solutions may only be valid
for the Cadence setup at the time when this document is written.
Problem: Simulation runs fine but Cadence states that the output waveform cannot
be displayed. Solution: Make sure that the schematic is saved after the last change. Problem: Oscillating output does not oscillate, or it starts to oscillate near the END
of simulation time, no matter how long the time is. Solution: Check if the circuit is initialized properly. For this, use the Convergence
Aid window which can be accessed via the Tool menu.
Problem: Output signal is identical to 0V. Solution: If a symbol is used in the schematic, make sure the Switch List contains
“symbol.” This entry on the switch list is an ordered list of cellviews that contain information to be simulated. The Netlister searches until it finds one of these cellviews. The default entry does not contain an extracted cellview.
Problem: Output signal hovers around 0V, sometimes reaching several milli-volts. Solution: Make sure that the Global Source under the Stimuli menu is turn ON. Problem: Simulation takes too long to run. Solution: Turn OFF output ‘march’ or use SpectreS as opposed to HSPICE.
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APPENDIX C: SKILLS ACQUIRED THROUGH THE PROJECT
This document is the end product of an EECE 496 project. The area of this project which
involves analog integrated circuit development, CAD tool use, and VLSI related issues is
challenging to an undergraduate student, especially given the limited time when a large
amount of learning is necessary before project tasks can be performed. Below is a list of
skills acquired from working on the project.
Analog Design Flow
The full development cycle of integrated circuits was examined, in particular the stages
of Schematic Capture, Simulation, Layout, LVS/DRC. The purpose, deliverables, tools
involved, and possible difficulties in various stages were understood.
I/O Circuits
Input, output, and input/output circuits were studied. Simulations were run to verify their
analog characteristics. Output buffers, ESD protection, and 50Ω characteristic impedance
of the coaxial transmission line at high frequency were investigated.
Analog Design for Testability
Issues on design for testability was studied, such as the importance of tests and
measurements; test planning; conducting tests, for example, landing probes onto the die
at the probe station; and cables, connectors and tools used.
33
Fabrication
Investigated the procedures for submitting a design for fabrication, criteria for selecting
different packages, and high frequency issues.
Transistor Sizing
Speed Optimization with varying the width of the transistors’ gates. Understanding the
tradeoff between current driving capability, speed, silicon area, and input capacitance.
CAD Tools
The analog IC design flow, with stages such as schematic capture, simulation, layout, and
extraction, was studied with the hands-on use of the Cadence CAD tool. In particular,
three key components were used extensively. First, Virtuoso Composer was used to lay
individual transistors and making Symbols from sub-circuits. Second, Analog Artist was
used to run transient, DC, and AC circuit simulations with, Spectre, and SpectreS. Third,
Virtuoso Layout was used to extract from layouts.
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REFERENCES [1]
M. Burns and G. W. Roberts, An Introduction to Mixed-Signal IC Test and
Measurement, Oxford University Press, 2001, p. 5.
[2]
Canadian Microelectronics Corporation, “Guide to Fabrication”, 2004,
http://www.cmc.ca/prod_serv/des_fab_test/fab/guide_to_fab.html
[3] Canadian Microelectronics Corporation, “Fabrication Service Frequently Asked
Questions”, 2004, http://www.cmc.ca/prod_serv/des_fab_test/fab/
[4] Canadian Microelectronics Corporation, “High-Speed Circuit Test Guide”, 1999,
http://www.cmc.ca/prod_serv/des_fab_test/test/testguide/index.html
[5] Canadian Microelectronics Corporation, “Testing and Testability Checklist”, 2004,
http://www.cmc.ca/prod_serv/des_fab_test/test/test_checklist.html
[6] A. B. Dowlatabadi, A robust, load-insensitive pad driver, IEEE Journal of Solid-
State Circuits, vol. 35, pp. 600 – 665, April 2000
[7] Canadian Microelectronics Corporation, “CMC Wafer Probing Guide”, 2004,
http://www.cmc.ca/prod_serv/des_fab_test/test/testguide/testguide_2.5_wafer.html
[8]
Hewlett-Packard Company, Communications Components Designer's Catalog (HP
publication number 5966-0895E (9/97))
[9] Hewlett-Packard Company, HP 85033D 3.5 mm Calibration Kit
[10] A. Amerasekera and C. Duvvury, ESD in silicon integrated circuits, John Wiley &
Sons, 1995, p. 11.