design of a planar inductor for a low-profile dc-dc converter...imola | midterm workshop – ghent...

IMOLA | Midterm Workshop – Ghent – 15.04.2013. | J. Kundrata and A. Baric

Slide 1

Design of a planar inductor for

a low-profile DC-DC converter

J. Kundrata and A. Baric

Midterm Workshop


Slide 2

Outline

Inductor design challenges

Planar inductor designs:

Single layer design

Double layer designs:

● Parallel

● Serial

Layer stack up designs:

OLED cathode influence

Ferrite (FPC) layer application

Inductor design in geometrical parameter space

Electrical inductor modelling

Conclusion


Slide 3

Design challenges – OLED module geometry

The foil geometry requires a planar inductor structure

The OLED tile limits the available inductor area

The maximum inductance is determined by the inductor area

The OLED cathode is a conductive plane in proximity to the

inductor

It represents a GND plane mirroring the inductor currents

EXAMPLE

OLED SIZE

30 x 30 mm2


Slide 4

Design challenges – Inductor requirements

Operating frequency 10 MHz

Input voltage 40 V

Output voltage 7,4 V

Output current 340 mA

The driver chip characteristics

Inductance 3 – 5 µH

Resistance < 1 Ω

Port capacitance < 50 pF

Resonant frequency > 50 MHz

The inductor requirements

Electrical π-network model


Slide 5

Planar inductor design (I)

DESIGN CHALLENGE

Planar structure

Limited area

Spiral inductor design

Single layer design Double layer design

Parallel design

Serial design

Standard design

Alternating design

A reference design


Slide 6

Planar inductor design (II)

Single layer design

Double layer design

Serial, standard design

fr = 52,7 MHz

Ls = 0,582 µH Rs = 2,72 Ω

C1 = 15,1 pF

C1 = 43,2 pF

fr = 176 MHz

Ls = 0,232 µH Rs = 1,02 Ω

C1 = 15,3 pF

C1 = 15,4 pF

Double layer design

Parallel design

fr = 162 MHz

Ls = 0,235 µH Rs = 0,552 Ω

C1 = 25,1 pF

C1 = 23,2 pF

The second layer

inductor in series

The second layer

inductor in parallel


Slide 7

Planar inductor design (III)

fr = 99,4 MHz

Ls = 0,525 µH

Double layer design

Serial, alternate design

Rs = 2,15 Ω

C1 = 28,7 pF

C1 = 36,6 pF

Single layer design

fr = 176 MHz

Ls = 0,232 µH Rs = 1,02 Ω

C1 = 15,3 pF

C1 = 15,4 pF

Each turn of the first

and second layer

inductor in series


Slide 8

Layer stack up design (I)

DESIGN CHALLENGE

OLED cathode

near the inductor

Layer stack up design

Without the ground plane With the ground plane

Without the ferrite layers

With the ferrite layers A reference design


Slide 9

Layer stack up design (II)

FPC layer ([50 100] µm)

PET layer (200 µm)

FPC layer ([50 100] µm)

Adhesive layer (50 µm)

PET layer (200 µm) &

2 metallization layers

PET layer (200 µm)

Adhesive layer (50 µm)

+ OLED cathode

+ FPC layers


Slide 10

Layer stack up design (III)

“Ferrite Polymer Compound” FPC

Layer of ferrite granules (D ~ 10 µm) and polymer filler compound

Applicable ferrite materials:

NiZn

MnZn

CoZrO

CoNiFe

Fe/SiO2 compounds

Brandon et al., 2003


Slide 11

Layer stack up design (IV)

FPC application effects FPC thickness effects

OLED

cathode FPC

FPC


Slide 12

Inductor design in geom. parameter space (I)

1. Rectangular grid in w-s-R space

2. Identifying the basic

mathematical relationships

3. Mathematical modelling

4. Modelling analysis in DC-DC converter specific context

The modelling workflow:


Slide 13

Inductor design in geom. parameter space (II)

Qmax

high Q

C3,min

C3,min low C3 low C3

fr,min limit

Modelling results:


Slide 14

Electrical inductor modelling (I)

Simple π-network models

• Interport resistance

• Interport inductance

• Port capacitances

Expanded π-network models

• Interport resistance

• Interport inductance

• Port capacitances

+

• Resonant behavior

• Skin effect


Slide 15

Electrical inductor modelling (II)

Interport resistance Interport inductance

Simple

π-model

Expanded

π-model


Slide 16

Conclusion

The foil structure of the IMOLA concept substantially restricts

the inductor design options

The foil structure implies a planar inductor structure and the

OLED tile size limits the maximum available inductor area

The OLED cathode degrades the inductor inductance

The DC-DC converter sets a number of inductor requirements

Besides the single layer inductor designs, numerous double

layer designs are available with differing electrical properties

Application of ferrite to layer stack up can shield the inductor

from the OLED cathode

A procedure for inductor design in geometrical parameter

space is presented

A simple and an expanded π-models are presented

design of a planar inductor for a low-profile dc-dc converter...imola | midterm workshop – ghent...

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