design of dds system for alternating current field
TRANSCRIPT
American Journal of Engineering, Technology and Society 2018; 5(1): 5-10
http://www.openscienceonline.com/journal/ajets
ISSN: 2381-6171 (Print); ISSN: 2381-618X (Online)
Design of DDS System for Alternating Current Field Measurement Detection Instrument
Jiang Hu, Shang Kun Ren*, Dan Zhang
School of Measuring and Optical Engineering, Nanchang Hangkong University, Nanchang, China
Email address
*Corresponding author
To cite this article Jiang Hu, Shang Kun Ren, Dan Zhang. Design of DDS System for Alternating Current Field Measurement Detection Instrument. American
Journal of Engineering, Technology and Society. Vol. 5, No. 1, 2018, pp. 5-10.
Received: July 4, 2017; Accepted: December 29, 2017; Published: January 26, 2018
Abstract
In order to improve the intelligence and integration of Alternating current field measurement technology, an Alternating current
field measurement excitation source system based on Field Programmable Gate Array (FPGA) is designed. The design
principle of the excitation source system is the direct digital frequency synthesis, including the hardware circuit and the digital
circuit. The hardware circuit realizes the function of digital mode conversion and produces sine signal. The digital circuit is
programmed by hardware description language, which can be used to generate digital signals with adjustable frequency and
phase. The results of ModelSim software simulation and experimental test show that the excitation source system can produce
47.68 Hz-48.8 kHz sine wave signal and the frequency resolution is 47.68 Hz. When the frequency and phase of the
synthesized signal need to be adjusted, the synthetic signal parameters can be adjusted by the key. The system has the
advantages of high efficiency, intelligence and high integration.
Keywords
ACFM, DDS, FPGA, Nondestructive, Electromagnetic Test
1. Introduction
Alternating current field measurement (ACFM) technique
is an active electromagnetic nondestructive testing
technology based on the principle of electromagnetic
induction. The technique utilizes an inductive alternating
current which is uniformly distributed on the surface of the
inspected artifacts by means of a detecting probe of the
alternating current. When the surface defects of the artifacts
are detected, the defect size information is quantitatively
analyzed by measuring the variation of the disturbed induced
magnetic field, because of the disturbance of the uniformly
distributed inductive current caused by the change of
impedance. [1]. Compared with the traditional nondestructive
testing technology, the alternating current field measurement
technique has no need for special treatment on the surface of
the inspected workpiece, simply cleaning the inspected
surface; do not need any coupling agent, the detection
method is simple to operate, the detection result is intuitive,
the non-contact detection, the repeatability detection
performance is good, the detection equipment is easy to
carry, can carry on the real-time detection, suitable for the
complex inspection component and so on merit [2-3].
Therefore, the technology can be applied to aerospace, oil
pipelines, railway traffic and pressure vessels and other
industries, has a broad application prospects [4]. The ACFM
technique has a great difference in the excitation frequency of
different materials. The frequency control of conventional
excitation source module is cumbersome and difficult to meet
the application of ACFM system [5]. This paper designs a
Direct Digital Synthesizer (DDS) system based on FPGA in
order to solve the complexity of frequency regulation, and it
can be meet the ACFM system.
FPGA is a new type of high integration digital device,
which can meet the design of most special detection systems
[9]. Based on FPGA, this paper designs a DDS system with
adjustable frequency and phase. DDS system is realized by
direct digital frequency, and the synthetic signal is suitable
for different measured materials. DDS system can not only
6 Jiang Hu et al.: Design of DDS System for Alternating Current Field Measurement Detection Instrument
meet the needs of the alternating current field measurement
system, but also reduce the power consumption and cost of
the system. Moreover, the pin of FPGA is rich and the
storage area is big. FPGA can specially suits the spot real-
time detection system. FPGA design program portability is
good. Waveform storage table can choose sine wave,
triangular wave, square wave, sawtooth wave and other
waveforms to meet the other active detection equipment to
the excitation source demand.
2. DDS Theory
DDS or DDFS is the abbreviation for directly digital
frequency synthesis, the principle is to make a complete
period of the signal to be normalized, sampling enough
points to store, through the clock frequency Look up
waveform storage table address corresponding amplitude
output to high-speed digital-analog converter, the output of
the digital-analog converter after the Low-pass filter to
generate periodic signals [7]. Typical DDS systems include
phase accumulators, sine look-up tables, digital analog
converters and Low-pass filter components [8].
The value of the phase accumulator and the frequency
register is accumulated in the DDS system, and the
cumulative result is assigned to the phase accumulator.
According to the Nyquist-Shannon sampling Theorem, the
maximum number of bits of the frequency register plus one is
not allowed to exceed the number of bits of the phase
accumulator. The phase register intercepts the high-order
output of the phase accumulator.
The number of digits of the phase register corresponds to
the address of the waveform storage table. In fact, the
waveform storage table preserves the phase and amplitude
information of the periodic signal. The amplitude of the
waveform storage table corresponds to the input of the high-
speed digital-analog converter. Usually the frequency
registers and the phase accumulator are accumulated, and the
value of the phase register is output to the waveform storage
table. When the value of the phase register changes, the
phase and amplitude conversion is realized. So the number of
frequency registers actually controls the frequency range of
the synthesized signal.
Assuming that a sine wave signal is stored inN2 times,
the clock frequency is clkf , the synthetic frequency is of ,
and the synthetic signal cycle is oT . The clock frequency
lookup waveform stores every a addresses of the table and
the output address corresponds to the amplitude. A complete
cycle of the synthesized sine signal requires a N2 time look-
up table. The relation between the synthetic frequency and
the clock frequency can be expressed as:
NN
1 1
1 22
clko
o
clk
ff
T
f
= = =×
where of is the synthetic frequency, oT is the synthetic
signal period, clkf is the clock frequency,
N2 is the
sampling times. When the sampling clock frequency is
constant, the length of the known waveform storage table is
unchanged, and the signal of different frequencies can be
synthesized by controlling the size of each cumulative
frequency control word and changing the number of lookup
tables. As the number of N increases, the frequency
resolution of the synthesized sinusoidal signal is higher. In
order to improve the frequency resolution of the design DDS
system as much as possible, the DAC digits can be improved
in consideration of the design cost. In the actual work
process, the frequency control registers and the phase
accumulator are usually accumulated. When the size of the
frequency control word is unequal to the 2 of integer power,
the synthetic signal can be produces the phase truncation
error. In order to reduce the phase truncation error, the
frequency control registers and the phase registers are set in
the same position.
3. Design of Hardware Circuit for
DDS System
The hardware circuit of the excitation source system is
mainly composed of the high speed digital mode conversion
circuit and the key circuit. The digital analog converter
circuit comprises a digital analog converter, a amplifying
circuit and a current-voltage conversion circuit. The key
circuit adopts the light touch switch. The change of keys
determines the value of the internal register of the excitation
source module, which is used to adjust the frequency and
phase of the excitation source module synthesizing signal.
When detecting the artifacts of different materials, the
excitation source parameters can be adjusted by the key
circuit, and the intelligent control is realized [10-12].
The digital to analog Converter can convert the numeral
signal to the analogue signal, and the DDS system needs to
be realized on the hardware circuit of high Speed Digital to
Analog (DA) conversion. High speed DA conversion chip
using DAC900, DAC900 is 10-bit high-speed Digital-to-
Analog converter, the highest support 165MSPS renewal
rate. The full-scale output current is determined by the ratio
of the internal reference voltage and an external resistor,
SETR . The current output can be directly connected to an
output resistor to provide a two-way complementary single-
ended voltage output. The output of DAC900 has one-
terminal and difference output modes, and the DDS system
adopts the differential output mode. The sinusoidal signal
output by the DA chip first is amplified by a differential
amplifier, and the I-to-V converter function is realized by the
operational amplifiers and resistors.
American Journal of Engineering, Technology and Society 2018; 5(1): 5-10 7
Figure 1. Schematic diagram of digital-to-analog conversion.
According to the DAC900 data manual, the full-scale
output current of the DA Converter can be achieved by
setting 2KΩ of the external resistor. Connect the reference
voltage to the ground using the internal reference voltage
1.24V. outfsI can be calculated by:
32 REFIOoutfs
SET
VI
R= ×
As shown in Figure 1, the differential output swing shown
in the formula:
2 1023V =
1024OUTDIFF OUT OUTFS LOADOUT
CodeV V I R
× −= − × ×
Where outfsI is full-scale output Current of DAC900,
REFIOV is internal reference voltage, SETR is set full range
output resistance value, OUTDIFFV is output voltage. Current-
output Digital to Analog Converter (DAC) usually requires a
current-voltage conversion circuit to output voltage, one
method is to directly output the current terminal load, the
other is to connect the operational amplifier to output
voltage. DAC output impedance is relatively large, usually
using operational amplifiers to export voltage. In order to
improve the carrying capacity of DDS system, the power
amplifier can be designed to improve the driving ability.
4. Verilog HDL Programming of the
DDS System
In this paper, we use Verilog Hardware Description
Language (Verilog HDL) to design the digital circuit of DDS
system on Quartus software platform. Verilog HDL is a kind
of Hardware Description Language, the designer needs to
master the specific physical circuit model. First you need to
write a design file, and then use the EDA tool for emulation
validation. Then the automatic integration tool is used to
switch to the gate-level Electric network table, and finally the
circuit is generated through the layout wiring.
The FPGA Chip selects Altera company’s Cyclone IV series
chip, the chip model is EP4CE6E22C8N. According to the first
section, the DDS system needs to design phase accumulator,
frequency register, phase register, waveform storage table and
look-up table. In order to control the frequency of synthetic
signals, this paper designed a separate key to adjust the
frequency control words, by controlling the size of frequency
control words to adjust the frequency of synthetic signals. The
DDS system input port includes a clock input port, a reset port,
a standalone key port, a DAC clock output port, and a DAC
data output port. The phase accumulator is composed of the
address register and the phase register, the frequency control
word is realized by the frequency register, and the phase
control is realized by the phase register. The design adopts a
20-bit phase accumulator, and the phase accumulator has high
10-bit and phase register to accumulate output. The system
clock is 50MHz and the frequency step value is about 48Hz.
The phase accumulator Verilog code is as follows:
//-------------------------------------------------------
always @(posedge SYSCLK or negedge RST_B)
begin
if(!RST_B)
FRE_CNT <= 20'h0;
else
FRE_CNT <= FRE_CNT+FRE_WORD;
end
always @(posedge SYSCLK or negedge RST_B)
begin
if(!RST_B)
ADDR <= 10'h0;
else
ADDR <= FRE_CNT[19:10]+P_WORD;
end
//------------------------------------------------------
The waveform storage table is generated using the Quartus
8 Jiang Hu et al.: Design of DDS System for Alternating Current Field Measurement Detection Instrument
II waveform Data generator MIF maker. The waveform
storage table generates a storage area that needs to be
imported into the FPGA. In the FPGA, the corresponding
waveform storage block is configured, and the depth and bit
width of the waveform generator file are consistent with the
waveform storage table. The waveform storage tables are set
up as follows:
a. Under the Quartus II Tools drop-down menu, select
Mega Wizard to create a new macro unit.
b. Selecting memory under Memory Compiler directory,
setting device model, bit width and depth correlation
parameter.
c. To set a store name.
d. Add a generated waveform storage table.
After the waveform storage table is set up, the digital
circuit of DDS system can be realized by example of the
storage area in the main program. The next step is to perform
functional simulations of the design code. In order to test the
logic function of the design program, this paper uses
ModelSim SE software to perform the function simulation.
ModelSim SE Software is a version of ModelSim, a
simulation tool for hardware description language. The DDS
system simulation needs to write test program test Bench.
After adding design source files and test files, verify the
functions of DDS digital circuit system. The test file design
scenario can be expressed as:
a. The system clock is 50M Hz, and the digital to analog
converter clock is two frequency divider system clock.
b. In the first stage, the initial value of the synthetic signal
is set to 5 KHz, the original phase is zero, and the
simulation time is 300µs.
c. The second stage, the synthesis signal frequency does
not change, the initial phase adjustment is 90 degrees.
The ModelSim SE simulation waveform of DDS Digital
circuit is shown in Figure 2. After the test file is written, the
design source files and Test bench are added to the ModelSim
SE software for emulation. Because the ModelSim SE
software can only recognize hexadecimal files, you also need
to convert the waveform storage table to a hexadecimal file.
Figure 2. Simulation waveform of DDS system function.
According to the simulation waveform, the period of the first
phase is in accordance with the design requirements. The period
of the simulation synthesis sine signal is 199.7µs, that is, the
frequency value is 5000Hz and the initial phase is zero. After
300µs simulation time, the period of synthesizing sine signal in
the simulation waveform is 198.1µs. The frequency is basically
unchanged and the phase becomes 270 degrees. By viewing the
simulation count value of phase register, the phase adjustment is
affected by the value of the last synthetic frequency, because the
value of the phase accumulator is not clear after adjusting the
phase. According to the simulation waveform, the frequency
adjustment of DDS system is correct and the phase adjustment is
wrong. The phase adjustment deviates from the set value. In
order to avoid the abnormal phase adjustment in the actual
control process, an asynchronous zeroing operation is designed
for the problem in the simulation waveform diagram. When the
phase of the synthetic signal is adjusted, the phase summation
counter and phase register are first cleared and then the synthetic
signal phase is adjusted.
After the function simulation is validated, the sequential
simulation is needed in the design and development of the
FPGA. Sequential simulation is the same as functional
simulation platform, simulation process and simulation test
file. The delay information generated by additional layout
American Journal of Engineering, Technology and Society 2018; 5(1): 5-10 9
cabling is added during the sequential simulation process. In
this paper, the board-level debugging is done directly after
ModelSim SE function simulation. The hardware circuit and
FPGA interface are connected, and the design circuit is
validated by oscilloscope test.
5. Conclusions
After the design of the DDS system based on FPGA,
download the design program to the FPGA chip, connect the
interface between the hardware module and the FPGA, and
test the output of the high speed DA transform chip to the
oscilloscope. Then select RIGOL DS1104z digital
oscilloscope, put FPGA on the initial value of the composite
signal 5KHz, and adjust the synthesis signal source
frequency and phase through the independent key. DDS
System Frequency Step value is 48Hz. The oscilloscope test
results are shown in Figure 3.
Figure 3. The test results of DDS system.
The test results of the oscilloscope indicate that the
synthesizer signal frequency of DDS system is 4.986KHz. By
calculating, the relative error of the excitation source system
is 0.28%. The system can quickly respond to input changes
by adjusting the frequency of the synthesized signal by a
separate key.
In this paper, the DDS system of alternating current field
measurement detector is realized on FPGA platform. By
using ModelSim SE software to simulate the design code, the
frequency and phase of DDS system synthesized signal can
be adjusted by independent key. Finally, the design system
waveform is obtained from the oscilloscope, which verifies
the accuracy of the design system. The DDS system has the
advantages of high efficiency and convenience, and is
beneficial to the actual detection of Alternating Current Field
Measurement. Users can synthesize different signal sources
only by modifying the contents of the waveform storage table.
With the high portability of FPGA design program, the DDS
system can be applied to other portable testing devices.
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