design of fast low-cost implementation of single-clock-cycle binary comparator · digital vlsi...
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Digital VLSI designVLSI Design Lab
ABV-IIITM Gwalior
Design of Fast Low-Cost
Implementation of
Single-Clock-Cycle Binary
Comparator
Presented BySatwik Patnaik (2011VLSI-10)Shuts Mehrotra (2011VLSI-03)
Bishwajeet Pandey (2011VLSI-08)Mahendra Dev (2011VLSI-15)
Amit Kumar (2011VLSI-19
5 September 20121
Under guidance of
Dr. Manisha Pattanaik
Digital VLSI designVLSI Design Lab
ABV-IIITM Gwalior
Introduction• In the last few years, the design of high-speed, low-power
and area-efficient binary comparators has received a great deal of attention.
• It is well known that comparison is a fundamental operation in almost all digital signal processors.
• Examples of efficient architectures of binary comparators are demonstrated in [1]-[4].
• Among hardware implementations existing in the literature, latter are very representative solutions.
• Comparators can be broadly classified into Analog and Digital.
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Digital VLSI designVLSI Design Lab
ABV-IIITM Gwalior
Contd...• We are however, just concerned about the design of
Digital comparators in this course project.• They are further classified into Total (Full) comparators
and Equality comparators.• In full comparators, given A and B being 2 n-bit binary
numbers, they are able to separately recognize the 3 possible conditions i.e. A > B, A < B and A = B.
• In equality comparators, as the name suggests, they only indicate equality when both the inputs are equal.
• We will see the importance of binary comparators in the next slide...
•
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Digital VLSI designVLSI Design Lab
ABV-IIITM Gwalior
Contd...
• Binary comparators have always been an important logic block in an ALU and have extensive applications such as decoding of x86 instructions.
• The recent emergence of MIMO (Multiple Input Multiple Output) technology for next generation communications has further aggravated the need for low-power and high-performance comparators.
• MIMO decoding algorithms require extensive iterations of binary number comparison.
• We will see about the basic algorithm used in comparison in the next slide...
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Digital VLSI designVLSI Design Lab
ABV-IIITM Gwalior
Contd...
• The basic comparison operation between 2 numbers A and B can be performed by a simple addition operation.
• We will see how using addition operation, we can compare 2 numbers A and B.
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Digital VLSI designVLSI Design Lab
ABV-IIITM Gwalior
Contd...
• Firstly, generate the 2’s complement of B. As we know, 2’s complement of any number can be obtained by adding 1 to the 1’s complement of the number.
• Then add the 2’s complement of B to A.• If the addition operation generates a carry equal to
1, we can conclude that either A > B or A=B.• On the other hand, if carry obtained is 0, then A <
B. An example is shown in the next slide...
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Digital VLSI designVLSI Design Lab
ABV-IIITM Gwalior
Contd...
• Consider the 4 bit numbers A=1000 and B=1001.
• The 2’s complement of B is 0111. This is now added to A=1000.
• The sum is 1111 and the carry is 0, which proves that A < B.
• In the similar fashion, we can take other examples and check this logic.
•
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Digital VLSI designVLSI Design Lab
ABV-IIITM Gwalior
Existing Comparator Designs
• In order to reach a very high throughput, the approach proposed in [1] uses 2-phase clocking dynamic logic with all N transistors (ANT) blocks.
• Such a 64-bit transistor requires 1890 transistors and produces the correct result within 3.5 clock cycles.
• Disadvantage of [1] is that it can only be implemented with heavy pipelining.
• Some popular microprocessors like ARM often need to execute a comparison instruction within a single clock cycle.
• The latches used to form the pipelines increase the circuit complexity and power consumption of the ANT comparator.
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Digital VLSI designVLSI Design Lab
ABV-IIITM Gwalior
Contd...• Single cycle, two-phase clocking architectures are presented
in [2] and [3].• These comparators use a priority-encoding algorithm [2]
whereas a parallel MSB checking method is exploited in [3].• The latter is 22% faster than [2] but it requires 88% more
transistors.• To increase the achievable speed, a modification of MSB
checking algorithm used in [3] has been proposed in [4] in which a MUX based structure has been used.
• This architecture is basically designed for high fan-in comparators and exhibits highest computational speed but requires 3386 transistors.
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Digital VLSI designVLSI Design Lab
ABV-IIITM Gwalior
Contd...• As always happens in the design of digital circuits, achieving high speed
is not the only concern.• Ensuring low-power consumption and reduced silicon area are also
equally important design goals.• All the aforementioned works achieve high-performance using dynamic
logic.• While dynamic logic has demonstrated superior performance as compared
to static logic, it is not suitable for low-power operation.• The data activity factor is always 0.5 in dynamic logic while the value is
close to 0.1 in static logic making it advantageous in terms of power consumption.
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Digital VLSI designVLSI Design Lab
ABV-IIITM Gwalior
Contd...
• Design in [4] is not suitable for static logic implementation due to tall transistor stack height.
• Also, a higher stack height is less attractive in deep sub-micrometer process, where the Vdd/Vt ratio is lower (3 for 65nm).
• Transistors will exit saturation mode sooner and are forced to operate in the linear region.
• In this current course project, we are concentrating only on tree-based comparator circuits.
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Digital VLSI designVLSI Design Lab
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Novel Comparator Design as per [8]
• The comparison between two n-bit numbers A and B can be performed by an addition operation.
• In fact, when A is greater than or equal to B, the addition operation between A and 2’s complement of B generates a carry signal equal to 1.
• When A is less than B, the carry signal is 0.• It is well known that low-cost addition architectures such as
ripple-carry can drastically reduce the operating speed.• On the other hand, high-speed adders increases the hardware
complexity.
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Digital VLSI designVLSI Design Lab
ABV-IIITM Gwalior
Contd...• For this reason, design of efficient comparators do
not employs addition logic.• The main consideration is that we actually require a
special addition operation that does not produce the sum bits as only the carry signal is enough to give the result.
• The paper uses the concept of CLA (Carry Look ahead Adder) for reducing hardware complexity.
• The basic design principle is outlined in the next slide...
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Digital VLSI designVLSI Design Lab
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Basic Design Principle
• In the well-known CLA logic, the basic terms to produce an addition operation are the propagate and generate signals.
• These are typically computed by ORing and ANDingcorresponding bits of the input data.
• These signals are then elaborated to fast compute the intermediate carries and sum bits.
• Generate and propagate terms can be computed as shown:
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Digital VLSI designVLSI Design Lab
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Contd...
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The signals GG[i] and GP[i] can be then grouped four by fourusing the same CLA logic as shown below :
Digital VLSI designVLSI Design Lab
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Contd...
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The comparison result is finally shown as follows:
Digital VLSI designVLSI Design Lab
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Contd...
• It can be verified mathematically that, the signal Out[0] can recognize the case of A greater than B and A less than B.
• In fact, it is the carry out signal obtained by summing A and 2’s complement of B.
• However, to have the functionality of the total comparator, the signal Out[1] is computed.
• Out [1] is basically computed to ascertain A equal to B.• When A is equal to B, then Out[1] and Out[0] are both equal
to ’1’.
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Digital VLSI designVLSI Design Lab
ABV-IIITM Gwalior
Contd...
• When A is greater than B, out [1] is ’0’ and out [0] is ’1’.• When A is less than B, out [1] and out [0] are both equal to ’0”• This design makes the occurrence of the case in which• Out [1] =’1’ and Out [0] =’0’ impossible.• In the traditional design of CMOS comparators, 64 2-input EX-NOR
gates are required to compare the corresponding bits of the operands.• This design makes use of 32 2-bit CLA circuits and states that the
design complexity is lower than designing 64 2-input EX-NOR gates.•
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Digital VLSI designVLSI Design Lab
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Logic diagram
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Digital VLSI designVLSI Design Lab
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Contd...
• This circuit uses 3 levels of operations.• The first and second levels perform their evaluation phase when the clock
signal is high, whereas they perform the pre-charge phase when the clock is low.
• The third level of the comparator operates in the opposite manner, thus making the circuit able to compare 2 64-bit inputs within one clock cycle.
• The first stage consists of 32 CLA blocks that generate the signals GG[i] and GP[i] defined in the above slides.
• These signals are then input to the 8 4-bit CLA modules of the second stage.
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Digital VLSI designVLSI Design Lab
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Contd...
• Finally, the 8-bit comparator of the third level completes the comparison operation.
• Both 4-bit and 8-bit CLA blocks exploit the Manchester-Carry-Chain-based architectures.
• The latter were chosen to achieve sufficiently high-speed with a good time-area-power trade-off.
• Output signals produced by the generic 4-bit CLA blocks are latched. Latches are basically used to make the comparator to do fast operation within one-clock cycle.
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Digital VLSI designVLSI Design Lab
ABV-IIITM Gwalior
Our findings...• Upon simulating the above logic in VHDL, we found that
the author’s observation of Out[1]=’1’ and Out[0]=’0’ being impossible is false.
• The above logic fails for many input cases for a 8-bit and a 16-bit comparator.
• One more inconsistency which we noticed is that, there is no use of the 16-bit AND gate.
• One also fails to understand the use of implementing 2-bit CLA adders as the complexity involved in designing them is very large.
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Digital VLSI designVLSI Design Lab
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Contd...
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We also referred [9], which is also by the same authors and although they have corrected the condition for equality, they have reverted the conditions for the other 2 conditions. In paper [9], authors have included modifications to compute GG and GP signals by including XOR operation. This idea involves more circuit complexity than [8]. Modified table looks as follows:
Digital VLSI designVLSI Design Lab
ABV-IIITM Gwalior
Contd...
• In the comparator designed by us, we have not used the 2-bit CLA adders. We have implemented the generation of generate and propagate signals by logic blocks.
• There is no n-bit AND gate in the design as proposed by [8].• We are using a combination of generate and propagate
signals to ascertain the comparison values.• All the simulations have been done at 90nm technology
(Level 49 parameters) in Tanner S-Edit tool.• The simulation results are shown in the next few slides...
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Digital VLSI designVLSI Design Lab
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Simulation Results (A equal B)
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Digital VLSI designVLSI Design Lab
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Simulation Results (A greater B)
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Digital VLSI designVLSI Design Lab
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Simulation Results (A less B)
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Digital VLSI designVLSI Design Lab
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Contd...
• We have simulated the designs in 90nm technology with a supply voltage of 1 Volt.
• The designs simulated are of 16-bit comparator and have been realized in both traditional CMOS and Domino logic respectively.
• The same design has also been simulated in Gate Diffusion Input (GDI) technique which further lowers the silicon area required and the total number of transistors.
• However, the design implemented in GDI for a 32-bit comparator works in an abnormal fashion for certain input conditions.
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Digital VLSI designVLSI Design Lab
ABV-IIITM Gwalior
Contd...
• We have also slightly re-modified our earlier method to design a comparator with reduced transistor count.
• Instead of using all the generate and propagate signals, we can use specific signals which yields the same functionality with reduction in hardware.
• The VHDL simulations were performed first to ensure the functional verification of the design.
• VHDL simulations have been performed for 8-bit, 16-bit, 32-bit and 64-bit comparators successfully.
• The results and simulations are covered in the coming slides...
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Digital VLSI designVLSI Design Lab
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VHDL Simulations for 16-bit comparator(A less B)
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Digital VLSI designVLSI Design Lab
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VHDL Simulations for 16-bit comparator(A eq B)
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Digital VLSI designVLSI Design Lab
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VHDL Simulations for 16-bit comparator(A gt B)
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Digital VLSI designVLSI Design Lab
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VHDL Simulations for 32-bit comparator(A gt B)
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Digital VLSI designVLSI Design Lab
ABV-IIITM Gwalior
VHDL Simulations for 32-bit comparator(A eq B)
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Digital VLSI designVLSI Design Lab
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VHDL Simulations for 32-bit comparator(A less B)
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Digital VLSI designVLSI Design Lab
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VHDL Simulations for 64-bit comparator(A eq B)
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Digital VLSI designVLSI Design Lab
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VHDL Simulations for 64-bit comparator(A gt B)
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Digital VLSI designVLSI Design Lab
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VHDL Simulations for 64-bit comparator (A less B)
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Digital VLSI designVLSI Design Lab
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Schematic of 16-bit Comparator
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Digital VLSI designVLSI Design Lab
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Schematic of 32-bit Comparator
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Digital VLSI designVLSI Design Lab
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Simulations for 16-bit comparator(A eq B)
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Digital VLSI designVLSI Design Lab
ABV-IIITM Gwalior
Simulations for 16-bit comparator(A gt B)
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Digital VLSI designVLSI Design Lab
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Simulations for 16-bit comparator (A less B)
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Digital VLSI designVLSI Design Lab
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Contd...
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•We have observed that the logic used to implement higher fan-in comparators cannot be used for design of lower order comparators like 4-bit and 8-bit comparators.•A slight change in logic, leads to area and transistor efficient architectures for the above mentioned comparators.•Using a little variant of the traditional method of designing comparators, we have designed 4-bit, 8-bit and 16-bit comparators.
Digital VLSI designVLSI Design Lab
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Comparator Design as per base paper, February 2012
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• In the base paper, the author has proposed a Radix-2-Tree based comparator inspired by the fact that generate and propagate signals can be defined for binary comparisons similar to G and P signals for binary addition.• A 2-bit binary number (A1A0, B1B0) comparison can be realized in the following manner:
Digital VLSI designVLSI Design Lab
ABV-IIITM Gwalior
Comparator Design as per base paper, February 2012
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• In the base paper, the author has proposed a Radix-2-Treebased comparator inspired by the fact that generate and propagate signals can be defined for binary comparisons similar to G and P signals for binary addition.• A 2-bit binary number (A1A0, B1B0) comparison cans be realized in the following manner:
Digital VLSI designVLSI Design Lab
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Contd...
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• Here A and B are binary inputs and Cin is the carry input, Cout is the carry output.• G and P are generated and propagate signals respectively.• An encoding scheme may be employed here as shown:
Digital VLSI designVLSI Design Lab
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Contd...
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Let us take an example of a 4-bit comparator and see how this equation can be resolved..
Digital VLSI designVLSI Design Lab
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Contd...
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Finally, big and EQ can be computed using the following equations:
Digital VLSI designVLSI Design Lab
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Conclusion• The design and implementation of tree-based comparator circuitry has
been undertaken by us in this course project.• We have tried to provide a different version of a 16-bit comparator which
works for all the possible combinations tested by us.• A 16-bit equality comparator has also been designed using a novel
method which reduces the transistor count further as proposed by [5].• According to us, rather than having a general scheme for comparators,
different logic should be used for lower fan-in comparators and separate logic for higher fan-in comparators.
• A modified version of 8-bit comparator is proposed which is better than the conventional CMOS comparator in terms of silicon area and number of transistors.
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References
• C.H. Huang and J.S. Wang, ”High Performance and power efficient CMOS comparators,” IEEE J. Solid- State Circuits, vol.38, no.2, pp.254-262, Feb.2003.
• C.C. wang, C.F. Wu and K.C. Tsai, ”1 GHz 64-bit high-speed comparator using ANT dynamic logic with two-phase clocking” IEEE Proc. Comput. Digit. Tech., vol.145, no.6, pp.433-436, Nov 1998
• H.M. Lam and C.Y.Tsui, ”High performance single clock cycle CMOS comparators,” Electron. Lett. vol.42, no.2, pp.75-77, Jan.2006
• H.M. Lam and C.Y.Tsui, ”A MUX based high performance single cycle CMOS comparator,” IEEE Trans. Circuits Syst. II, Exp.Briefs, vol.54, no.7, pp.591-595, Jul. 2007.
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Contd...
• S. Perri and P. Corsonello, ”Fast Low-Cost Implementation of Single-Clock-Cycle Binary Comparator,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 12, pp. 1239-1243, Dec. 2008.
• S. Perri and P. Corsonello, ”Fast Low-Cost Implementation• F. Frustaci, S. Perri, M. Lamuzza and P. Corsonello, ”A new low-power
high-speed single-clock-cycle binary comparator,” in Proc. IEEE Int. Symp. Circuits Syst., 2010, pp. 317-320.
• Pierce Chuang, David Li, Manoj Sachdev, ”A Low-Power High-Performance Single-Cycle Tree-Based 64-Bit Binary Comparator,” IEEE Trans. Circuits Syst. II, Exp. Briefs,vol.59, no.2, pp.108-112, Feb. 2012.
•
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