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DESIGN AND TEST OF INTEGRATED INDUCTORS

FOR RF APPLICATIONS


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Design and Testof Integrated Inductors

for RF Applications

by

Jaime AguileraVision Technologies,

Spain

and

Roc BerenguerCentro de Estudios e Investigaciones Tcnicas de Gipuzkoa (C.E.I.T.),Spain

KLUWER ACADEMIC PUBLISHERSNEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW
http://www.wkap.nl/http://www.wkap.nl/http://www.wkap.nl/


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eBook ISBN: 0-306-48705-5

Print ISBN: 1-4020-7676-2

2004Kluwer Academic PublishersNew York, Boston, Dordrecht, London, Moscow

Print 2003Kluwer Academic Publishers

All rights reserved

No part of this eBook may be reproduced or transmitted in any form or by any means, electronic,mechanical, recording, or otherwise, without written consent from the Publisher

Created in the United States of America

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and Kluwer's eBookstore at: http://ebooks.kluweronline.com

Dordrecht
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Contents

Dedication v

Contents vii

List of Figures xi

List of Tables xvii

List of Abbreviations xix

Preface xxi

1. Introduction 1

4

8

9

1.

2.

Conventional IC fabrication technologies

Keys to progress in RF transceiver design; High Q integrated inductors2.1 LC Parallel Tank

2.1.1

2.1.2

Low Noise Amplifiers (LNA)

Voltage Controlled Oscillators (VCO)

2.2

2.3

Inductive degeneration for matching purposes

RF Filters

3. The challenge of integrating high quality inductors

3.1

3.2

Metal losses

Substrate losses4. Structure of the book

11

14

16

18

19

20

2121


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viii Design and test of integrated inductors for RF applications

2. General considerations

1. Ways of integrating an inductor

1.1

1.2

Conventional fabrication processes

Non-conventional fabrication processes

23

23

24

27

28

29

30

30

31

34

35

36

37

37

38

38

40

41

41

44

4547

48

48

49

50

51

51

51

53

54

56

58

60

63

66

6668

73

75

76

76

2. Spiral inductors on silicon based technologies

2.1 Physical overview: Difficulty of integrating an inductor

2.1.1 Inductance

2.1.1.1

2.1.1.2

2.1.1.3

Self inductance

Mutual inductance

Total inductance

2.1.2 Resistance

2.1.2.1

2.1.2.2

Skin effect

Proximity effects

2.1.3 Parasitic effects in the substrate

2.1.3.1

2.1.3.2

Magnetically induced parasitic effects in the substrate

Electricallyinduced parasitic effects in the substrate

2.1.4 Parasitic capacitance between metal turns

2.2 Spiral inductor electrical models

2.2.1

2.2.2

2.2.3

model

Transformer model

Wideband model2.3 Quality factor definition

2.3.1

2.3.2

2.3.3

definition

definition

definition

2.4 Different attempts to predict the performance

2.4.1

2.4.2

2.4.3

Field electromagnetic simulators

ASITIC

Method based in the model parameter definition

2.5 Quality factor improvement methods

2.5.1

2.5.2

2.5.3

2.5.4

Broken guard ring

Biased N-well beneath the inductor

Substrate shielding

Non conventional fabrication processes

3. Inductors test and characterization

1. On wafer measuring equipment

1.11.2

1.3

1.4

Vector Network AnalyzerProbes

Probe station

Commercial calibration kits

2. Measuring accuracy and Repeatability

2.1 Different types of measuring errors


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Design and test of integrated inductors for RF applications ix

2.2

2.3

Random errors

Systematic errors

77

77

78

79

80

80

82

85

87

88

89

89

90

91

92

93

95

96

102

104

105109

113

113

114

114

115

115

115

116

118

118

120

121

127

2.3.1

2.3.2

2.3.3

Systematic errors due to VNA

Cables and connectors

Probes

2.4 Calibration

2.4.1 SOLT Calibration

2.5 Repeatability and accuracy

3. Measuring configuration: 1-port versus 2-port configuration

3.1 General Case

3.1.1

3.1.2

3.1.3

Two-Port measurement with the device placed in series

Two-Port measurement with the device placed in parallel

One-Port measurement

3.2 Inductor model case

3.2.1

3.2.2

3.2.3

Two-Port measurement with the model placed in series

Two-Port measurement with the model placed in parallel

One-Port measurement

3.3 Sensitivity analysis

4. Test fixture design

4.1 Substrate related issues

4.1.14.1.2

Interterminal couplingInterport coupling

4.2 Metallization related issues

4.2.1

4.2.2

4.2.3

4.2.4

4.2.5

4.2.6

Pad material

Probe tip material

Probe alignment

Setup stability

Tolerances

Wear of the probes and the pads

4.3 General Guidelines

5. De-embedding techniques

5.1

5.2

5.3

Test-fixture model

In-fixture standards

De-embedding procedure

6. model inductor characterization

4. Influence of the geometric parameters on the inductors performance:

Design rules 135

135

137

137

139

141

1.

2.

Problem description

Analytical study and simulations

2.1

2.2

2.3

Number of sides

Spacing between tracks

External radius and number of turns


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x Design and test of integrated inductors for RF applications

2.3.1

2.3.2

Number of turns

External radius

2.4

2.5

Width

Metal layers connected in parallel

141

142

143

145

148

148

149

150

152

153

156

158

160

162

163

165

167

168

168

168169

170

173

177

185

3. Empirical study

3.1

3.2

3.3

Inductor selection

Fabrication and measurement

Analysis of the empirical data

3.3.1 External radius and number of turns

3.3.1.1

3.3.1.2

Influence of the proximity effect on the internal turns

Link between the track width and proximity effect

3.3.2

3.3.3

3.3.4

Skin and corner effects

Geometry of the viaTrack width higher than

4. Design considerations

5. Inductors design flow

1.

2.

Generation phase

Filtering phase

2.1

2.2

Inductance filtering

CM and internal radius3.

4.

Performance estimation phase

Verification phase

Appendix

References

Index


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List of Figures

Figure 1-1.

Figure 1-2.

Figure 1-3.

Weight and size improvement experimented by mobile phones from

year 1993 to 2001. 2

3a)Super heterodyne and b) Low IF radio architectures.

RF Technologies: a)GaAs MESFET b) GasAs HBT

Si-Bipolar d) SiGe HBT e) CMOS

c) Advanced

7

9

1012

13

14

15

17

Figure 1-4.

Figure 1-5.Figure 1-6.

Figure 1-7.

Figure 1-8.

Figure 1-9.

Parallel LC tank circuit.

Realistic model for a parallel LC tank.Narrow-band differential low noise amplifier topology.

Simplified small signal equivalent circuit.

Different VCO topologies depending on implemented feedback.

Basic LC-tuned oscillator.

Figure 1-10.

Figure 1-11.

LNA input with inductive degeneration.

Small signal equivalent circuit of the input of the LNA of Figure 1-10.


Figure 2-1.

Figure 2-2.

LC Low-pass filter.Loss mechanisms.

Microphotography of a squared, octagonal, and icosagonal inductor

18

1920

24with a CMOS technology.

Microphotography of a voltage controlled oscillator using two spirals

fabricated with a CMOS technology in a mirror configuration.

25

25

26

26

27

Figure 2-3. Microphotography of a balanced inductor fabricated on a

SiGe.

Figure 2-4.

Figure 2-5.

Figure 2-6.

Geometry of a centre-tapped inductor.

Diagram of a multilevel inductor using two metal layers.

Multilevel geometry for maximizing the inductance per unite area.


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xii

Figure 2- 7.

Figure 2-8.

Figure 2-9.

Designand test of integrated inductors for RF applications

Microphotography of: a) toroidal inductor b) solenoidal inductor with

inclined top and bottom conductor [Ahn98] and c) solenoidal inductor

28

Cross-section of an integrated spiral inductor on a Si technology and

the physical effects that arise when a time-varying voltage is applied

29

Self inductance value for a rectangular conductor versus its length and

31

32Figure 2-10.

Figure 2-11.

Method for computing the GMD between areas.

Mutual inductance of two rectangular conductors versus distance

between centres and width. 33

Figure 2-12. Mutual inductance of two rectangular conductors versus width and

separation between them. 33Figure 2-13. Illustration of the positive and negative mutual inductance of a

squared planar spiral. 35

36Figure 2-14.

Figure 2-15.

Figure 2-16.

Figure 2-17.

Illustration of the skin effect in a rectangular conductor.

Schematic representation of the induced currents in the substrate

to the magnetic field penetration.

due

38

39

the

40

Schematic representation of the metal-substrate capacitance.

Schematic representation of the displacement currents due to

metal-substrate capacitance.Figure 2-18. Schematic representation of the parasitic capacitance between layers

and metal tracks. 41

42

44

45

46

49

52

54

55

56

the

57

58

59

the

61

63

64

Figure 2-19.

Figure 2-20.

Figure 2-21.

Figure 2-22.

Figure 2-23.

Figure 2-24.

Figure 2-25.

Figure 2-26.

Figure 2-27.

Figure 2-28.

Two-port model.

One-port model.

Transformer Model.

Wideband model.

Simplified model.

Equivalent energetic model for the one-port model.

Schematic view of a spiral with a broken guard ring.

One-port model of a spiral with a broken guard ring.

Schematic view of an inductor with a biased N-well beneath it.

One-port model of an inductor with a biased N-well beneath

inductor.

Figure 2-29.

Figure 2-30.

Figure 2-31.

Figure 3-1.

Figure 3-2.

One port model of a spiral with substrate shielding.

View of a squared spiral with a patterned ground shield underneath

the spiral.

Microphotography of an inductor without substrate underneath

spiral [Chan98].

Individual die mounted on a test fixture.

Basic elements involved in the characterization of a passive element.

with parallel conductor [Yoon99].

across its ends.

width (the thickness is fixed at


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Design and test of integrated inductors for RF applications xiii

Figure 3-3.

Figure 3-4.

Figure 3-5.

Figure 3-6.

Figure 3-7.

Figure 3-8.

Figure 3-9.

Figure 3-10.

Figure 3-11.

Figure 3-12.

Figure 3-13.

Figure 3-14.


Figure 3-17.

Figure 3-18.

Figure 3-19.

Figure 3-20.

Figure 3-21.

66

67

68

69

70

71

71

72

73

74

76

78

79

81

82

83

84

85

87

88

89

90

91

92

92

93

96

103

105

106

107

108

Test fixture and DUT.

Applicability of the different measuring methods.

Simplified block diagram of a vector network analyzer.

Typical construction for an air coplanar probe (ACP).

Electric field pattern of a balanced and unbalanced coplanar probe.

Coplanar probe planarization (Reference plane definition).

Checking of the probe tip planarity by means of a contact substrate.

Alignment marks to set skating.

Resulting open stub under the probe due to skating.

Standard setup of a manual probe station.

General purpose impedance standard substrate (ISS).

VNA based system.

Major systematic errors.Measuring setup 12 term error model.

ISS short standard.

ISS load standard.

Comparision between load and short reflection responses.

ISS thru standard.

Three possible configurations for measuring a two-port device

with a VNA.

Figure 3-22.Figure 3-23. Setup for the calculation of the scattering parameters of a two-port

measurement with the device placed in series.

Figure 3-24.

Figure 3-25.

Setup for the calculation of the scattering parameters of a two-port

measurement with the device placed in parallel.

Setup for the calculation of the scattering parameters of a one-port

measurement.

Figure 3-26.

Figure 3-27.

model of an integrated inductor.

measurement with the model placed in series.

Figure 3-28.

Figure 3-29.

measurement with the model placed in parallel.

measurement.

Figure 3-30.

Figure 3-31.

Figure 3-32.

Inductor measurement with and without de-embedding.

Test fixture interterminal and interport coupling.

ground (G) pads.

Figure 3-33.

Figure 3-34.

Configuration to measure the input capacitance of a generic device

with value

Different pad shapes.

Two port network.



Setup for the calculation of the scattering parameters of a one-port

General model for the coupling mechanism between signal (S) and


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xiv Design and test of integrated inductors for RF applications

Figure 3-35.

Figure 3-36.

Figure 3-3 7.

Figure 3-38.

Figure 3-39.

Figure 3-40.

Figure 3-41.

Figure 3-42.

Figure 3-43.

Figure 3-44.

Figure 3-45.


Figure 3-48.

Figure 3-49.

Figure 3-50.

Figure 3-51.

Figure 3-52.

Figure 3-53.

Figure 3-54.

Figure 3-55.

Figure 3-56.

Figure 4-1.

Figure 4-2.

Figure 4-3.

Figure 4-4.

Figure 4-5.

Figure 4-6.

Recommended implementation of a signal pad for a

108

Interport coupling of different test-fixtures with different distances

110

Cross sectional view of two test-fixtures with and without ground

111

Interport coupling measurement of two test-fixtures with and without

ground contacts. 112

Interport coupling measurement of different test-fixtures, where the

113

Measured mean and standard deviation of the DC contact resistance

115

Contact resistance degradation after reprobing over the same pad116

Use of n-well or metal shield underneath the pads to reduce effect of

Test-fixture model.

117

119

120

In-fixture standards: single open, single short, open and short standars.

121

122123

124

126

128

128

129

130

Measurement of the single short.Measurement of the single open.

Measurement of the short standard.

Measurement of the open standard.

Integrated inductor model.

Microphotography of the inductor to model.

and of the inductor under test.

and of the inductor under test.

Comparison between the de-embedded S-parameters of the integrated

131

Comparison of the real part between the measured and simulated data.

132

Comparison of the imaginary part between the measured and

133

135

137

138

Geometric parameters that define an integrated inductor.

Ideal variation of the quality curve as the track width is increased.

Quarter of a square and circular inductor.

Simulation of the influence of the number of sides on the quality at

139

Simulation of the influence of the spacing on an inductors quality. 140

Simulation of the influence of the number of turns on an inductors

quality. 142

CMOS

process.

between ports and different types of substrate.

contacts.

pads are placed at different distantes: and

for different applied skate.

several times.

parasitic pad capacitance

Integrated inductor test-fixture.

inductor and simulated S-parameters of the obtained model.

simulated data.

1.8GHz.


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Design and test of integrated inductors for RF applications xv

Figure 4-7.

Figure 4-8.

Figure 4-9.

Figure 4-10.

Figure 4-11.

Figure 4-12.

Figure 4-13.

Figure 4-14.

Simulation of the resistance for different track widths.

Different possibilities of connecting two metal layers in parallel.

Equivalent circuit used to simulate the influence of the via area.

Microphotography of some of the fabricated inductors.

Microphotography of one of the de-embedding structures.

Measured inductance and quality of a 2.8 nH inductor.

Measured resistance of a 2.8 nH inductor.

144

146

147

149

150

151

151

Measured resistance of several inductors with a track width of

154

Figure 4-15.

Figure 4-16.

Figure 4-17.

Figure 4-18.

Measured resistance of two pairs of inductors with the same

155

Measured resistance of two inductors used to analyze the effect of the

156157Proximity effect between two metal layers connected in parallel.

Measured resistance of eight inductors selected to demonstrate that the

influence of the skin and corner effect is minimum in comparison to

159

Figure 4-19. Zoomed out of the resistance curves of b_5, Bo_21, Bo_24 and

Bo_62. 160

Figure 4-20.

Figure 5-1.

Figure 5-2.

Figure 5-3.

Measured quality and inductance of a same geometry with different

vias. 161166

170

171

Proposed design flow.

Relation between and an inductors area.

Relation between and an inductors area.

the proximity effect.

width on the proximity effect.

inductance.


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List of Tables

Table 1-1. Commonly used technologies for communication components

5

Table 1-2.

Table 3-1.

Table 3-2.

Table 3-3a.

Table 3-3b.

Table 3-4a.

Table 3-4b.

Table 3-5.

Performance comparison of some RF IC Technologies [Kuc00].

Geometrical characteristics of the fabricated inductor.

model parameters of the fabricated inductor.

Results of the analysis of the parameter: (a) Argument.

Results of the analysis of the parameter: (b) Module.

Results of the analysis of the parameter: (a) Argument.

Results of the analysis of the parameter: (b) Module.

8

97

97

98

99

100

101

General values for substrate and metallization parameters of some

104

128

130

138143

147

154

155

158159

Geometric characteristics of the inductors used to analyze the

161

Table 3-6.

Table 3-7.

Table 4-1.

Table 4-2.

Table 4-3.

Table 4-4.

Table 4-5.

Table 4-6.

Table 4-7.

Table 4-8.

fabrication technologies.

Dimensions of the balanced inductor.

Optimization result.

Relation between the number of sides and the quality of an inductor.

Skin depth for the aluminum at 1 GHz.

Variation of the inductance and resistance with the via area.

Resistances slope of the selected inductors.

CM and internal radius on an inductors performance.

Geometric characteristics of the inductors used to analyze the effect of

Relevant geometric characteristics of the inductors used to

demonstrate that the influence of the skin effect is minimum on

inductors with a track width between 10 andResistances slope of the selected inductors.

influence of the geometry of the via.

[Kuc00].


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xviii Design and test of integrated inductors for RF applications

Table 4-9.

Table A-1.

than

Relevant data of five measured inductors with a track width higher

Geometrical characteristics of the fabricated inductors.

162

173


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List of Abbreviations

AC

ACP

AlSiCu

AMS

Au

BeCu

BiCMOS

BJT

CM

CMOS

CSP

Cu

DC

DECT

DUT

EDGE

EPI

F

GaAs

GMD

GPRS

GSM

Alternating current

Air Coplanar Probe

Aluminum Silicon Copper

Austrian Mikro Systeme AQ

Gold

Berillium Copper

Bipolar Complementary Metal Oxide Semiconductor

Bipolar Junction Transistor

Metal Quantity

Complementary Metal Oxide Semiconductor

Chip Scale Package

Copper

Direct Current

Digital Enhanced Cordless Telecommunication

Device Under Test

Enhaced Data Rated for GSM Evolution

Epitaxial

Noise Figure

Gallium Arsenide

Geometric Mean Distance

General Package Radio Service

Global System Mobile


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xx Design and test of integrated inductors for RF applications

HBT

IC

IF

ISS

LNA

LO

LRM

LRRM

MESFET

PA

PCB

Q

RF

SA

SiGe

SOLT

TRL

UMTS

VCO

VLSI

VNA

W

WLAN

Heterojunction Bipolar Transistor

Integrated Circuit

Intermediate Frequency

Impedance Standard Substrate

Low Noise Amplifier

Local Oscillator

Line, Reflect, Match

Line, Reflect, Reflect, Match

Metal Semiconductor Field Effect Transistor

Power Amplifier

Printed Circuit borrad

Quality Factor

Radio Frequency

Spectrum Analyzer

Silicon-Germanium

Short, Open, Load, Thru

Thru, Reflect, Line

Universal Mobile Telecommunications System

Voltage Controlled Oscillator

Very Large Scale Integration

Vector Network Analyzer

Tungsten

Wireless Local Area Network


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Preface

This book is the result of several years of research on the field of

radiofrequency integrated circuit design, specifically on the design of

integrated inductors for RF applications on conventional technologies.

One of the key elements today in the wireless industry, especially in the

silicon RF integrated circuits field, is the design of high-quality passive

elements. The performance of several basic RF blocks such as low noise

amplifiers, mixers and voltage controlled oscillators depends on the qualityof these elements.

The work done establishes the design guidelines for the definition of the

inductors geometrical characteristics and new techniques to improve their

quality. It also covers their measurement and characterisation. This fact is

not always taken into account by the designers due to the lack of information

in bibliography regarding to this topic.

The approach of this book is novel due to two facts; first it tries to help

designers with poor or none experience by describing the whole design flowof an inductor. From the definition and analysis of the physical effects that

appear in them to their modelization. It also covers issues such as the

maximization of the quality factor by a correct definition of the geometry,

novel aggressive design rules, measuring setup, test-fixture parasitics de-

embedding, etc.

Secondly it will help designers with high experience due to the fact that,

based on empirical data, some design rules that have been widely used by

the design community have been proved to be conservative and breaking

them will lead up to higher quality designs.

To make intuitive and helpful to any designer, the book has been

structured as follows. The first chapter shows how the performance of some


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xxii Design and test of integrated inductors for RF applications

RF building blocks, like LNAs, VCOs or RF Filters, highly depend on the

quality factor of the integrated inductors used to implement them.

It also introduces the difficulty that entails the integration of RF passive

elements in conventional Si based low cost technologies, due to metal losses

and substrate losses.Chapter 2 covers some general considerations like the physical analysis

of the integrated inductor, the existing electrical models to model them

model, transformer model or wide band modified model), or some

methods to improve the quality factor of an integrated inductor (Broken

guard rings, Substrate shielding, etc.).Inductors test and characterization is covered in chapter 3. In the

inductor modelling, the accurate measurement of the device is very

important due to the fact that these are elements with very low resistance,where a single ohm makes a big difference in the quality factor. This is the

reason why the book also covers the design of the test fixture and the

measurement setup.

Chapter 4 analyses the influence of the geometrical parameters in the

inductors performance and will establish the design guidelines for the

definition of the elements geometrical characteristics. These design

guidelines are derived from analytical and empirical data. It also introduces

some new techniques to improve the quality factor.Finally due to the fact that foundries only supply models for discrete

values of inductance, and that these inductors are not optimized for an

specific frequency range, there is a need of an inductors design flow in

order to be able to obtain a specific inductor value, optimized for a specific

application or what is the same a specific frequency range. The inductors

design flow is covered in chapter 5, where design rules derived in chapter 4

are applied.

We also wish to express our gratitude to all persons who have contributed

to the development of this book. We would like to thank Prof. Andrs

Garca-Alonso and Prof. Joaquin de No for all their support. Our thanks also

goes to the University of Navarra, and CEIT for offering us the possibility of

this research work and all our colleagues at the Electronics and

Communication department (Guillermo, Juan, Erik, Iigo, Josu, ...) for their

direct or indirect contributions to this work. We would also like to thank

Mrs. Carmen Conde for her comments and corrections to our English.

Finally, we thank to our families for their support and patience. Without

it this book would not have been possible.

JaimeAguilera

RocBerenguer


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Chapter 1

INTRODUCTION

The fast growing of the wireless market has created an urgent demand forsmaller and cheaper handsets with increased functionality and performance

while still meeting the tight constraints for mass production within a short

product life cycle.

The successful achievement of these conflicting trends has been possible

due to the development of key technical capabilities in the design and

production of each new wireless device generation.

In the baseband section of the handset, the great development

experimented by the CMOS processes in the last decade, has shrunk thesilicon real estate required for the processor, memory and interface ICs.

The advanced chip scale package (CSP) techniques and multi-layer

laminate printed circuit boards (PCB) have minimized the electronic

interconnect and packaging volume. The battery technology has advanced

from the older nickel cadmium and nickel metal-hydride to the lithium ion

and lithium polymer technologies, improving the battery pack size, weight

and performance. The antenna has migrated from outside in the old designs

to inside the plastic housing in the new ones, giving more freedom in the

handset form and design. As it is shown in Figure 1-1, all these

improvements have led to lighter, smaller and compact handsets.

In contrast to this situation, the improvement in the passive component

content of the handset has been much less dramatic compared to other

technical areas. This inertia has not been due to the lack of attention by the

set-makers or in the literature.


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2 Introduction


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Design and test of integrated inductors for RF applications 3

It is estimated that in a single-mode telephone, passive components

suppose the 90 percent of the component count, 80 percent of the size and 70

percent of the cost [Pul02]. High quality passive components are specially

prevalent in the RF Front-end and radio transceiver sections of the wirelessterminal, and these increase proportionally as new standards (GPRS, EDGE,UMTS, Bluetooth, ...), are incorporated to the handset. In addition todominating the component count, size and cost of the terminal the large

number of passive components is a major factor in the assembly line

production and yield and contribute to unwanted reliability failures. Thus abig research effort has been done in that field in order to reduce the passive

component count of the handset.


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4 Introduction

One of the main methods to reduce the passive component content of the

mobile device has focused primarily on optimizing the system architecture

and partitioning to increase the level of integration on the ICs without

sacrificing the performance or cost. In the radio transceiver section, as it is

shown in Figure 1-2, the move from the super heterodyne architecture to thezero or low IF architecture has eliminated the set of passive components

required for the IF functions, thus reducing the number of required passive

devices.

But the direct approach to reduce the passive component content in the

mobile terminal is the integration of the passive components into a substrate.

This trend has been accelerated by the steady improvement in the

performance of the passive components integrated in the RF IC processes,

enabling the integration of passive components on chips where previouslyonly external surface mount components could meet the required RF

performance.

The following chapters explore the possibility of obtaining high quality

integrated inductors on low cost silicon substrates and the test considerations

to obtain accurate models of them. Previously, next section briefly describes

the competing RF fabrication technologies where the inductors can be

integrated. After that, section 2 illustrates how the quality factor of the

integrated inductor determines the performance of the basic RF buildingblocks like Low Noise Amplifiers (LNAs), Voltage Controlled Oscillators

(VCOs) or filters. Section 3 gives a short introduction of the challenge of

integrating high quality inductors, and finally section 4 establishes the need

for an inductor design flow.

1. CONVENTIONAL IC FABRICATION

TECHNOLOGIES

The competing technologies on the RF market are briefly described in

this section. Traditionally, the GaAs based technologies were the preferred

option to implement the RF part of the mobile handsets.

The MESFET still is the working horse GaAs technology. It is mostly

based on ion implantation into semi insulating substrates (Figure 1-3a). This

is the least expensive process concerning raw material cost, since no

epitaxial layers are required. The technologies on the market are processed

with gate length from down to values in the range of

25GHz are available in production depending on the gate length used. FETs

can easily achieve noise figures below 1 dB in the 1-2GHz frequency range.

The other still used GaAs technology is the based on HBT transistors.

The HBT transistor is a modified bipolar transistor (Figure 1-3b). The


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emitter and base layers are formed with different band gap materials. The

emitter having the wider band gap, thus the emitter delivers a barrier against

the hole injection into the base. In this way, the main deficiencies of a

standard homojunction bipolar are overcome. Due to the required EPI layer

the raw material cost is higher compared to MESFET. The min feature size

for GaAs based HBTs are about width. in the range of 30-

60GHz is reached in production. The HBT delivers an excellent RF power

density due to its vertical current flow.

These two GaAs technologies based on HBTs and MESFET transistors

covers arround 15 to 20 % of the RF applications on the market [Ber99]. As

shown in table 1.1, these RF applications are limited to the RF power

amplifiers (PA) and Low Noise Amplifiers (LNA) of medium and high

performance systems like GSM, DECT or CDMA. The other RFapplications are covered by the Silicon based technologies mainly due to

their lower cost.


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6 Introduction

The most used Si based technologies to implement the RF function of

commercial handsets are the advanced silicon bipolar processes and the SiGe

processes. The advanced performance silicon bipolar processes with the

up to 25GHz are processed on refined high performance IC technology lines.

Standard feature sizes of emitter width in double poly self aligned

technique, side wall spacer technique, buried layers, selective implanted

collector are build into these highly sophisticated devices (Figure l-3c).

Even more advanced technologies with further shrunk emitter widths are

available with up to 45GHz. One of the biggest advantages of the Si

processes is the potential to use the high integration capability of Si. Not

only in highly integrated bipolar only circuits, but also the combination with

CMOS technology offering the possibility of integration of the RF functions

and the baseband functions in one chip.The SiGe HBT is a further improvement of the Si advanced bipolar

process. The base layer is replaced by a hetero SiGe layer (Figure 1-3d).

Features sizes of emitter width with up to 75GHz are achieved

using advanced sophisticated processes. The other processes optimised for

low noise applications show in production from 60 to 70GHz. Like the

advanced silicon bipolar processes, the SiGe processes take advantage of the

high integration capability of Si, being also fully compatible with CMOS

technologies. To serve also power applications, higher breakdown voltagesare required. The base layers together with the min feature sizes have to be

enlarged. This reduces the performances drastically; e.g. the goes down to

about 30GHz, that is the reason why this kind of processes have not yet

substituted the GaAs ones in the power amplification function of the

transceiver. The general bipolar advantage of low phase noise is valid for

the SiGe HBT also, and they are widely used on the implementation of

frequency synthesizers.

As it is shown by table 1.1 all baseband functions of the mobile phone

are implemented using digital CMOS processes. The technologies on the

market are processed with gate length from down to (Figure

l-3e). values in the range of 45GHz are available in production depending

on the gate length used. During the last decade there has been a strong

motivation to extend the application of CMOS processes to the RF part, due

to its much lower cost. In fact as shown in table 1.2 the performance of the

MOS transistor is comparable with the performance of the transistors of

other technologies.


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But as also illustrated by table 1.2 the quality factor of the passive

integrated on a Si BJT or CMOS processes are poor compared to the

integrated on SiGe or GaAs ones. This is one of the reasons why the

introduction of CMOS processes in the RF part of high and medium

performance transceivers has been delayed, and they are limited to low cost,

low performance systems like Bluetooth or WLAN.


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8 Introduction

A key parameter to obtain high performance RF circuits is the quality factor

(Q) of the integrated passives. The next section will explain how the quality

factor of the integrated passives determines the performance of the basic RF

building blocks, like LNA, VCO or RF Filter.

2. KEYS TO PROGRESS IN RF TRANSCEIVER

DESIGN; HIGH Q INTEGRATED INDUCTORS

Figure l-2b shows the block diagram of a low IF front-end. It is

composed by a LNA, a RF Filter, a down conversion mixer and a VCO. One

characteristic of these RF circuits is the relatively large ratio of passive to

active components. In contrast with the digital VLSI circuits or even with

other low frequency analog circuits, such as Op-amps, many of those passive

components may be inductors or even transformers.

A widely used LC network, when implementing LNAs or VCOs, is the

so-called LC parallel tank or simply tank circuit (Figure 1-4). The

performance of these two RF circuits will depend on the quality factor Q of

the tank circuit.


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2.1 LC Parallel Tank

For this network, the impedance is:

From inspection of the network or of the Equation 1.1, it is easy to seethat the impedance goes to zero both at DC, because the inductor acts as a

short there, and at very high frequencies, because the capacitor acts like a

short there. We may even say that, at very low frequencies, the networks

impedance is dominated by the inductor, and is that of the capacitor at very

high frequencies. What divides low from high is the frequency at which

the inductive and capacitive parts cancel. Known as the resonance

frequency, this is given by Equation 1.2:

Purely parallel LC networks rarely exist in practice, so it is important to

analyse configurations that might be more real. Because inductors tend to be

significantly lossier than capacitors, the model shown in the Figure 1-5 is a

more realistic approximation to the typical parallel LC tank.


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10 Introduction

Let us convert now the circuit of Figure 1-5 to a purely RLC network byreplacing the series LR section by a parallel one. Such a substitution will not

be valid in general; only at frequencies near the resonance the equivalence

will be reasonable. To show this formally, let us equate the parallel andseries impedances of the LR section:

If we equate the real parts, and note that we

obtain equation 1.4.

If we equate now the imaginary parts we obtain equation 1.5.

From inspection of equation 1.4 it is easy to see that the impedance of thetank at the frequency of resonance is determined by the series resistance

of the inductor and its quality factor Q. To obtain a high impedance value at

the resonance it is necessary to dispose of a high quality inductor or what isthe same an inductor with very low series resistance


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Let us analyse in the following section which are the implications of this

statement in the design of low noise amplifiers and voltage controlled

oscillators.

2.1.1 Low Noise Amplifiers (LNA)

As shown by Figure 1 -2 the LNA is the first gain stage in the receiver

path. The most important requirements for the LNA are detailed below.

1.

2.

3.

4.

To provide enough gain to overcome the noise contribution of

the next stages in the receiver path.

To add as little noise as possible.

To provide impedance to the RF antenna at the input andimpedance to the RF Filter at the output, with the minimum external

components. The overall gain should be insensitive to tolerances of

typical external components.

To provide enough linearity at the output.

Applying the Friis equation to a simple front-end consisting of a LNA

and a mixer, the noise factor of the whole front-end can be expressed as

follows (Equation 1.6).

The equation 1.6 shows the importance of the LNA performance in the

whole receiver chain. The LNA must provide enough gain to

overcome the noise of the next stages, adding as little noise as

possible. Once explained the importance of the LNA gain in the performanceof the whole front-end let us analyse the typical LNA configuration. Figure

1-6 shows the most extended differential topology in Bipolar and CMOS

technologies for narrow-band applications.

It consists in a cascode stage and a LC tank. This configuration is

expected to achieve near optimum noise performance while providing a

specific input and output impedance [Sha97].


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12 Introduction

Let us consider now the simplified small signal equivalent circuit for theCMOS LNA (Figure 1-7).


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Where is the transconductance of the transistor is the

equivalent parallel inductance of the inductor L, is total capacitance due

to the capacitor C and the terminal capacitances of the transistor

is the total parallel resistance due to the output resistance of the cascode

stage and the equivalent parallel resistance of inductor L, and finally isthe source inductance of transistor

From inspection of the circuit of Figure 1-7 and not considering the

effect of we can obtain that the gain of the low noise amplifier at the

frequency of interest, the frequency of resonance, is determined by the

impedance of the LC tank and the transconductance of the input

transistor. The obtained gain is expressed by equation 1.7:

where

As we can see from equation 1.7 if we want to design a high gain LNA it

is necessary to implement a LC tank with a high value or what is the

same to dispose of an inductor with a high quality factor.From another point of view, we could consider the case where we were

given a certain gain. If we dispose of high quality inductors we could

achieve this given value of gain with less power consumption, because the

will present a higher value and therefore the required value of will


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14 Introduction

be lower. This statement is especially important when considering mobile

applications. Thus one of keys to progress in the design of low power LNAs

is the implementation of high quality inductors.

2.1.2 Voltage Controlled Oscillators (VCO)

VCOs are key building blocks in wireless transceivers and other

communication systems. As shown in Figure 1-2, the VCO is part of the

frequency synthesizer which generates the LO signal.

The key performance specifications are detailed below.

1.

2.

The power consumption.

The phase noise performance.

The toughest one to achieve is usually the phase noise spec. This is due

to the very narrow channel spacings used in cellular telecommunications

networks, such as GSM or DCS.

Figure 1-8 shows different VCO topologies depending on implemented

feedback [Zan98]. All this topologies have in common that they are LC-

tuned.

This is due to LC-tuned oscillators are expected to have much better

phase noise because they can use the bandpass characteristic of the LC-tank


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to reduce the phase noise. Other types of oscillators, like ring oscillator,

suffer from switching effects that can introduce noise in the power supply,

and have therefore a worse phase noise than LC-tuned oscillators.

A strong effort has been done in order to explain and model the phase

noise performance of LC-tuned oscillators [Cran98, Cran95, Lee00]. For

instance, equation 1.9 mathematically expresses the phase noise performance

of the basic LC-tuned oscillator of Figure 1-9 operating in the linear region

[Cran95], where is associated with the series resistance of the capacitor,

with the series resistance of the inductor and with the output

resistance of the transconductor and the parallel resistances across C and L.

Where is the oscillation amplitude, the oscillation frequency

which is equal to the resonance frequency of the LC tank, A is a factor

equal to or larger than 1 that takes into account the active element

contribution to the phase noise, and finally is the effective resistance of

the tank, which is equal to:


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16 Introduction

If we considerer equations 1.9 and 1.10, we can deduce two efficientways to improve the phase noise performance of the oscillator. The first one

is to enlarge the oscillation amplitude and thus making the signallarger than the noise. And the second one is to reduce the effective resistance

of the tank.Due to the fact that at RF frequencies inductors usually dominate the

quality of the tank [Her02], it is the passive component which

determines the phase noise performance of the VCO. Thus to design a VCO

with low phase noise it is necessary to dispose of high quality inductors.As we have mentioned at the beginning of this section the other

important spec when designing VCOs is the power consumption, specially

if it is intended to be used in a mobile application.The necessary power consumption to maintain the oscillation in the basic

LC-tuned oscillator is given by equation 1.11 [Cran95]:

If we analyse equation 1.11 we can deduce two ways to reduce thenecessary power consumption to maintain the oscillation. The first one is for

a given frequency of oscillation to reduce the capacitive part of the tank and

increase the inductive part while not decreasing the quality factor of thetank. The second one is to decrease the effective resistance of the tank orwhat is the same to increase the quality factor.

Therefore, like in the design of low power LNAs, one of the keys to

progress in the design of low power VCOs is the implementation of highquality inductors.

In next sections we will see other applications of integrated inductors likeinductive degeneration for input and output matching purposes and RFfiltering.

2.2 Inductive degeneration for matching purposes

Many RF circuits need to match their input and/or their output ports to aimpedance value, in order to maximize the transferred power between

the different RF circuits or blocks. That is the reason why, as mentioned insection 1.2.1.1, one of the most important requirements for the LNA is toprovide impedance to the RF antenna at the input and to the RF


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Filter at the output. It forces in certain occasions to place matching networksat the input and output ports of the circuit to fit its impedance to

There are many methods to match the input and output ports of RFcircuits. Probably the simplest one uses a matching network based on

resistances, so that the influence of the frequency on the impedance value isminimized. A broadband matching is obtained with this method. But it has

an important drawback; it is the excess of generated noise which seriously

affects the yield of the circuit.A method, widely used, that avoids the matching of the input and output

ports by means of resistances is the so called inductive degeneration[Rud97]. This method is broadly used in the design of narrow band LNAsand mixers, since it is the matching configuration which presents the best

noise performance. Figure 1-10 shows the case of a low noise amplifier(LNA) which input port is matched using the inductive degenerationconfiguration.

The provides the ground connection of the LNA. It plays twoimportant roles in the circuit:

1.

2.

As already mention, it allows conjugate matching of the input.

Linearizes the circuit.

Figure 1-11 shows the small signal equivalent circuit of the input of theLNA of Figure 1-10.


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18 Introduction

If we neglect the effect of and we can write the input impedance

as:

Thus, with proper choice of and we can achieve an input

impedance while the last two terms in equation 1.12

cancel.

For this kind of applications the inductors quality factor is not critical,

but lower quality factors will lead to a decrease in the noise performance of

this matching configuration.

2.3 RF Filters

As mentioned before, low power wireless communication systems are

becoming a dominant force in microelectronic systems. Ultra low power RF

design using Si based technologies will offer low cost components for small

portable wireless communication systems. Regardless of the specific

transceiver architecture, all RF functions require in the receiver path a

bandpass filter with minimum insertion loss to select the frequency band of

interest and in the transmitter path a low pass filter to pass the wanted signal

and eliminate or attenuate harmonics, mainly at the output stage of thepower amplifier.

A strong research effort has been done during recent years to fullfil, with

integrated passive RLC structures, the insertion loss in the pass-band and the

attenuation levels at the harmonics frequencies required by the strict


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commercial specifications. The result has been very poor mainly due to the

low quality factor of the integrated inductors. Thus there is a strong

motivation for the implementation of high quality inductors.

Figure 1-12 shows the typical configuration for a low-pass filter

implemented with inductors and and capacitors and Some

implementations can be found in [Nguy90, Kim02].

3. THE CHALLENGE OF INTEGRATING HIGH

QUALITY INDUCTORS

In this section we are going to explain why the quality factor of the

integrated passive elements is critically determined by the characteristics of

the substrate and the metallization of the technology in which they are

implemented. The different loss mechanisms are shown in Figure 1-13 and

explained in the following paragraphs [Nik00].

It is necessary to mention that in chapter 4 of this book all these effects

are analyzed with greater depth. The objective of this section is only to

introduce the difficulty that entails the integration of RF passive elements in

conventional Si based low cost technologies.


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20 Introduction

3.1 Metal losses

The passive elements generally make use of one or more metallization

layers. For example, an inductor is made up of one or more metal tracks in

parallel forming one or several concentric turns. Usually at lower

frequencies than the frequency of maximum quality, the quality of these

elements is determined by the conductivity of the metal tracks since the

current circulation produces ohmic losses [Agu00], That is the reason why

advanced RF processes, like the B7HF from Siemens, replace the AlSiCumetallizations by copper metallizations, in order to increase the conductivity

of the metal tracks and reduce the series resistance of the integrated

inductors. Other RF processes, like the CMOS process from UMC,

implement a thick top metal layer with higher conductivity to reduce the

resistivity of the metal tracks and increase the quality factor of the integrated

inductors.

At high frequencies, the distribution of the current in the metal tracks

stops being uniform due to skin and proximity effects. In any metal track,the alternating current tends to circulate around the way of minimum

impedance, but due to the magnetic field that penetrates in, generating

electric fields that move the current to the surface, it is accumulated in the

surface of the conductor. As the frequency increases, the effective area


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around which the current circulates decreases increasing to the current

density and therefore losses by Joule effect [Burg96]. That is one of the

reasons why to implement high quality inductors at high frequency is a

difficult task.

Additionally, another effect exists that mainly limits the use of integrated

passive elements in applications in which it is needed to handle high power,for example in power amplifiers. This effect is known as electromigration

and establishes the maximum current density that can handle the metal track

once it is fixed its width [AMS00].

3.2 Substrate losses

The substrate of the low cost silicon based technologies is one of thegreater sources of loss at high frequencies due to its high conductivity,

tipically between 2 and

The conductive nature of the substrate causes several loss mechanisms:

Electric coupling between the different metal layers and the

conductive substrate due to the existing dielectric among them.

Currents induced in the substrate due to the variable magnetic fields

that are originated by the different metal layers and that penetrate inthe substrate.

All these mechanisms reduce the quality factor of the integrated passives.

4. STRUCTURE OF THE BOOK

In this chapter we have seen how the performance of some RF buildingblocks, like LNAs, VCOs or RF Filters, highly depend on the quality

factor of the integrated inductors used to implement them.We have also introduced the difficulty that entails the integration of RF

passive elements in conventional Si based low cost technologies, due to

metal losses and substrate losses.Chapter 2 will cover some general considerations like the physical

analysis of the integrated inductor, the existing electrical models to model

them model, transformer model or wide band modified model), orsome methods to improve the quality factor of an integrated inductor

(Broken guard rings, Substrate shielding, etc.).

Inductors test and characterization is covered in chapter 3. In the

inductor modelling, the accurate measurement of the device is very

important due to the fact that these are elements with very low resistance,


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22 Introduction

where a single ohm makes a big difference in the quality factor. This is the

reason why the book also covers the design of the test fixture and the

measurement setup.

Chapter 4 will analyse the influence of the geometrical parameters in the

inductors performance and will establish the design guidelines for the

definition of the elements geometrical characteristics. It will also introduce

some new techniques to improve the quality factor.

Finally due to the fact that foundries only supply models for discrete

values of inductance, and that these inductances are not wide band modelled

there is a need of an inductors design flow in order to be able to obtain a

specific inductor value, optimized for a specific application or what is the

same a specific frequency range. The inductors design flow is covered in

chapter 5.


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Chapter 2

GENERAL CONSIDERATIONS

In 1990 was reported one of the first Silicon Integrated Circuit with

integrated inductors. It was a passive filter [Nguy90] for radio-frequency

applications. Since then, many advances have been accomplished regarding

the integration of silicon passive components.

This chapter is a review of the state of the art of these devices when

integrated on Silicon technology. It will cover the different methods

available for inductor integration, as well as the latest techniques for

improving their quality. In addition, after studying in detail the physicalbehavior of spiral inductors and the electrical models utilized to describe

their functionality in the frequency range of GHz, the most common

definitions of inductor quality will be presented.

We will end the chapter giving some rough notes about inductors on non-

conventional fabrication processes.

1. WAYS OF INTEGRATING AN INDUCTOR

This section describes the different configurations that an integrated

inductor can adopt for RF applications, considering both conventional and

non-conventional technologies. By non-conventional technologies it is

meant those technologies allowing stages of post-processing in which some

part of the wafer is eliminated by etching, or where the characteristics of the

different composition layers are modified.

There exist many solutions for the implementation of an inductor and the

designer should understand which configuration is the most appropriated for

his needs.


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24 General considerations

1.1 Conventional fabrication processes

Today, the most common configuration used for the design of an

inductor is known as the geometric spiral. This configuration is simply a

spiral around a center and, depending on the permitted angle between the

metal tracks dictated by the fabrication technology used, the geometry of the

inductor could be squared, hexagonal, circular etc. Figure 2-1 shows four

inductors with spiral geometry and different number of edges.

As it is shown in the previous figure, an inductor can only be fabricated

with technologies having two or more metal layers since the innerconnection requires a metal layer different from the one used by the spiral.

In many instances, it is important to produce an inductor with symmetric

behavior, that is to say, its characteristics should be independent from which

input port the inductor is analyzed. Symmetry will occur when the centers of

the magnetic and electric fields of the inductor coincide, something that

does not happen in spiral geometries. This inconvenience is special relevant

when the inductor is used in differential circuits where the goal is to

minimize or suppress by circuit symmetry interferences of common modelike temperature or voltage supply variations.

To avoid this problem when designing differential circuits, two inductors

rather than one are used, and they are implemented using a mirror

configuration like the one shown in figure 2-2 [Cran97].


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Other possibility to solve the lack of symmetry is by implementing

centre-tapped inductors. There exist different methods to design this kind of

inductor geometries, but the most common is called balanced geometry

[Long97]. A micro-photography of this geometry is shown in figure 2-3. It

can be seen that the level of metallization changes every half turn of the

spiral. In this way, a fairly symmetric geometry is obtained, making viablethe use of these inductors on differential circuits.

Figure 2-4 [Kuhn95] shows another centre-tapped geometry very useful

for application where the differential circuit should be biased through aninductor, like in a VCO with a NMOS configuration.


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Other problem the designer could face is the available area for inductor

integration. This aspect gave rise to the concept of multilevel inductor. This

technique consists in implementing the same spiral in different metal layers,and serially connecting them, as shown in figure 2-5 [Burg96].

With this structure, the mutual inductance among the metal layers of the

inductor increases. This in turn increments the inductance per unit of area,

permitting the implementation of inductors with large inductances within

areas smaller than the areas required by the corresponding mono-level

configurations. For example, in a CMOS process with five metal

layers, it is possible to produce inductors of 45 nH within an area of

[Zolf01].


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Figure 2-6 shows a modification of the geometry shown in the previous

Figure, in order to maximize the inductance per unit area [Agu0l]. The way

the tracks are placed is such that it maximizes the coupling between tracks,

giving as a result an increase of the total inductance.

1.2 Non-conventional fabrication processes

The previous section has presented a review of the different geometriescurrently used for the integration of an inductor with standard fabrication

technology. Depending on the requirements of the designer, there exist a

variety of solutions, for example for the case of a balanced circuit, or when

only a small area is available for the integration of the inductor, etc.

All the previously mentioned geometries can be implemented using

either conventional or non-conventional technologies; however, there exist a

group of geometries that can only be produced by the latter technologies. In

particular they are the solenoidal and toroidal structures.


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It is important to emphasize that these are conventional configurations

used in lumped inductors. In the toroidal case, cores of iron-nickel in two

metallization levels are also integrated by using micro-mechanization, and

strips of copper metallization are then wrapped around them, as shown in

figure 2-7 a).

In the case of solenoids, either for the inclined or parallel conductor,

(Figure 2-7 b-c), the oxide thickness is increased up to levels that are notviable with standard processes. The reason is that when using standard

processes, thickness larger than [Kim01] will create prohibitive

stresses between the Si and the due to their thermal expansion

coefficients

Also, as in the previous case, magnetic cores are added to coil around

them copper or aluminum metallizations. For example, there have been

reported solenoidal copper inductors with a quality of 16.7 at 2.4 GHz and

an inductance of 2.67 nH [Yoon99].In the case where the designer has access to any of these processes, it is

possible to integrate inductors with the same geometries than lumped

inductors: solenoidal and toroidal, etc. However, all these processes are too

expensive, generally making its commercial application non-viable.

2. SPIRAL INDUCTORS ON SILICON BASED

TECHNOLOGIES

Once explained the different conventional and non-conventional

fabrication options for the integration of an inductor, this section describes in

detail the spiral inductors built on a silicon substrate.


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The section begins analyzing the electromagnetic effects induced by

these inductor geometries, and reviewing some of the most up to date

electrical models used to characterize their behavior in the frequency range

of GHz. Then the quality factor of an inductor is defined, and the section

ends by analyzing some methods to improve the quality of a spiral inductor

for a given geometry.

2.1 Physical overview: Difficulty of integrating an

inductor

As already explained in the previous section, a spiral inductor is built by

a metal strip spiral shaped as a square, hexagon, etc. The spiral is built by

using one of the metal layers embedded in silicon oxide and placed at some

distance from the semiconductor substrate. As it is shown in Figure 2-8,

when a time-varying voltage is applied between the ends of the spiral, three

electrical and one magnetic field are generated.

In what follows the reasons for the generation of theses fields and their

effects on the behavior of the spiral are explained.

Magnetic field B(t): Any time-variant current flowing along a conductor

induces a magnetic field. Two effects are produced:

The self and mutual inductance coupling among the metal tracks

composing the inductor.


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Current is induced in the substrate and metal tracks.

Electric field along the spiral, It is generated as a consequence of

the existing voltage difference between the two ends of the spiral. It

produces:Ohmic losses in the spiral due to the resistivity of the metal tracks.

Electric field passing through the oxide between strips, It is

generated as a result of the existing voltage difference between adjacent

strips, and between those and the inner connection. It produces:

Capacitative coupling among the coils of the inductor.

Electric field passing through the oxide and the substrate It is

generated as a result of the existing voltage difference between the spiral

and the substrate. It produces:

Capacitative coupling between spiral and substrate,

Ohmic losses in the conductor substrate due to displacement

currents induced through the capacitative coupling between the

spiral and the substrate.

Next, each one of these effects is studied more in detail.

2.1.1 Inductance

The inductance of an inductor has two components, self and mutual

inductance.

2.1.1.1 Self inductance

According to Amperes law [Sanc01], an alternating current flowing

along a conductor induces a magnetic field. The self inductance of arectangular conductor was derived by Grover [Grov62] and is written as

Where denotes the conductor inductance in nH, and 1, w, and t

represents the length, width, and thickness of the conductor in cm,

respectively.It is important to mention that expression (2.1) fails to be valid when the

width or the thickness dimensions double the length of the conductor.

However, this is not a restriction for inductor integration since the above

situation never occurs.


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Figure 2-9 shows the self inductance for a rectangular conductorcomputed by using expression (2.1). Length and width dimensions are varied

while maintaining fixed its thickness at This parameter has not been

changed, since in conventional fabrication process it remains fixed to

approximately the above value.

It can clearly be seen the influence that width has in the value of self

inductance. This is due to the fact that inductance is mainly determined by

the outer magnetic flux generated by the conductor [Yue96]. Consequently,

when the width diminishes the self inductance increases.

2.1.1.2 Mutual inductance

Mutual inductance, between two circuits, 1 and 2, can be defined as

the ratio between the flux generated by circuit 1 crossing to circuit 2

and the current that flows in circuit 1 It is determined by equation (2.2).

In case of two parallel conductors the mutual inductance is defined as


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Where M is the inductance in nH, 1 is the length of the conductor in cm

and Q is a coefficient that depends on the geometry, and it is given by

[Ling98].

GMD is the geometric average of the distance between the areas of the

two conductors. The GMD between two areas can be obtained by

partitioning the areas in differential intervals elements and computing the

geometric average of the distance between these elements like it is shown inFigure 2-10.

The geometric average of the distance between these two areas is

computed in the following way:

Where n and m denote the number of differential elements within areas

A' and A, respectively. Dij' is the distance from element i in area A, toelement j in area A'. For the case of two conductors with rectangular shape,

the GMD is defined as [Moha99]

Where w and d are the width and distance, center to center, between the

conductors in cm, respectively. Figure 2-11 and Figure 2-12 show the

mutual inductance between two rectangular conductors of length as

a function of the distance center to center and separation, respectively. These

curves are displayed for three different widths.


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As it can be observed, the mutual inductance hardly varies with the

width of the strip when the distance center to center remains fixed. This

implies that the value of mutual inductance of coils, having the same

distances between spirals barely change when the width of the strips is

modified.


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2.1.1.3 Total inductance

Total inductance of a conductor in a system is given by the sum of three

terms. The self inductance plus the sum of the magnetic couplings of those

conductors (represented by mutual inductances) that contribute to increase

the self magnetic flux, minus the sum of magnetic couplings of theremaining conductors that reduce the self magnetic flux of the original

conductor. In other words

Based on the study of Grover, equation (2.1), Greenhouse [Gree74]developed an algorithm to compute the inductance of a planar rectangular

spiral. The method determines the total inductance of a rectangular spiral asthe addition of the self inductance contributions of each segment forming thespiral, plus the sum of the positive and negative mutual inductances of allsegment pair combinations.

Mutual inductance between two segments depends on their angle of

intersection, length and separation. Two orthogonal metal tracks have nomutual inductance since their magnetic fluxes are not linked together. Inparallel metal tracks the sign of the mutual inductance is set by the direction

of the current. This last consideration is shown in Figure 2-13 [Soye98].Later, other algorithms suitable for calculating the inductance of

inductors with different geometries (hexagonal, etc) had appeared in theliterature. However, due to their computational complexity they are moreappropriated to be used with simulation tools than for analytic calculations.


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After having analyzed the inductance of an integrated spiral inductor, it

is proceed to study the second most important characteristic of these

elements: resistance.

2.1.2 Resistance

When a DC current flows through a conductor, the current distribution is

uniform over its entirely surface. A conductor has a value of resistance, since

it presents a resistivity to any current carried by the conductor. This value isgiven by

Where is the resistivity, L the length and A the conductor area. As

frequency increases, the resistance is no longer constant due to the fact that

distribution of the current is not uniform across the conductor cross section.In case of a spiral inductor the dependence of the resistance with frequency

not only depends on the conductor itself (skin effect) but also on the

influence of neighborhood strips (proximity effects).


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2.1.2.1 Skin effect

The skin effect in a conductor accounts for the alteration of the current

density distribution from the magnetic field generated by the current itself.

As it is shown in Figure 2-14, when a magnetic field generated by a

current in a conductor crosses its cross-section induces a force over the

current itself. This force is perpendicular to the magnetic field and to the

direction of the current flow. This effect is known as Lorenzs force

[Lore01].

As it can be observed, the current is pushed toward the outer surface of

the conductor. The higher the frequency is, the higher the resistance of the

conductor will be, since the current is restricted to a small part of its totalcross-sectional area.

The influence of the skin effect over the resistance of a conductor is

evaluated by means of the skin depth. This parameter is defined as the

equivalent thickness of a hollow conductor having the same resistance at the

frequency of interest. As an example, for a cylindrical wire the skin depth is

defined as [Ling98]


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Where is the magnetic permeability of the material, the conductivity

and the angular frequency of interest. The resistivity of this conductor is

then defined as

Where is the skin depth in cm, is the conductivity in is

the magnetic permeability of the conductor in and f is the frequency of

the AC current [Stey01].

2.1.2.2 Proximity effects

Proximity effects in a conductor are a consequence of the influence of an

external time-varying magnetic field over the conductor. In this case, an

induced current is generated regardless whether or no there is a current flow

through the conductor. In case there is an alternating current, the skin effect

and the proximity effect will add together, changing the current distribution

and increasing the resistance of the conductor [Sanc01].

The induced currents in the tracks of a spiral inductor have a negative

side effect, especially in the inner coils turns since it is in the center of the

spiral where the magnetic field reaches its maximum intensity. In a fullywinding coil (the coil turns reach the center) a large portion of the magnetic

field passes through the inner coil turns, inducing in these turns a strong

current density, and therefore increasing their resistivity. When adding this

effect to the small inductance contribution from the inner coil turns with

respect to the outer coil turns due to the difference in length, one conclude

that it is better to fabricate hollow inductors [Stey01].

This section began by studying the variations of the resistance of a

conductor due to the magnetic field induced by an alternating current carriedby the conductor itself, without considering any external influence. Latter it

has been shown that when a wire is within a system of conductors, like for

example a spiral, the variation of the resistance versus frequency it is not

only due to skin effects but also to proximity effects.

2.1.3 Parasitic effects in the substrate

When an inductor is integrated on a Silicon based technology, some

undesirable induced effects show up. The reason being that the metallic

layers are separated from the semiconductor substrate by a layer of silicon


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oxide. These effects can be classified in two types, magnetically induced and

electrically induced.

2.1.3.1 Magnetically induced parasitic effects in the substrate

One of the fundamental properties of an inductor is that generates amagnetic field. This alternating field penetrates into the conductive substrate

and induces a voltage difference, which in turn generates a current. This

phenomenon diminishes the energy in the coil, decreasing at the same time

the quality of the inductor.

Figure 2-15 schematically shows this effect for a cross section cut of an

inductor integrated on Silicon technology. It is important to mention that

some studies indicate that the radius of the spiral approximately gives the

depth of penetration of the magnetic field into the substrate [Yue96].

Inductance is other parameter affected by the induced currents in the

substrate. These currents flow in the opposite direction than the current

carried by the coil, resulting in a reduction of the magnitude of the total

magnetic field. Therefore, the value of the inductance will decrease, since

the inductance is defined as the ratio between the magnetic flux and the

current in the spiral [Cran97].

2.1.3.2 Electrically induced parasitic effects in the substrate

Other parasitic effect that shows up in Silicon integrated inductors is the

capacitative coupling between the inductor and the substrate. The reader can

understand this effect by realizing that a capacitor is just two conductive


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plates (metallic layer form by the inductor and semiconductor substrate)

separated by a dielectric (Silicon oxide), as shown in Figure 2-16. This has a

negative effect since depending on the capacity and the frequency, a portion

of the inductor energy will be stored in this capacitor. It could even happen

that the inductor starts behaving like a capacitor rather than as an inductor.

The value of the frequency where this occurs is called resonance frequency

of the inductor

In addition, ohmic losses are produced since there are displacement

currents induced in the substrate. This is illustrated in Figure 2-17.


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2.1.4 Parasitic capacitance between metal turns

When a voltage is applied to the ends of a coil, it creates a voltagedistribution along its metal tracks. Recall on the other hand, that the silicon

oxide isolates the metal tracks of a spiral inductor. Therefore, due to the

structure metal/oxide/metal appears a parasitic capacitor between the metal

tracks. On the other hand, there is a voltage difference between the plates so

energy will be accumulated in the capacitor. This capacitance is called

parasitic capacitance between metal turns. Figure 2-18 schematically shows

this effect.

This capacitance includes both the adjacent capacitance between tracks

on the same metallic layer and the vertical capacitance between tracks

located on different layers.


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As it can deducted from this section the common property of all low

price fabrication technologies this is the low substrate resistivity

propitiates the occurrences of undesired effects. Clearly this is a greathandicap when designing inductors in this kind of technologies due to the

poor quality.

2.2 Spiral inductor electrical models

This section provides a review of integrated inductors electrical models

use to describe their behavior in the range of GHz under the constraint of

low cost fabrication technologies. There exist several models with the

model [Nguy92] being the most well known the transformer model

[Matt0l] and the wideband model [Pino02]. It is important to mention

that the parameters of the electrical circuits representing these models are

not only empirical but they also have a physical meaning. In what follow

these models are explained in detail.

2.2.1 model

Due to its simplicity the model is the most common model utilized

today by the designers. It is simple its parameters are easy to adjust toempirical data and they have a clear physical meaning. As a drawback it is

a narrow band model that is to say it is only valid for modeling the

behavior of an inductor in a small range of frequencies. For this reason it is

normally used only to model the spiral at the frequency of interest [Pino02].


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As it can be seen from Figure 2-19 the model uses ideal components

such as resistors inductors and capacitors. These elements present a clearcorrelation with the behavior of an integrated inductor in a Silicon based

fabrication technology.

accounts for both the capacitance among the strips and between the

strips and the coil inner connection. Its value is usually negligible

represents the inductor resistance it accounts for the ohmic losses due

to the metal track resistance induced effects in the metallic conductor

and magnetic induced currents in the substrate.

models the inductance of the coil.

represents the parasitic capacitance between the metal of the spiral

and the substrate.

accounts for the ohmic losses in the substrate produced by the

displacement currents induced in the substrate.

models the capacitative effects of the substrate due to its

semiconductor characteristics.

As it has been said before the drawback of the Model is that many of

its components like resistance inductance substrate parasites etc. depend

on frequency. This makes the model only valid for a small range of


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frequencies to 1 GHz) or when losses in the substrate are

negligible [Pino02].

In 1996 Patrick Yue [Yue96] developed expressions for the computation

of each parameter in the model as a function of the inductor geometric

values and fabrication process parameters. These expressions are given by:

Where w is the width and t the depth of the strip 1 the length of the

spiral the skin depth at the considered frequency and the resistivity of

the metal.

The inductance is computed by using the H.M. Greenhouse algorithm

explained in section 2.1.1.3.

Where n is the number of crossings between the coil and the centrallower connection w is the width of the strips is the oxide dielectric

constant is the oxide depth between the spiral tracks and its central

interconnection.

Where l is the length of the metallic spiral w is the width of the stripis the depth of the oxide and is the oxide dielectric constant.

Where are the substrate capacitance and conductance per unit

area respectively. These two constants are empirically computed.


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It is important to emphasize that the above expressions allow a

qualitative rather than a quantitative analysis of the inductor since there are

limitations in the validity of some of the equations. For example the

resistance is computed based only on the DC resistance of the metal and

on the skin effect without considering the losses resulting by the proximity

effects of the metal and substrate. Other drawback is that the proposed

expression for the computation of the resistance is more appropriate for

circular conductors rather than rectangular.

The model just described is only valid when none of the two ports of

the inductor is connected to AC ground. When this is not the case the

resulting model is simpler and is called the one-port model. Figure 2-20

shows this model.

The meaning of the parameters of the one port model is identical to itscounterpart the two-port model.

2.2.2 Transformer model

The transformer model arises as an evolution of the model. As shown

in Figure 2-21 its main advantage is that permits independently characterize

the effect of the induced magnetic field in the substrate.


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The parameters of this model are identical to the corresponding

parameters in the two-port model. However the model has threeadditional parameters describing the effect of the magnetic induced current

design of inductor

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