design of low power nyquist a2d.pdf

8/11/2019 Design of low power nyquist A2D.pdf

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Abstract

ThescalingofCMOStechnologieshasincreasedtheperformanceofgeneral

purpose processors and DSPs while analog circuits designed in the same

processhavenotbeenable toutilize theprocessscaling to thesameextent,

sufferingfromreducedvoltageheadroomandreducedanaloggain.Inorderto

designefficientanalogtodigitalconvertersinnanoscaleCMOSthereisaneedto both understand the physical limitations as well as to develop new

architecturesandcircuits that take fulladvantageofwhat theprocesshas to

offer.

This thesisexplores thepowerdissipationofNyquist rateanalogtodigital

convertersandtheirlowerbounds,setbyboththethermalnoiselimitandthe

minimumdevice and feature sizesofferedby theprocess.Theuseofdigital

errorcorrection,whichallows for lowaccuracyanalogcomponents leadstoa

power dissipation reduction. Developing the bounds for power dissipation

basedonthisconcept, it isseenthatthepowerof lowtomediumresolution

convertersisreducedwhengoingtomoremodernCMOSprocesses,something

whichissupportedbypublishedresults.

The design of comparators is studied in detail and a new topology is

proposed which reduces the kickback by 6x compared to conventional

topologies. This comparator is used in two flash ADCs, the first employing

redundancy in thecomparatorarray,allowing for theuseofsmallsized, low

power, lowaccuracy comparators to achieve an overall lowpower solution.

TheflashADCachieves4effectivebitsat2.5GS/swhiledissipating30mWofpower.


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Theconceptof lowaccuracycomponents istakento itsedge inthesecond

ADC which does not include a reference network, instead relying on the

process variations to generate the reference levels based on the mismatch

induced comparatoroffsets.The referencefreeADCachievesa resolutionof

3.69bitsat1.5GS/swhiledissipation23mWshowingthatprocessvariations

notnecessarilymustbeseenasdetrimentaltocircuitperformancebutrather

canbeseenasasourceofdiversity.


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Preface

This licentiate thesispresentsmy research during the periodMarch 2006 to

July2009attheElectronicDevicesgroup,DepartmentofElectricalEngineering,

LinkpingUniversity,Sweden.Thefollowingpapersareincludedinthethesis:

PaperI

Timmy

Sundstrm,

Boris Murmann and Christer Svensson,

Power Dissipation Bounds for HighSpeed Nyquist AnalogtoDigital

Converters, in IEEE Transactions on Circuits and SystemsI: Regular

Papers,Vol.56,No.3,pp.509518,March2009.

PaperII TimmySundstrmandAtilaAlvandpour,AKickbackReduced

Comparatorfora46bit3GS/sFlashADCina90nmCMOSProcess,in

MixedDesignof IntegratedCircuitsandSystems,MIXDES,Ciechocinek,

Poland,2123June2007.

Paper III Timmy Sundstrm and Atila Alvandpour, A 6bit 2.5GS/s

FlashADCusingComparatorRedundancyforLowPowerin90nmCMOS,

accepted for publication inJournalofAnalog IntegratedCircuitsand

SignalProcessing,Springer,August2009.

Paper IV Timmy Sundstrm and Atila Alvandpour, Utilizing Process

VariationsforReferenceGenerationinaFlashADC,inIEEETransactions

onCircuitsandSystemsII:ExpressBriefs,Vol.56,No.5,pp.364368,

May2009.


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The research has also generated the following peerreviewed publications

whicharenotincludedinthethesis:

Timmy Sundstrm andAtilaAlvandpour, A comparative analysisof

logicstylesforsecureIC'sagainstDPAattacks,inProceedingsofthe

23rdNorchipconference,Oulu,Finland,Nov2122,2005,pp297 300.

TimmySundstrm,BehzadMesgarzadeh,MattiasKrysander,Markus

Klein, IngemarSderquist,AnneliCrona,TorbjrnFranssonandAtila

Alvandpour,PrognosticsofElectronicSystemsthroughPowerSupply

Current Trends, in International Conference on Prognostics and

HealthManagement2008,PHM2008.

TimmySundstrm and Atila Alvandpour, A 2.5GS/s 30mW 4bit

Flash ADC in 90nm CMOS, in Proceedings of the 26rd Norchip

conference,Tallinn,Estonia,Nov1617,2008,pp264 267.


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Abbreviations

ADC Analogtodigitalconverter

AGC Automaticgaincontrol

CMOS Complementarymetaloxidesemiconductor

DNL Differentialnonlinearity

DR Dynamicrange

INL Integralnonlinearity

LSB Leastsignificantbit

LUT Lookuptable

MLSD MaximumlikelihoodsequencedetectionMMF Multimodefibre

MSB Mostsignificantbit

PCM Pulsecodedmodulation

PCB Printedcircuitboard

PLL Phaselockedloop

SAR Successiveapproximationregister

SINAD Signaltonoiseanddistortionratio


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SNDR Signaltonoiseanddistortionratio

SNR SignaltonoiseratioUWB Ultrawideband


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Acknowledgments

I would especially like to thank the following persons for their support and

encouragement.

MysupervisorProfessorAtilaAlvandpour,forthesupportandguidance

andforkeepingmefocusedonthatwhichisrelevant.

ProfessorChristerSvenssonforallvaluablediscussionsandinsight.

Dr. Martin Hansson for the great collaboration with tapeouts and

teachingandforbeingagreatfriend.

M.Sc.JonasFritzinforyourgreatfriendshipandsupport.

Dr. Henrik Fredriksson and Dr. Stefan Andersson for all the valuable

technicaldiscussions.

OursecretaryAnnaFolkessonforhelpingwiththenontechnicalaspects

ofbeingaPh.Dstudent.

ResearchEngineerArtaAlvandpourforhisassistanceinawidevarietyof

problems.

All the past and present members of the Electronic Devices research

group especially, Ass. Prof. Jerzy Dabrowski, Ass. Prof. Behzad

Mesgarzadeh,Adj.Prof.AzizOuacha,Adj.Prof.TedJohansson,Dr.Peter


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Caputa,Dr.HkanBengtsson, ,Dr.RashadRamzan,Dr.NaveedAhsan,

Dr. Christer Jansson, Dr. Ingemar Sderquist, Dr. Sriram Vangal, M.Sc.

ShakeelAhmad,M.Sc.AliFazli,M.Sc.DaiZhangandM.Sc.AminOjani.

Allmyfriendsforenrichingmyoutofworklife.

Myfamily,especiallymyparentsforalltheloveandsupport.

FinallyIwouldliketothankCamillaforallthepatienceandlove,andfor

alwaysbeingthereforme.

TimmySundstrm

Linkping,October2009


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TableofContents

Abstract iii

Preface v

Abbreviations

vii

Acknowledgments ix

ListofFigures xv

PartIDesignofHighSpeedADCs 1

Chapter1Introduction 3

1.1 IntroductiontoAnalogtoDigitalConverters..................................3

1.2 BriefHistoryandTrends..................................................................3

1.3 Applications.....................................................................................4

1.3.1 UltraWidebandRadio..................................................................................4

1.3.2 SerialLinkApplications.................................................................................5

1.4 MotivationandScopeoftheThesis.................................................5

1.5 OrganizationoftheThesis...............................................................7

1.6 References.......................................................................................7


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Chapter2AnalogtoDigitalConversionBasics 9

2.1 TheAnalogtoDigitalConverter......................................................92.2 QuantizationError...........................................................................9

2.3 StaticErrors....................................................................................12

2.4 DynamicErrors...............................................................................13

2.5 References.....................................................................................14

Chapter3HighSpeedADCArchitectures 15

3.1 FlashADCs......................................................................................16

3.1.1 InherentSampleandHold..........................................................................17

3.1.2 FlashDecoders............................................................................................18

3.1.3 FlashADCPerformance..............................................................................18

3.2 InterpolatingandFoldingADCs.....................................................19

3.2.1 FoldingADCPerformance...........................................................................21

3.3 SuccessiveApproximationandAlgorithmicADCs..........................21

3.3.1 RedundancyorReducedRadix...................................................................23

3.3.2 PerformanceofSuccessiveApproximationADCs.......................................24

3.4 PipelineADCs.................................................................................24

3.4.1 PipelineADCPerformance..........................................................................263.5 InterleavedADCs............................................................................26

3.5.1 PerformanceofInterleavedADCs..............................................................27

3.6 References.....................................................................................28

Chapter4TheCMOSProcessanditsLimitations 33

4.1 EffectsandLimitationsduetoScaling...........................................33

4.1.1 ReducedSupplyVoltage.............................................................................33

4.1.2 IncreasedTransitFrequency.......................................................................34

4.2 MatchingandProcessVariations...................................................354.3 OvercomingScalingandProcessVariations..................................37

4.4 References.....................................................................................37

Chapter5DesignConsiderationsforHighSpeedADCs 41

5.1 PowerDissipationofADCs.............................................................41

5.1.1 NoiseofSampling.......................................................................................42

5.1.2 PowerDissipationBounds..........................................................................43

5.1.3 ApproachingThermalNoiseLimitedPipelineADCs...................................46

5.2 ComparatorDesign........................................................................48


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5.2.1 PreamplifierandLatchTopology...............................................................48

5.2.1.a ComparatorNoise...................................................................................49

5.2.1.b ComparatorSpeed..................................................................................50

5.2.2 SenseamplifierbasedComparator............................................................50

5.2.2.a ComparatorNoise...................................................................................51

5.2.2.b ComparatorSpeed..................................................................................51

5.2.3 ComparatorOffset......................................................................................52

5.2.4 Kickback......................................................................................................52

5.2.5 Metastability...............................................................................................54

5.3 DesignTradeoffs...........................................................................54

5.3.1 TradeoffsinFlashADCs.............................................................................555.3.2 Redundancy................................................................................................55

5.4 References.....................................................................................56

Chapter6FutureWork 59

PartIIPapers 61

PaperI 63

I.I Introduction...................................................................................64

I.II Preliminaries..................................................................................65

I.III PowerDissipationofADCComponents.........................................70

I.IV PowerDissipationofADCs.............................................................75

I.V CaseStudies...................................................................................81

I.VI Conclusion......................................................................................85

I.VII Appendix........................................................................................86

I.VIII References.....................................................................................88

PaperII

91

II.I Introduction...................................................................................92

II.II DifferentialPairComparator..........................................................94

II.III Kickbackeffects............................................................................94

II.IV ProposedComparator....................................................................96

II.V ADCImplementation.....................................................................98

II.VI PerformanceComparison..............................................................98

II.VII Conclusions..................................................................................101

II.VIIIReferences...................................................................................101


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PaperIII 103

III.I Introduction.................................................................................104III.II ComparatorRedundancy.............................................................105

III.III ADCArchitecture.........................................................................109

III.IV MeasurementResults..................................................................114

III.V Conclusion....................................................................................118

III.VI References...................................................................................118

PaperIV 121

IV.I Introduction.................................................................................122

IV.II DistributionofReferenceLevels..................................................124

IV.III ADCArchitecture.........................................................................127

IV.IV MeasurementResults..................................................................130

IV.V Conclusion....................................................................................134

IV.VI References...................................................................................135


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ListofFigures

Figure1.1AnalldigitalUWBreceiver.....................................................................................5

Figure2.1Quantizationoftheinputsignal...........................................................................10

Figure2.2Quantizationerrorasafunctionofinputlevel....................................................11

Figure2.3NonlinearstaticerrorsinADCs...........................................................................13

Figure3.1PerformanceregionsofdifferenthighspeedADCarchitectures........................16

Figure3.2 FlashADCarchitecture..........................................................................................17

Figure3.3TheprincipleofinterpolationinADCs.................................................................20

Figure3.4ThefoldingADCarchitectureandfunctionality...................................................20

Figure3.5SuccessiveApproximationArchitecture..............................................................22

Figure3.6ThearchitectureofapipelineADC......................................................................25

Figure3.7ApipelineMDAC..................................................................................................25

Figure3.8InterleavingofADCswiththeuseofdoublesampling........................................27

Figure4.1 ExpectedchangeinsupplyvoltageaccordingtotheITRS....................................34

Figure4.2 ExpectedchangeintransitfrequencyaccordingtotheITRS...............................34Figure4.3 Lithography limitations leading to systematicerrors in transistorwidths

afterfabrication..............................................................................................................36

Figure 4.4 The source of two major process variation contributors, line edge

roughnessandrandomdiscretedopantvariations.......................................................36

Figure5.1(a)Samplingan inputsignalonacapacitorand(b)theequivalentmodel

withtheswitchonresistanceandnoisesource............................................................42

Figure5.2 TrendofdecreasingpowerdissipationforflashandpipelineADCs.P/fshas

halvedevery2.2yearsoverthepasttwelveyears........................................................44

Figure 5.3 Power dissipation in relation to Ps for flash ADCs of the last 12 years

togetherwiththeresultsoftheconvertersofPaperIIIandPaperIV.ThepowerdissipationboundofflashconvertersderivedinPaperIisshownwithasolidline,


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shownasadashedlineisthepowerdissipationboundwhenthedigitalpowerof

aLUTisalsoincluded......................................................................................................45

Figure5.4Powerdissipation in relation toPs forpipelineADCsofthe last12years

especially highlighting the ones from the last two years showing a significant

improvement inpowerefficiency.Thebound forpipelineADCs fromPaper I is

shownasa solid lineand thedashed line is the sumof thepowerdissipation

boundandthepowerdissipationofadigitalcorrectionLUT........................................47

Figure5.5Comparatorconsistingofapreamplifierandalatch.........................................48

Figure5.6SenseamplifierbasedComparator......................................................................51

Figure5.7Partofasenseamplifierbasedcomparator,highlightingthesourceofthe

kickbacknoise.................................................................................................................53

Figure5.8Proposedkickbackreducedsenseamplifierbasedcomparator........................53

Figure I.1 Comparison of published ADC powerdissipation data and minimumrequiredsamplingpower(PS)........................................................................................68

FigureI.2 TrendofdecreasingpowerdissipationforflashandpipelineADCs.P/fshas

halvedevery2.5yearsoverthepasttenyears..............................................................69

Figure I.3 Switchedcapacitorgain stage. (a)Schematicwith switchesand feedback

network.(b)Modelforanalysisintheredistributionphase ( )2 .................................73FigureI.4 PredictedpowerboundsforprocesslimitedpipelineADCs[(I.27)]andflash

ADCs[(I.29)]togetherwithADCsurveydata ( ),o .Thefollowingtypicalprocessparameterswereused.(350nmCMOS) 3=FSV V, 300=effV mV,and 3min =C fF.

(90nm CMOS) 1=FS

V V, 100=eff

V mV, and 1min

=C fF. (Other parameters)

5.0+= SNRBitsn , 1= ,and 300=T K.......................................................................79

FigureI.5 PredictedpowerlimitsforpipelineADCs[purelyprocesslimited(I.27)and

withadditionalcapacitormatchingconstraints (I.35)]togetherwithsurveydata

( ) . The following typical process parameters were used. (350nm CMOS)3=FSV V, 300=effV mV,and 3min =C fF.(90nmCMOS) 1=FSV V, 100=effV mV,

and 1min

=C fF.(Otherparameters) 5.0+= SNRBitsn , 1= , 1=CK 2

/ mfF ,

%1=K m,and 300=T K..........................................................................................80

FigureI.6 Experimentaldatapointsusedforourcasestudy(90nmpipelineADC[29]

and 90nm flash ADC[30]). The labels marked stages only and comp only

representthe SfP / valuescountingonlypowerdissipatedinthepipelinestages

andflashcomparators,respectively.Alsoshownforcomparisonarethecurvesof

FigureI.4for90nmtechnology.....................................................................................83

FigureI.7 (a) effV versus GSV and Tf versus GSV fornMOSdevicesin90 and350nm

technology......................................................................................................................87

FigureII.1 Kickbackfromthecomparatortotheinputs.......................................................93

FigureII.2Originalsenseamplifierbasedcomparator.........................................................94

FigureII.3Modelforthedifferentialpaircurrents...............................................................95

FigureII.4 Proposedkickbackreducedcomparator.............................................................97

FigureII.5 Proposedkickbackreducedcomparator.............................................................97FigureII.6Drainandsourcevoltagesoftheproposedcomparator......................................97


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FigureII.7 FlashADCarchitecture..........................................................................................98

FigureII.8ADCchipmicrograph.............................................................................................99

FigureII.9Drainandsourcevoltagesoftheinputtransistors.............................................100

FigureII.10 Referencevoltagesufferingfromkickbackunderoneclockcycle.................101

Figure III.1 Meanachievableeffectiveresolutionofa6bitFlashADCusingdifferent

calibrationtechniques..................................................................................................107

FigureIII.2 Meanachievableeffectiveresolutionsfora10bitFlashADC..........................108

FigureIII.3 FlashADCArchitecture......................................................................................108

FigureIII.4 Differentialpairsenseamplifierbasedcomparator..........................................110

FigureIII.5 ExternalSPIcontrolinterfaceandclockgatingcircuit......................................111

FigureIII.6 63to6bitWallaceTreeDecoder......................................................................112

FigureIII.7 Atransmissiongatefulladdercell.....................................................................112

FigureIII.8 ThePCBwiththedirectlybondeddie................................................................113FigureIII.9 Chipmicrograph.................................................................................................113

Figure III.10 Differential nonlinearity (DNL) and integral nonlinearity (INL) of the

ADC...............................................................................................................................114

FigureIII.11 EffectivenumberofbitsandSNDRvs.samplingfrequency............................115

FigureIII.12 EffectivenumberofbitsandSNDRvs.inputfrequency..................................115

FigureIII.13 Outputwaveformshowingevery32ndsamplewith256samplepointsat

2.5GS/sandaninputfrequencyof1.3MHz................................................................116

Figure III.14 Output spectrum showing the fundamental and harmonics inmarked

withcircles.TheSFDRis31.3dBFSandtheSNDR25.5dB..........................................116

FigureIV.1 Distributionofreferencelevelsinrelationtotheideallocationsofa4bitADC...............................................................................................................................125

Figure IV.2 ENOB assuming only static errors, achieved for an ADC with normally

distributedreferencelevels..........................................................................................126

FigureIV.3ArchitectureoftheFlashADC............................................................................128

FigureIV.4Wallacetreedecoder(63to6bits)...................................................................129

FigureIV.5 Transmissiongatefulladdercell.......................................................................129

FigureIV.6 Senseamplifierbasedcomparator...................................................................131

FigureIV.7 ENOB/SINADversusinputfrequency................................................................131

FigureIV.8MicrographofthefabricatedADC.....................................................................134


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3

Chapter1

Introduction

1.1 IntroductiontoAnalogtoDigitalConverters

Ananalogtodigitalconverter(ADC)actsasabridgebetweentheanalogand

digital worlds. It is a necessary component whenever data from the analog

domain,throughsensorsortransducers,shouldbedigitallyprocessedorwhen

transmittingdatabetweenchipsthrougheitherlongrangewirelessradiolinks

orhighspeed transmissionbetween chipson the sameprinted circuitboard

(PCB).

1.2 BriefHistoryandTrends

The first documented example of an ADC was a 5bit, electrooptical and

mechanical flashtype converter patented by Paul Rainey in 1921, used to

transmit facsimile over telegraph lines with 5bit pulsecoded modulation

(PCM)[1].

Thefirstallelectrical implementationcame in1937byAlecHarveyReeves,

thisalsohada5bit resolutionand theADCwas implementedby converting


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4 Introduction

theinputsignaltoatrainofpulseswhichwascountedtogeneratethebinary

outputatasamplerateof6kS/s[1].

Followingthis,thesuccessiveapproximationADCwasdevelopedin1948by

Black,EdsonandGoodalltodigitizevoiceto5bitsat8kS/s[1].Alsoin1948,a

96kS/s,7bitADCwasdevelopedand itwas implementedusinganelectron

beamwithasensorplacedon theother sideofamask.Themaskhadholes

patternedaccordingtothebinaryweightssothatallbitsweresimultaneously

detected, the pattern also employed Gray coding of the output in order to

reducetheeffectoferrorsinthemostsignificantbit(MSB)transition[1],much

asisdoneinmodernhighspeedflashADCs[2].

Following the development of the transistor in 1947 and the integratedcircuitin1958,theADCdevelopmentcontinuedinthe1960swithforexample

an8bit,10MS/sconverterthatwasused inmissiledefenseprograms in the

UnitedStates [1].During the samedecade,all thecurrentlyusedhighspeed

architecturesweredevelopedincludingpipelineADCswitherrorcorrection.

In the recent years there has been a trend in ADC research to use low

accuracyanalog componentswhichare compensated for through theuseof

digital error correction [3]. The motivation behind this is that analog design

havenotbeenabletobenefitfromprocessscaling inthesamewayasdigital

logicandthereforetherelativelyareacheapdigitallogicisusedtocompensate

fortheshortcomingsofexpensiveanalogcircuits.

1.3 Applications

There aremany applications for analogtodigital converters, ranging from

sensors, audio and data acquisition systems to video, radar and

communicationsinterfaces.Theapplicationswhichrequirethehighestsample

rates in the ADC are typically found in the video, radar and communicationareas.Twoexamplestakenfromthecommunicationdomainaregivenhere.

1.3.1

UltraWidebandRadio

Ultrawideband (UWB) targets high data rates for personal wireless

connectivitywithin 10meters of range. The definition states that any signal

whichoccupiesmorethan500MHzofbandwidthwithinthe3.110.6GHzband

andfollowsthespectralmaskasgivenin[5]isUWB.NoIEEEstandardforUWB

communicationexistsandthe802.16.3ataskgroupassignedtodevelopsucha

standardwasdissolved in2006 [6].However, thedevelopmentand researchsupportingthistechnologyhasproceeded.


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1.4MotivationandScopeoftheThesis 5

A system implementation of a receiver containing a minimum of analog

components isgiven in[4]andshowninFigure1.1.Thedesignchallengesare

thewidebandLNAandAGC,afastswitchingreferencephaselockedloop(PLL)

to facilitate the frequency hopping and a high bandwidth, high samplerate

lowtomediumresolutionADC.

Theactual resolution requirementof theADCwasanalyzed in [4]with the

conclusion thata4bit resolution isenough forUWBapplications.Given that

theAGCconditionsthe inputsignal inanoptimalway,aneffectiveresolution

of3bitisenoughaccordingto[7].

GiventhehighsamplingratesandlowresolutionrequirementsoftheADCs,

theflasharchitectureisthemostcommonlyusedinthesesystems.Thedesign

ofsuchADCsisexploredinChapter3aswellastheresearchpaperspresented

inthisthesis.

1.3.2

SerialLinkApplications

Incurrent10Gb/sEthernet links,multimodefibers(MMF)areusedforthe

optical transmission over distances less than 1 km [10]. The multimode

propagationof these fiberscausessignaldispersionsimilar to those resulting

from multipath fading in wireless links. This requires electronic dispersion

compensation (EDC) implemented in the transceivers. The receiver

implementation is moving towards maximumlikelihood sequence detectors

(MLSD) which requires medium resolution, high speed ADCs in order to be

feasible[8],[9],[10].

Moving towardsevenhighdata rateswith the coming 40Gband100Gb

EthernetstandardsthereisaneedforADCsampleratesof56GS/s[11]forcing

the use of interleaving architectures in order to implement these in the

standardcomplementarymetaloxidesemiconductor(CMOS)processes.

1.4 MotivationandScopeoftheThesis

Whenpushingforincreasingdataratesandlongerbatterylifetimethereisacorrespondingincreaseinthedemandsofbandwidthandpowerdissipationin

ADC

Data out

DAC

LNA AGC

DSP

Figure1.1 AnalldigitalUWBreceiver.


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6 Introduction

the receivers for wireless and wireline applications. The advance in CMOS

technologies has increased the performance of general purpose processors and

DSPs while analog circuits designed in the same process have not been able to

utilize the process scaling to the same extent. In order to design efficient

analogtodigital converters in nanoscale CMOS there is a need to both

understand the physical limitations as well as to develop new architectures and

circuits that take full advantage of what the process has to offer.

In Paper I, the power dissipation of Nyquist rate analogtodigital converters

is explored and the lower bounds, as set by the thermal noise limits, are

investigated. The paper explores the use of digital error correction in order to

use lowaccuracy components with the precision requirements set by the noiselevel and resolution. Also, the bound on capacitance values when determined

by mismatch is explored and overall it is seen that there is a gain in reduced

power dissipation when going to more modern CMOS processes, especially for

the low resolution regions.

The design of comparators is studied in Paper II, which proposes a new

comparator topology which reduces the kickback by 6x compared to

conventional topologies.

This comparator was then used in Paper III which presents a flash ADC with 4

effective number of bits at 2.5 GS/s and which dissipates 30 mW. This is

achieved through the use of lowaccuracy components, utilizing redundancy to

meet the desired resolution. The comparators are designed with small device

sizes in order to get low power dissipation at the cost of lower accuracy. The

reference levels are then stochastically distributed from their nominal levels as

determined by the reference network. In order to save power, comparators

which does not contribute to an increase in resolution are disabled in order to

achieve a good tradeoff between power and resolution.

Finally, the concept of lowaccuracy components is taken one step further inPaper IV which presents a flash ADC which has removed the reference network

altogether and uses the stochastically distributed nature of the comparator

levels as a source of references. This ADC achieved a resolution of 3.69 bits at

1.5 GS/s while dissipating 23 mW showing that the process variations not

necessarily must been seen as detrimental to circuit performance but can also

be viewed of as a source of diversity.


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1.5OrganizationoftheThesis 7

1.5

Organization

of

the

Thesis

This thesis is organized into two parts:

Part I Design of High Speed ADCs

Part II Papers

In the first chapter of Part I, an introduction to analogtodigital converters is

given. Chapter 2 presents the basic concepts of analogtodigital conversion,

highlights difficulties and also describes how the converters can be

characterized. In Chapter 3, common architectures used to implement high

speed ADCs are described. Chapter 4 discusses the CMOS process and thelimitations associated with implementing ADCs in these processes. Chapter 5

investigates the challenges and design considerations associated with designing

highspeed ADCs, such as lower bounds on power dissipation, which is further

discussed in Paper I. Chapter 5 also explores the design of one of the

fundamental ADC building blocks, the comparator. Several different

comparator topologies are presented together with the topology suggested in

Paper II. The design of ADCs typically involves tradeoffs between certain

performance parameters, such tradeoffs are also discussed together with the

results of Paper III and Paper IV which proposes techniques to circumvent some

of these tradeoffs.

Concluding the thesis is Part II which contains the full versions of the

research papers.

1.6 References

[1].

Analog Devices, TheDataConversionHandbook,Newnes, 2005.

[2].

R. A. Kertis, et.al., A 20 GS/s 5Bit SiGe BiCMOS DualNyquist Flash ADC

With Sampling Capability up to 35 GS/s Featuring Offset Corrected

ExclusiveOr Comparators, in IEEEJournalofSolidStateCircuits, Volume

44, Issue 9, pp. 2295 2311, Sept. 2009.

[3].

B. Murmann, A/D converter trends: Power dissipation, scaling and

digitally assisted architectures, in CustomIntegratedCircuitsConference,

pp. 105 112, Sept. 2008.


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8 Introduction

[4]. P.P. Newaskar, R. Blazquez, A.R. Chandrakasan, A/D precision

requirements for an ultrawideband radio receiver in IEEEWorkshopon

SignalProcessingSystems,2002.(SIPS'02), pp. 270 275,Oct. 2002.

[5]. G.R. Aiello, Challenges for ultrawideband (UWB) CMOS integration, in

IEEERadioFrequencyIntegratedCircuits(RFIC)Symposium, pp. 497 500,

June, 2003.

[6]. http://www.ieee802.org, June 2009.

[7].

Y. Vanderperren, G. Leus, W. Dehaene, An Approach for Specifying the

ADC and AGC Requirements for UWB Digital Receivers, in TheInstitutionof Engineering and Technology Seminar on Ultra Wideband Systems,

TechnologiesandApplications, pp. 196 200, April 2006.

[8]. A. Nazemi, et.al., A 10.3GS/s 6bit (5.1 ENOB at Nyquist) time

interleaved/pipelined ADC using openloop amplifiers and digital

calibration in 90nm CMOS, in IEEESymposiumonVLSICircuits, pp. 18

19, June 2008.

[9].

O.E. Agazzi, et.al., A 90 nm CMOS DSP MLSD Transceiver With Integrated

AFE for Electronic Dispersion Compensation of Multimode Optical Fibers at

10 Gb/s, in IEEEJournalofSolidStateCircuits, Volume 43, Issue 12, pp.

2939 2957, Dec. 2008.

[10]. A.C. Carusone, The limits of light: The finite bandwidth of optical fibre

[Open Column], in IEEECircuitsandSystemsMagazine, Volume 8, Issue

2, pp. 56 63, Second Quarter 2008.

[11].

G. Raybon, P.J. Winzer, 100 Gb/s Challenges and Solutions, in Optical

Fiber communication/National FiberOptic Engineers Conference, pp. 1 35, Feb. 2008.


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Chapter2

AnalogtoDigitalConversionBasics

2.1 TheAnalogtoDigitalConverter

The conversion of an analog signal to digital quantizes the input in both time

and amplitude [1]. Quantization in time (referred to as sampling) is performed

either by an explicit trackandhold circuit, as is done in most ADC

architectures, or distributed across several comparators as is done in flash

ADCs. The amplitude quantization (referred to just as quantization)

approximates the input signal given a set of fixed reference levels. The number

of possible quantization levels determine the resolution of the ADC, which is

typically described with the number of binary bits, n, needed to represent the

quantization level.

2.2 QuantizationError

The sampling of an input signal with bandwidth fbwith a sample rate of fsof

twice the signal bandwidth is referred to as Nyquist sampling and given fixed

and equidistant sampling instances this process does not introduce any error asthe signal can be ideally reconstructed [2].


28/75

10 AnalogtoDigitalConversionBasics

In contrast to sampling, the quantization introduces errors which cannot be

removed [2]. This is illustrated for a 3bit ideal ADC in Figure 2.1 showing how anormalized input between 0 and 1 is mapped to the corresponding output

codes using the midriser convention given in [3], where the first transition

occurs qsabove Vmin. Here, qscorrespond to the quantization step size, defined

as in (2.1), and Vminis the lower end of the input range.

qs =VFS

2n (2.1)

Where VFSis the fullscale input range and is defined as:

VFS=Vmax Vmin (2.2)

If the analog input signal is approximated with a corresponding analog output,

Vout as in (2.3) where Dout is the decimal value of the output code then the

quantization error, , is described by (2.4).

OutputCode

Input Level

001

000

011

010

101

100

110

111

1

8

2

8

3

8

4

8

5

8

6

8

7

8

Input signal

Quanzed output

Figure2.1Quantizationoftheinputsignal.


29/75

2.2QuantizationError 11

Vout =qs 1

2

+Dout (2.3)= Vout Vin (2.4)

Ideally, the quantization error is then bound between qs/2and qs/2and varies

with the input signal as shown in Figure 2.2.

For converters with very low resolution there is a strong relationship

between the quantization error and the input signal. However, when the

resolution increases the quantization error becomes less correlated to the

input and can be approximated as noise. The distribution of the quantization

noise can be approximated as uniform white noise [4], given that the resolution

of the ADC is above approximately 4 bits [1]. With this approximation, the

quantization noise power can be calculated as in (2.5).

2 = 1

qs

qs/2

qs/2

2d

= 1qs

3

3qs/2qs/2

= q2s

12

(2.5)

A sinusoidal input signal with an amplitude of VFS/2 then results in an output

signaltonoiseratio (SNR) as expressed by (2.6). Expressing this result in

decibels then results in the famous formula of (2.7).

QuanzaonError

Input Level-qs/2

qs/2

1

8

2

8

3

8

4

8

5

8

6

8

7

8

0

Figure2.2Quantizationerrorasafunctionofinputlevel.


30/75


SNR = Psig

Pnoise

=

V2FS8q2s12

=

V2FS8

V2FS22n 12

= 3 22n

2

(2.6)

SNR= 6.02n + 1.76 [dB] (2.7)

2.3

StaticErrors

Besides the quantization noise, another error source in nonideal ADC is the

deviation between the ideal quantization levels and the actual quantization

levels in the ADC. This result in both linear and nonlinear deviation of the

transfer function between the analog input and the digital output compared to

that of an ideal ADC. Following [3], the linear error can be quantified with

offset and gain error, defined as the values which the input should be

multiplied with, and added to in order to minimize the mean square error

between from the output values. The linear error sources could be important,depending on the application [2], but are often not reported.

The nonlinear errors are quantified using differential nonlinearity (DNL) and

integral nonlinearity (INL). In the IEEE standard for measurements of ADCs [3],

they are defined as:

DNL[k] The difference between the code bin width of code kand the

average code bin width, divided by the average code bin width after

correcting for gain and offset.

DNL The maximum absolute value of DNL for all k.


31/75

2.4DynamicErrors 13

INL[k] The difference between the ideal and actual code transition

level kafter correcting for gain and offset.

INL The maximum absolute value of INL for all k.

The nonlinear error sources are shown for a 4bit ADC in Figure 2.3.

2.4 DynamicErrors

In order to completely quantify ADC performance, also sampling and input

frequency dependant error sources should be characterized. The terms used to

describe the dynamic performance are, as defined in [1]: SNR The ratioof the signalpower to the totalnoisepowerat the

output,measuredtypicallyforasinusoidalinput.

Signaltonoiseanddistortion (SNDR, also SINAD) The ratio of the

signalpower to the total noise and harmonicpower at the output,

whentheinputisasinusoid.

Effectivenumberofbits (ENOB)Definedas in (2.8),whereSNDR is

themaximumSNDRfortheconverter,measuredindecibel.

DigitalOutput

Input Level

Ideal Transfer funcon

Transfer funcon

DNL[10] + 1 LSB

INL[8]

INL[12]

Figure2.3NonlinearstaticerrorsinADCs.


32/75


ENOB=SNDR 1.76

6.02 (2.8)

Dynamic Range (DR) The ratio of thepower of afullscale input

sinusoidaltothepowerofasinusoidalinputforwhichSNR=0dB.

There is a wide variety of sources responsible for causing degradation of the

dynamic performance. Architecture independent examples are finite circuit

bandwidth and clock jitter in sampling circuits, some examples related to

specific architectures will be discussed in Chapter 3 and dynamic errors related

to the comparator functionality can be found in Chapter 5.

2.5 References

[1]. B. Razavi, PrinciplesofDataConversionSystemDesign,IEEE Press, 1995.

[2]. R.J. van de Plassche, CMOS IntegratedAnalogtoDigital and Digitalto

AnalogConverters,2nd

Edition, Kluwer Academic Publishers, 2003.

[3].

IEEE Standard for Terminology and Test Methods for AnalogtoDigital

Converters, IEEE Standard 12412000, 2000.

[4]. P.R. PerezAlcazar, A. Santos, Relationship between sampling rate and

quantization noise, in 14th International Conference on Digital Signal

Processing, pp. 807 810, July 2002.


33/75

15

Chapter3

HighSpeedADCArchitectures

There is a wide variety of different ADC architectures available depending onthe requirements of the application. They can range from highspeed, low

resolution flash converters to the highresolution, lowspeed oversampled

noiseshaping sigmadelta converters. This thesis deals mainly with the design

highspeed Nyquist rate converters. The architectures which are considered

highspeed in this context are:

Flash ADCs The most parallel converter architecture. The entire

conversion is complete within one clock cycle.

Folding and Interpolating ADCs These are closely related to flash

ADCs but using a multistep implementation. The conversion is often

finished within one clock cycle.

Successive approximation and algorithmic ADCs These architectures

typically generate one bit per clock cycle, the benefits are the low area

needed for the implementation.

Pipeline ADCs Several algorithmic stages are pipelined to form the

pipeline ADC architecture. The latency is the same as for the

algorithmic architecture but the throughput is increased at the cost of

additional area.


34/75

16 HighSpeedADCArchitectures

An overview of the performance regions for the different architectures is

shown in Figure 3.1

3.1 FlashADCs

The flash ADC architecture offers the highest potential sample rate of all the

different architectures with the principle being shown in Figure 3.2. The correct

quantization level is decided through the parallel comparison of the input

signal to all 2n1 reference levels. The reference levels are typically generated

through a resistor ladder where 2nequally sized resistor are used to generate

the reference voltages. Each comparator will then decide whether the inputsignal is larger than this reference level, generating a 1 on the output if this is

case and a 0 otherwise. The output from the comparator array will then be

thermometer coded, named from the analogy with the mercury level in a

classical thermometer. In the thermometer code, the transition from 1s to 0s

is indicating the best approximation of the input signal. A decoder is then used

in order to convert the thermometer code to an nbit digital output word.

The flash ADC is most suitable for low resolutions as the hardware needed

doubles for a resolution increase of 1 bit, whereas the power dissipation

Sam

pleRate[samples/s]

2 4 6 8 10 12 14 16Resoluon [bits]

Flash

Pipeline

Folding

SAR

10 G

1 G

100 M

10 M

1 M

100 K10 K

Figure3.1PerformanceregionsofdifferenthighspeedADCarchitectures.


35/75

3.1FlashADCs 17

increases by more than a factor of two, something which is further explored in

Chapter 5.

The flash architecture often results in a high input capacitance, in

comparison with other architectures, due to the high parallelism.

3.1.1

InherentSampleandHold

Because the correct quantization level is decided within one clock cycle there

is no requirement to precede the comparator array with a sampleandholdcircuit as sampling is inherently performed by the comparators.

The absence of a sampleandhold increases the circuit requirements and

introduces several error sources. For example, timing skew between the

comparators would result in signal dependant distortion as the comparators

would sample different time instances of the input signal. This can be solved by

careful layout and delay matching of the signal and clock paths.

The finite rise time of the clock signal to the comparators gives rise to an

inputslew dependant sampling instant [3]. This effect can be reduced by

Decoder

Vin

Vref+

Vref-

Digital output

n-bits

Figure3.2

Flash

ADC

architecture.


36/75


increasing the rise time of the clock signal, resulting in a power dissipation

increase in the clock driver.

All these error sources results in signal (and clock) frequency dependant

harmonic distortion, reducing the signal to noise and distortion ratio. The

power saved by not including an explicit sampleandhold must then be

weighed against the respective costs mentioned above.

3.1.2

FlashDecoders

The choice of decoder topology has an effect on the ADC latency and

robustness to comparator offset and noise. The most straightforward

implementation of a decoder consists of first detecting the 1to0 transition

in the thermometer code, this transition point is then used to address a line in

a ROM which contains the corresponding binary coded output word. The

problem with this solution is that imperfections in the thermometer code, so

called bubbleerrors, would result in several lines in the ROM being addressed

at the same time thereby introducing significant errors, especially for input

signals in proximity to the major code transition. One way to correct for the

above error is to use bubblesuppressing logic which cancels the effect of

bubbles when appearing near the 1to0 transition. However, the

appearance of bubbles further away from the correct transition point requiresmore complex circuits to be corrected [4]. In order to reduce the effect of these

bubble errors the contents of the ROM can be grey coded. In this way, when

two nearby ROM lines are simultaneously addressed the error would then be

minimal.

Another decoder topology which is able to optimally correct for bubble

errors is the Wallace tree decoder [5]. By summing all the comparator output

values the bubbles are suppressed and the binary output is generated at the

cost of extra hardware.

For all the decoder topologies the digital hardware implementation can be

pipelined in order to increase the digital throughput at the cost of extra latency

and power dissipation.

3.1.3

FlashADCPerformance

Flash ADCs mainly target the high sampling rate applications that could be

hard or impossible to reach with other architectures. Table 31 summarizes the

performance of flash ADCs showing the high sampling rate achieved in both

CMOS and BiCMOS processes. Based upon published results, the resolution of

flash ADCs are typically limited to 5 bits but also higher resolutions have been


37/75

3.2InterpolatingandFoldingADCs 19

achieved for full flash architectures as is seen in the same table. This table also

shows the results achieved for the flash ADCs of Paper III and Paper IV

3.2 InterpolatingandFoldingADCs

Interpolation and folding are two techniques which are often used togetherto increase the linearity and reduce the hardware of flash ADCs. The goal is to

design fast converters with higher resolution than full flash ADCs, without the

expensive powerresolution tradeoff that comes with the flash architecture.

Interpolation is used to reduce the number of required comparator pre

amplifiers. This is done by interpolating the output of the preamplifiers in

order to generate additional zerocrossing points which can be detected by the

comparators as shown in Figure 3.3. This is valid as long as the both the

Table31 PerformancesummaryofflashADCs.

Author

Year

Effective

Number

of Bits

(ENOB)

Sampling

Frequency

(fs)

Effective

Resolution

Bandwidth

(ERBW)

Process

Power

Dissipation

(P)

[6]

20093.7 35 GS/s 8 GHz

0.18 m

SiGe BiCMOS4.5 W

[8]

20087.0 1.25 GS/s 1.3 GHz

90 nm

CMOS207 mW

[9]

20046.0 4 GS/s 1 GHz

0.13 m

CMOS990 mW

[10]

20085.3 5 GS/s 2.5 GHz

65 nm

CMOS320 mW

[11]

20063.7 1.25 GS/s 3.3 GHz

90 nm

CMOS2.5 mW

PaperIII 4.0 2.5GS/s 300MHz90nm

CMOS30mW

PaperIV 3.69 1.5GS/s 600MHz90nm

CMOS23mW


38/75


adjacent preamplifiers are still operating in their linear region [2]. Depending

on the output impedance of the preamplifiers, there is also a certain amount

of averaging between all the preamplifiers. This has the benefits ofsuppressing the preamplifier offsets while it also generates significant

distortion near the edges of the input region reducing the useful input range to

about 70% [1][2]. In order to compensate for this, additional preamplifiers

needs to be added to restore the input range. Also different values for the

interpolation resistances can be used, but this makes the ADC more susceptible

Vin

PreAmp

PreAmp

PreAmp

PreAmp

Vref,n+2

Vref,n+1

Vref,n

Vref,n-1Vout,n-1

Vout,n

Vout,n+1

Vout,n+2

Vint,n+1

Vint,n

Vint,n-1

Vout,n

Vout,n+1

Vint,n

Vout

Vout

Figure3.3TheprincipleofinterpolationinADCs.

Folding

Circuit

Vin

Coarse

ADC

Fine

ADC

m bits

n bits

n+mb

its

Vout

Vin

Figure3.4ThefoldingADCarchitectureandfunctionality.


39/75

3.3SuccessiveApproximationandAlgorithmicADCs 21

to process variations because matching is best for resistors of equal physical

dimensions.

Folding is another technique to reduce the hardware needed to achieve a

certain resolution at the cost of increased conversion time. The concept is

shown in Figure 3.4, in order to achieve a resolution of n+mbits the work is

divided into two parts. A course quantizer decides the most significant nbits. In

parallel with this, a folding circuit folds the input range according to the Figure

3.4, shown for n = 2. The fine quantizer, which has fixed reference levels,

decide the least significant m bits. In Figure 3.4 the ideal folding function is

indicated by the dashed line, the real implementations of the folding circuits

will result in smoothing of the folding signal near the edges indicated by thesolid line. This smoothing will decrease the linearity and limits the achievable

resolution.

The folding and interpolating ADC finish the conversion within one clock

cycle, therefore there is, as was the case for flash ADCs, no need to include a

frontend sampleandhold. Another potential bandwidth limitation, besides

those seen in full flash ADCs, is that the signal delay through the folding circuit

must be handled by the ADC in order to prevent the coarse and fine ADCs to

process different sets of data.

3.2.1

FoldingADCPerformance

Table 32 summarizes the performance of different folding and interpolating

ADCs for both CMOS and alternative processes. This again shows a wide spread

in the performance with both highspeed and highresolution ADCs using this

architecture. The table also highlights the performance differences between

CMOS, GaAs and the high performance InP technology which has been used

lately. Most notable is the difference in conversion rate and power dissipation.

Compared to the full flash architectures at the same conversion rate, the

folding architecture is more efficient but cannot reach the highest conversionrates of the flash ADCs.

3.3 SuccessiveApproximationandAlgorithmicADCs

Where the flash ADC corresponds to the maximally parallel implementation

the successive approximation register (SAR) is the sequential equivalent. The

SAR functionality can best be described as the implementation of a binary

search algorithm as shown in Figure 3.5. First, the input signal is sampled at a


40/75


frequency of fs, the digital outputs are then sequentially determined starting

with the MSB by first comparing the input signal to the reference level at VFS/2.

Depending on the comparator decision, a new reference level is generated and

successively the input level is approximated by the SAR ADC. The internal logic

Table32Performance

summary

of

Folding

and

Interpolating

ADCs.

Author

Year

Effective

Number

of Bits

(ENOB)

Sampling

Frequency

(fs)

Effective

Resolution

Bandwidth

(ERBW)

Process

Power

Dissipation

(P)

[7]

19945.6 4 GS/s 1.8 GHz

GaAs/AlGaAs

HBT5.7 W

[12]

2008

6.0 5 GS/s 7.5 GHz InP HBT 8.4 W

[13]

20085.7 1 GS/s 200 MHz

0.18 m

CMOS60 mW

[14]

20099.2 1 GS/s 1 GHz

0.18 m

CMOS1.2 W

[15]

20094.7 1.75 GS/s 878 MHz

90 nm

CMOS2.2 mW

[16]

20095.8 2.7 GS/s 1.35 GHz

90 nm

CMOS50 mW

S&

H

Vin

fsSAR

DAC

fclk

n bit Digital Output

Figure3.5

Successive

approximation

architecture.


41/75

3.3SuccessiveApproximationandAlgorithmicADCs 23

and comparator is clocked with a frequency of nfs, which will limit the sample

rate of the SAR in comparison the flash architecture.

Because the difference between input signal and reference successively gets

smaller, circuit noise will limit the achievable resolution. A faulty comparator

decision means that further iterations will not provide additional information

of the input signal.

Where the SAR ADC successively alter the reference level to match the input

signal the algorithmic ADC uses a fixed reference level and resamples a residue

value. The first cycle, an input signal Vinis compared against the reference level

of VFS/2. Depending on the decision of the comparator, x0, the input value of

the next clock cycle will be 2Vinx0VFS. Multiplication by two is oftenimplemented using operational amplifiers employed in switchedcapacitor

feedback configuration where the gain of the opamp and matching of the

capacitors determine the accuracy of the multiplication.

In contrast to the SAR, the average value of the difference between the input

signal and reference remains constant making the algorithmic ADC less

susceptible to comparator noise. However, a faulty decision will overdrive the

input range to the following iterations, again with irreversible effect. The

additional noise generated by the multiplication circuit, as well as the

multiplication accuracy will limit the achievable resolution.

Aside from the reduced hardware, the input capacitance of SAR ADCs are

often low, typically constraint by noise. This makes the SAR ADC a very

attractive candidate for use in the interleaved ADCs described in Chapter 3.5.

3.3.1

RedundancyorReducedRadix

Because of the significant impact of a faulty comparator decision,

redundancy, or reduced radix, can be employed which allows for faulty

comparator decisions when the input signal is close to the reference level.

Redundancy in SAR ADCs can be implemented by increasing the subADC

resolution while still only increasing the reference resolution by one bit per

cycle or by reducing the radix when switching the references. In the algorithmic

ADCs, either the subADC resolution can be increased, maintaining a gain of

two, or the implemented gain can be reduced to allow an overlap of the

possible input regions for the next cycle. Because of this overlap, a faulty

comparator decision will not overdrive the input range to the succeeding stage

which would saturate the following stages. The redundancy can correct for


42/75


comparator noise and offset, but the noise generated by the algorithmic

amplifier and stored on the sampling capacitor will be treated as part of the

input signal and therefore, cannot be corrected using this technique.

The redundancy requires additional hardware to generate the correct binary

output and also requires additional clock cycles to attain the same resolution.

However, the maximum achievable resolution is increased because the impact

of comparator noise and offset is reduced.

3.3.2

PerformanceofSuccessiveApproximationADCs

SAR ADCs are sometimes used for their low power dissipation, often with

lower requirements on the conversion rate. But as they are also used in the

interleaved ADCs some are also designed with lower resolution and higher

conversion rate. The performance of these highspeed SAR ADCs will be

presented in the section of interleaved ADCs. Table 33 summarizes the

performance of CMOS SAR ADCs showing the low power and high resolution

capacity of this architecture.

3.4 PipelineADCs

The pipeline ADC architecture combines the benefits of high throughput and

an input capacitance bound by noise constraints. This is at the cost of extra

hardware, power dissipation and the same high latency associated with the

SAR ADCs. The architecture is shown in Figure 3.6. Each stage samples the input

Table

3

3

Performance

summary

of

SAR

ADCs.

Author

Year

Effective

Number

of Bits

(ENOB)

Sampling

Frequency

(fs)

Effective

Resolution

Bandwidth

(ERBW)

Process

Power

Dissipation

(P)

[17]

20088.6 40 MS/s 32 MHz

90 nm

CMOS820 W

[18]

2009

9.4 100 kS/s 50 kHz0.18 m

CMOS

3.8 W

[19]

200910.2 11 MS/s 5.5 MHz

0.13 m

CMOS3.6 mW


43/75

3.4PipelineADCs 25

signal and generates akadditional bits of information of the input. An output

residue is sent to the succeeding stages with the last stage typically

implemented as a flash ADC.

Each stage, known as a multiplying DAC (MDAC), is based on the same

principle as the algorithmic ADC and is shown in Figure 3.7. The input signal is

sampled and quantized by an abit subADC, this is converted back to analog

and subtracted from the input signal, resulting in the subADC quantization

error. This is amplified to cover the full input range which has the advantagethat all pipeline stages can be designed identically, simplifying the

implementation.

As with SAR ADCs, redundancy can be utilized in order to remove the effect

of comparator offset and noise. A common scheme is to use 1.5 bit stages with

a1

bit

stage

1

a2

bit

stage

2

an

bit

stage

n

a1 +a2 + ... +anbits

S&H

stag

e

ana2a1

Time re-alignment and Digital Correcon

Vin

Figure

3.6

The

architecture

of

a

pipeline

ADC.

abit

ADC

S&H

Vin

abit

DAC

a bit Digital Output

Gain Vresidue

Figure3.7ApipelineMDAC.


44/75


two comparators and a gain of two in the multiplier. With this, the architecture

is immune to comparator noise and offsets within a magnitude of VFS/8.

3.4.1

PipelineADC

Performance

As with the other ADC architectures the spread of ADC performance is large

with both highspeed pipeline ADCs approaching 1 GS/s and high resolution

ADCs with above 12 effective bits as is seen in Table 34. Regarding the high

samplerate pipeline ADCs, most of these are utilized in interleaved ADCs and

their performance is summarized in that part of this chapter.

3.5 InterleavedADCs

In order to achieve very high sampling rates, especially at medium

resolutions, then a single ADC is not sufficient and timeinterleaving of ADCs is

needed to increase the sample rate. For this each subADC samples the input in

a sequential manner. The concept of interleaving is shown in Figure 3.8 where

nparallel ADCs are used to increase the effective sample rate ntimes. In Figure

3.8, an input stage presented in [24] is also shown. The main sampleandhold

samples the input signal at the frequency fs, this is later resampled the by the

subS&H at the frequency of fs/nbut with a clock duty cycle of 1/n. The clock

signal to each subS&H is phase shifted to uniformly sample the input signal.

Table34Performance

summary

of

pipeline

ADCs.

Author

Year

Effective

Number

of Bits

(ENOB)

Sampling

Frequency

(fs)

Effective

Resolution

Bandwidth

(ERBW)

Process

Power

Dissipation

(P)

[20]

20099.0 500 MS/s 233 MHz

90 nm

CMOS55 mW

[21]

1999

7.5 500 MS/s 250 MHz27 GHz fT

BiCMOS

950 mW

[22]

20075.3 800 MS/s 400 MHz

0.18 m

CMOS105 mW

[23]

200912.8 125 MS/s 150 MHz

0.18 m

CMOS385 mW


45/75

3.5InterleavedADCs 27

Using this input technique, the high bandwidth and sample rate requirementsare placed on the input stage alone, allowing the input stage of the subADCs

to be designed with a bandwidth set by the Nyquist rate of that individual ADC.

Any architecture of the subADCs is viable, but common choices are SAR and

pipeline ADCs due to their low input capacitance. This is beneficial because the

aggregate input capacitance has a direct impact on the power dissipation of the

input stage which needs to maintain the high bandwidth requirement.

When interleaving several ADCs the mismatch between the interchannel

gain and offset and also skew from the ideal samplings instants results in nonharmonic spurs. These error sources can be compensated for through various

techniques, for example the blind equalization technique in [25] or, as

considered part of the channel and compensated for using MIMO techniques

as in [26].

3.5.1

PerformanceofInterleavedADCs

The applications for interleaved ADCs are for example in digital oscilloscopes

as in [27] or for multiGb/s transceivers as in for example [28], [30] and [31].

Noteworthy is the performance of the individual pipeline subADCs in [28] and

k

bitsDigitalOutput

ADC

S&H

VinMain

S&H

channel,1

sampling

ADC

S&H

channel,2

ADC

S&H

channel,n

Ou

tputMulplexer

kbits

kbits

kbits

Figure3.8InterleavingofADCswiththeuseofdoublesampling.


46/75


[30] with sampling rates of 1.3 and 1.2 GS/s respectively as seen in Table 3 5.

Also, for the SAR architecture the highest rates exist in interleaved form in [31]and [32] with 150 MS/s per SAR subADC.

3.6 References

[1]. R.J. van de Plassche, CMOS IntegratedAnalogtoDigital and Digitalto

AnalogConverters,2nd

Edition, Kluwer Academic Publishers, 2003.

[2].

B. Razavi, PrinciplesofDataConversionSystemDesign,IEEE Press, 1995.

Table35Performance

summary

interleaved

ADCs.

Author

Year

Effective

Number

of Bits

(ENOB)

Sampling

Frequency

(fs)

/

Channel

Sampling

Frequency

Effective

Resolution

Bandwidth

(ERBW)

Process

Channel

Architecture

/

Interleaving

Factor

Power

Dissipation

(P)

[27]2003

6.5 20 GS/s250 MS/s

2 GHz 0.18 mCMOS

Pipeline80

10 W

[28]

20085.8

10.3 GS/s

1.3 GS/s4 GHz

90 nm

CMOS

Pipeline

81.6 W

[29]

20053.4

6 GS/s

600 MS/s2.2 GHz

0.18 m

CMOS

Pipeline

10780 mW

[30]

20094.8

4.8 GS/s

1.2 GS/s6.1 GHz

0.13 m

CMOS

Pipeline

4300 mW

[24]

20068.8

1 GS/s

125 MS/s400 MHz

0.13 m

CMOS

Pipeline

8250 mW

[31]

20085.3

24 GS/s

150 Mhz4 GHz

90 nm

CMOS

SAR

16x101.2 W

[32]

20095.4

2.5 GS/s

156 MHz1.25 GHz

45 nm

CMOS

SAR

1650 mW


47/75

3.6References 29

[3]. B. Peetz, B.D. Hamilton, J. Kang, An 8bit 250 Megasample per second A/D

Converter, in IEEEJournalofSolidStateCircuits,Volume 21, Issue 6, pp.

997 1002, Dec. 1986.

[4]. C.W. Mangelsdorf, A 400MHz input flash converter with error correction,

in IEEEJournalofSolidStateCircuits,Volume 25, Issue 1, pp. 184 191,

Feb. 1990.

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34 TheCMOSProcessanditsLimitations

it degrades the DC performance the transistors, specifically transistor voltage

gain, defined as gm/gds, and linearity [2]. The reason for this is the reduced

voltage headroom for transistor biasing and also reduced signal swings. The

projected supply voltage for high performance CMOS processes according to

ITRS 2008 [4] is shown in Figure 4.1 and shows that the problem will continue

to get worse over time.

4.1.2

IncreasedTransitFrequency

In contrast the DC parameters of voltage gain and linearity, the AC

performance of the transistor does increase with technology scaling. The

transit frequency, fT, determines the frequency at which the smallsignal

current gain of a transistor has dropped to unity (4.1) and is indicative of the

Figure4.1 ExpectedchangeinsupplyvoltageaccordingtotheITRS.

Figure

4.2

Expected

change

in

transit

frequency

according

to

the

ITRS.


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4.2MatchingandProcessVariations 35

device speeds offered by the process. fT scales inversely proportional to the

transistor gate length and therefore increases with the scaling of the process,

offering higher device speeds and therefore higher bandwidth [2]. The

expected growth in fT for the high performance processes according to ITRS

2008 [4] is shown in Figure 4.2 and shows a steady increase in the predicted

device speeds.

fT = gm

2CG (4.1)

4.2

Matching

and

Process

Variations

Besides the above mentioned challenges in designing analog circuits in

nanoscale CMOS, there is also the issue with process variations in that the

manufactured transistors will deviate from the nominal behavior through both

variations in the manufacturing process as well as the stochastic nature of

some process steps.

Besides the variations introduced during the manufacturing process, there

are also environmental effects causing variations in temperature and voltage

across the chip [14]. These variations could have an effect of the analogcircuitry, changing offset, gain or nonlinearity performance over time.

The variations due to process manufacturing could be of both systematic and

random nature. Systematic variations include for example variations in

interconnect thickness resulting from nonuniform metal density during the

chemicalmechanical polishing (CMP) process [14] as well as transistor

geometry variations because of the limited lithography resolution. This latter is

layout dependant and is exemplified in Figure 4.3. The random effects causing

variations in transistor behavior include random discrete dopant fluctuations,

lineedge roughness and variations in the channellength [10], [11]. Highlightedin Figure 4.4 are the two issues of random dopant fluctuation and line edge

roughness. When going to the 22nm process node and below, these will

become significant contributors to the overall variations [15]. With the small

gate areas possible at these nodes, the number of dopants has been reduced to

the extent that individual atoms, both in quantity and location, have an impact

of the transistor behavior [16]. The roughness of the edges defined by

lithography will also cause random variations in the effective gate length and

width. On a chip both the passive and active devices will be subject to the


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variations caused by the inaccuracies of the photolithographic process [13].

Because the control of geometry precision in the lithography process will

reduce with decreasing feature sizes [12], these effects can be expected to

further increase in future process nodes.

Diffusion Poly

Figure4.3Lithographylimitations leadingtosystematicerrors intransistor

widthsafterfabrication.

Ideal transistor Transistor with rough gate

edges and discrete dopants

Figure4.4Thesourceoftwomajorprocessvariationcontributors,lineedge

roughnessandrandomdiscretedopantvariations.


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4.3OvercomingScalingandProcessVariations 37

4.3 OvercomingScalingandProcessVariations

As seen, the process scaling introduces both benefits and drawbacks for the

design of analogtodigital converters. A solution, as proposed in [2], to

overcome the issue with reduced supply voltage is to operate critical analog

circuits at a higher supply voltage. Without special considerations this would

result in higher stress of the transistors with oxide breakdown, hotcarriers and

NBTI breakdown [5], [6] to follow at an accelerated rate. The use of thickoxide

transistors, which are often an option at modern CMOS processes, can allow

higher supply voltage and effectively means that analog parts can be run with

transistor performance equal to that of older processes, with increasedlinearity and analog gain but reduced speeds.

An alternative solution is to follow the trend shown in publications and panel

discussions as [7], [8] and [9] where the digital processing power in modern

processes are used to correct for the analog circuit shortcomings. For example,

matching is less of a concern when the accuracy can be compensated for

digitally. This also applies to nonlinearity which allows for the use of low

accuracy, nonlinear analog circuits which are corrected by digital circuits,

thereby utilizing the capability of modern processes.

4.4 References

[1]. C. H. Diaz, D. D. Tang, and J. Y.C. Sun, CMOS technology for MS/RF SOC,

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Mar. 2003.

[2]. A.J, Annema, B. Nauta, R. van Langevelde, H. Tuinhout, Analog circuits in

ultradeepsubmicron CMOS, in IEEE Journal of SolidState Circuits,

Volume 40, Issue 1, pp. 132 143, Oct. 2005.

[3]. G.E. Moore, Cramming more components onto integrated circuits, in

Electronics,Volume 38, Issue 8, 1965.

[4]. InternationalTechnologyRoadmapforSemiconductors. [Online]. Available:

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[5].

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[6].

R. Fernandez, J.MartinMartinez, R. Rodriguez, M. Nafria, abd X.H.

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[7]. B. Murmann, A/D converter trends: Power dissipation, scaling and

digitally assisted architectures, in CustomIntegratedCircuitsConference,

pp. 105 112, Sept. 2008.

[8]. A. Matsuzawa, Technology trend of ADCs, in IEEE International

Symposium on VLSI Design,Automation and Test, pp. 176 179, April

2008.

[9].

A. Matsuzawa, A. Abidi, S. Bogdan, J. Craninckx, J. Dawson, T.C. Lee, B.

Murmann, B.S. Song, Digitally assisted analog and RF circuits: Potentials

and issues, in IEEEAsianSolidStateCircuitsConference, pp. 485 485,

Nov. 2008.

[10].

S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De,

Parameter variations and impact on circuits and microarchitecture, in

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[11]. S. Bhunia, S. Mukhopadhyay, and K. Roy, Process variations and process

tolerant design, in VLSIDesign., pp. 699 704, Jan. 2007.

[12]. H. Masuda, S. Ohkawa, A. Kurokawa, and M. Aoki, Challenge: Variability

characterization and modeling for 65to 90nm processes, in IEEECustom

Integr.CircuitsConf., pp. 593 599, Sep. 2005.

[13]. R. Difrenza, P. Llinares, S. Taupin, R. Palla, C. Garnier, G. Ghibaudo,

Comparison between matching parameters and fluctuations at the wafer

level, in Proceedings of the 2002 International Conference on

MicroelectronicTestStructures, pp. 241 246, April 2002.

[14]. S. Nassif, K. Bernstein, D.J. Frank, A. Gattiker, W. Haensch, B.L. Ji, E.

Nowak, D. Pearson, N.J. Rohrer, High Performance CMOS Variability in the

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4.4References 39

[15]. A. Asenov, S. Roy, R.A. Brown, G. Roy, C. Alexander, C. Riddet, C. Millar, B.

Cheng, A. Martinez, N. Seoane, D. Reid, M.F. Bukhori, X. Wang, U. Kovac,

Advanced simulation of statistical variability and reliability in nano CMOS

transistors, in IEEEInternationalElectronDevicesMeeting, 2008.

[16]. S. Toriyama, D. Hagishima, K. Matsuzawa, N. Sano, Device Simulation of

Random Dopant Effects in Ultrasmall MOSFETs Based on Advanced

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41

Chapter5

DesignConsiderationsforHighSpeedADCs

In the design of highspeed ADCs, an understanding of the fundamentallimitations from both the process and the underlying physical phenomena is

necessary in order to design highperformance and efficient converters. The

first part of this chapter provides an introduction to the lower limits of power

dissipation in ADCs as set by the noise constraints and is followed by a

discussion on the d

design of low power nyquist a2d.pdf

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