CHAPTER 1

INTRODUCTION

1.1 Brief Introduction

Microelectronic is one of the most rapidly developing fields in the past few decades.

According to Moore’s law the density of integrated circuits components would

double every eighteen months (Moore, 1965). The demand for real time range image

acquisition has been growing especially in the engineering, sciences and as well as in

the field of medicine (Strand, 1985). Due to this growing demand, extensive research

to develop the latest and more compact range image sensors are carried out by

various organizations and institutions throughout the world. To tackle the

requirement needed for a real time, compact, low cost and vigorous range imaging

system, Time of Flight (TOF) is the most attractive and cheapest solution. However,

much work need to be done as TOF does not offer the best resolution range images

although it is the fastest and cheapest method available.

The pioneer of optical TOF measurement is Galileo Galilei, who imagined light as a

kind of particle that travels through free space with a measureable speed. He tried to

prove this idea by a simple experiment, described in one of his famous books named

“DISCORSI E DIMOSTRAZIONI MATEMATICHE”.

1  

In the dar

about 1km

lantern, co

light. The

‘B’ to unc

way Galil

from toda

the distan

experience

quickly an

was of th

measured.

incredibly

experimen

measuring

a Jupiter m

Figure

rk of night

m away fro

overed by th

e experimen

cover his la

lei hoped to

ay’s point of

nce of 2km.

e. Before ca

nd measured

he same ord

. However,

y quickly th

nt. After a

g the speed

moon, sternl

1.1: Galile

he placed

om each oth

heir hands,

nt started wi

antern as w

o person ‘A

f view, sinc

. So much

arrying out

d their react

der of magn

he conclud

hat it was n

few years

of light by

ly speaking

2

o Galilei’s

two people

her as show

so that initi

ith person ‘

well, as soon

A’ to person

ce we know

more rema

his experim

tion times. H

nitude as th

ded that lig

not possible

s i.e. in 16

using the d

g also a TOF

Experimen

e ‘A’ and ‘B

wn in Figu

ially one co

A’ uncover

n as he saw

n ‘B’ and ba

w that the li

arkable is G

ment, he trai

He found th

he reaction

ght exists in

e to measur

676 it was

departures fr

F experimen

nt (Galilei,

B’ onto two

ure 1.1 abo

ould not see

ring his lant

w the first la

ack to ‘A’,

ight only ne

Galilei’s co

ined the exp

hat the meas

times that

nstantaneou

re its speed

s Roemer

from predict

nt (Brockhau

1638)

o neighbori

ove. Both c

e the other’s

tern and wa

antern’s lig

a hopeless

eeds 6.6µs t

onclusion fr

perimenters

sured speed

he had pre

usly and pro

with the p

who succe

ted eclipse

us, 1989).

ing hills

carried a

s lantern

aiting for

ght. That

attempt

to travel

rom this

to react

d of light

eviously

opagates

proposed

eeded in

times of

 

In 1849, F

surprising

In 1983 th

(Penrose,

possible to

can be don

to the targ

plane i.e. t

Fizeau was

gly precise v

he speed of

2004). Wi

o modify G

ne by meas

get and back

the same di

more succe

value for th

f light has b

th this pre

Galilei’s or F

suring the el

k to the rece

stance from

essful in me

he speed of

een fixed b

cise knowl

Fizeau’s exp

lapsed time

eiver, where

m the target.

easuring the

light consta

by definition

edge of th

periments a

e during wh

e the source

e TOF on e

ant, ‘c’ to b

n to c = 2.9

e velocity

and to meas

hich light tra

and the rec

earth, he ob

be 3.153 ×

9792458 ×

of light, it

sure distanc

avels from a

ceiver is at t

btained a

108 m/s.

108 m/s

t is thus

ces. This

a source

the same

1.2 Time of Flight (TTOF) Imagge Sensor Setup

Times of

measure d

a range im

The exper

Flight (TO

distance of o

mage. Figure

riment consi

OF) range im

objects in a

e 1.2 is the

ists of light

magers are

scene. The

general exp

source, an

the image

e measured

perimental s

object and a

e sensors w

distance is

setup for TO

a sensor.

which has ab

then repres

OF Range I

bility to

ented as

Imaging.

Figgure 1.2: Baasic Princip

3

ple of Time

e of Flight ((TOF) Rannge Imaging

 

In this method the range L is determined by sensing the roundtrip TOF of light and is

given by:

L12 c TD (1.1)

where c is the speed of light and TD is the round trip TOF of light.

1.3 Problem Statement

Although there a fully CMOS TOF image sensor has been proposed, a modification

to the CMOS process is necessary in order to create an n-epitaxial layer for efficient

charge transfer (Kawahito et al., 2007). This enquires extra design and fabrication

cost.

An alternative method that allows efficient charge transfer without modifying the

CMOS process is to use charge transfer amplifiers. The higher the gain of the

amplifier used, the more linear is the charge transfer (Halin & Kawahito, 2004).

Since there are many choices of amplifier topologies in CMOS technology, a clear

method of choosing one amplifier in terms of linearity, power and the number of

transistors is required for designing the optimum TOF pixel range image sensor that

uses the standard CMOS process.

4  

1.4 Aim and Objective

The objective of this thesis is to analyze various types CMOS amplifiers like 2-Stage

OPAMP, Folded Cascode, Telescopic and Cascode Amplifiers in terms of gain,

power dissipation and number of transistors used in the design. By the comparison of

different designed CMOS amplifiers, a best amplifier is picked to design the active

pixel TOF sensor.

1.5 Scope of Work

Scope of this thesis is to simulate and calculate the Charge Transfer Efficiency

(CTE) using various amplifiers and the design of the best TOF Active Pixel Sensor

(APS) based on our analysis.

1.6 Thesis Layout

This thesis is divided into five chapters. Chapter 1, summarizes the CTE analysis and

TOF Range Imaging. Discussion on the problem statement, aim & objective, and the

scope of work is also included in this chapter.

In Chapter 2, CCD and CMOS image sensors are discussed followed by discussion

on different types of CMOS amplifiers and its design methodology. A discussion on

other 3D imaging methods is also presented. The basic working principles of these

methods will be discussed, as well as their advantages and disadvantages. Since

CMOS imaging sensing technology is proposed for this work, materials regarding

5  

CMOS image sensors are reviewed. At the end of the Chapter there is an explanation

on Active Pixel Sensor (APS) and CTE.

In Chapter 3 the Methodology and Research Design to achieve the objectives of this

work is explained.

In Chapter 4 detailed results regarding various CMOS amplifier design, CTE

analysis and the TOF pixel simulation is presented. Related results are verified and

compared with previous works.

Finally, in Chapter 5 a conclusion for this work is presented where a Cascode

Amplifier is found to be the most suitable amplifier when used for the Active Pixel

TOF Sensor due to its low power consumption, circuit simplicity and high gain

leading toward high CTE. Suggestions for future development of the CMOS TOF

range image sensor us also presented.

6  

CHAPTER 2

LITERATURE REVIEW

2.1 Introduction

Image sensors are mainly divided into two types i.e. Complementary Metal Oxide

Semiconductor image sensors (CMOS) and Charge Couple Devices (CCD) image

sensors. Nowadays CMOS Active Pixel Sensors (APS) are extensively used in

webcams, robotics, x-rays machines, computers, mobile phones cameras,

automobiles, cinematography, spectrography and in many scientific applications

because they are cost efficient and consume less power when compared to CCD

image sensors. This work explores state of the art research on TOF active pixels by

reviewing the solid state TOF imaging methodologies, preliminaries on CCD and

CMOS image sensors, types of CMOS amplifiers focusing on their design

methodologies and the Charge Transfer Analysis idea for a fully CMOS TOF pixel.

2.2 CMOS Image Sensors

An image sensor is a device which captures a scene by changing the light information in the

scene to digital signals. CMOS image sensors allow the ability to monolithically integrate a

considerable amount of VLSI electronics on-chip. Moreover, it also reduces the component

and packaging cost (Bigas et al., 2006).

7  

CMOS image sensor generally consists of an imaging area. This imaging area contains an

array of pixels with readout, horizontal access and vertical access circuitry shown in Figure

2.1 (c).

(a) (b)

(c)

Figure 2.1: CMOS (a) Passive Pixel Sensor Schematic (PPS) (b) Active Pixel Sensor Schematic (APS) (c) Imager Block Diagram

A

PD

Output

ROW SELECT

PD

Output

ROW SELECT

VDD VDD

RESET RESET

Vert

ical

Acc

ess C

ircu

itry

Horizental Access Circuitry

Pixel Pixel

Pixel

Pixel

PixelPixel

Pixel

Pixel

Pixel

Pixel

Pixel PixelPixel

Pixel

Pixel

Pixel

Pixel

Pixel

Pixel Pixel

PixelPixel

Pixel

Pixel Pixel

Readout Circuitry

Output

Row control line

Col

oum

n co

ntro

l lin

e

8  

CMOS image sensors are generally divided into two main types, these are Passive Pixel

Sensors (PPS) and Active Pixel Sensors (APS) as shown in Figure 2.1 (a) and (b). Photo

charge conversion is done in the Photodiode (PD) structure during the pixel’s accumulation

time which is typically 33ms for standard video rate (Bigas et al., 2006). Initially, the

RESET signal is activated to connect PD and VDD. This will pull the voltage across PD to an

initial value, VRESET. When the RESET signal is deactivated, the pixel’s accumulation time

starts. During this time, the voltage across PD will drop in proportions to the collected

photons from the scene. The final voltage value across PD represents the raw measured

signal. This signal is readout onto the output line by activating signal ROW SELECT

(Bigas et al., 2006; Otha, 2007).

2.2.1 Three Transistor (3T) Active Pixel Sensor

The APS is named because an active element is used in the pixel. This active element

amplifies the signal in each pixel. The simplest APS design is the 3T APS. The schematic

of 3T APS with timing pulses are shown in Figure 2.2 (a) and (b). PD is the photodiode

and transistor M1, M2 and M3 are the reset, amplifying and row select transistors

respectively.

The operation of the pixel is as follows. When the reset signal becomes high, transistor

M1 turns on initializing the voltages at node ‘X’ i.e. VX=VDD-VTH and integration starts

when the M1 turns off. When the light falls on the PD, the photo-generated carriers are

accumulated in PD junction capacitance CPD. These accumulated charges changes the

potential in PD i.e. VPD decreases because of the input light intensity. Then the signal is

readout to the common vertical output line by turning on transistor M3. When readout

9  

process is finished, M3 is turned off and M1 is turned on to start the next integration

process (Otha, 2007; Suat, 2005).

M1

M2

M3

VDD

Col output line

Reset

PD

X

Sel

Reset

Sel

V1 RST

VPD

V2 RST

V1 SIG

V2 SIG

(a)

(b)

Figure 2.2: Conventional 3T APS (a) Schematic (b) Pixel Timing Diagram

2.2.2 Four Transistor (4T) Active Pixel Sensor

The schematic representation and timing control signal of the 4T-APS is shown in Figure

2.3 (a) and (b). The idea is to add another transfer transistor M4 which is used to transfer

photo-generated carriers to the drain of M4 which is a modelled as a Floating Diffusion

10  

(FD) capacitor. This is required to allow reset noise cancellations because the

accumulation frame and reset signal are in the same cycle (Ohta, 2007).

Tx

M4

M1

M2

M3

VDD

Col output line

Reset

PD

X

Sel

FD

Y

Reset

Sel

TX

VX

Col o/p

(a)

(b)

Figure 2.3: Conventional 4-Transistor APS (a) Schematic (b) Pixel Timing Diagram

This 4T APS operates as follows: Initially the signal charges are accumulated in the PD,

after that FD is reset by turning on the M1 transistor. Due to this reset voltage Vrst is read

out and stored in a Correlated Double Sampling (CDS) circuitry by turning on M3 i.e.

11  

reset transistor. After that signal charge accumulated in the PD is transferred to the FD

through transfer gate M4 following the readout signal by turning on the select transistor

M3 (Guo, 2009; Ohta, 2008).

2.3 Advantages of CMOS Image Sensor

The main advantages of CMOS imagers are:

1. CMOS image sensors power consumption is lower than that of CCDs because CMOS

imagers can operate at low voltages. Single supply voltage is sufficient for CMOS

Imagers while CCDs requires 3 to 4 different supply voltages (Bigas et al., 2006).

2. CMOS image sensors have lower cost as compared to CCD’s technology.

3. Another big advantage of CMOS imager is its on-chip functionality and compatibility

with standard CMOS technology (Bigas et al., 2006; Ohta., 2007).

2.4 Charge Coupled Devices (CCD) Image Sensors

A CCD is a device which is normally used for the transferring of electrical charge

from one capacitor to the adjacent capacitor. Two scientists named W. Boyle and G.

Smith developed CCD’s in Bell Laboratories (Boyle & Smith., 1970). Figure 2.4

illustrates how a three phase clock is used to move a charge packet through a CCD.

CCDs are constructed using closely MOS capacitors arranged in single row. Charge

packets are moved under one gate to another by clocking the gates potential using

various clocking schemes i.e. the one and a half, two, three and four phase clocks.

12  

SiO2

p-type substratePoli-silicon Gates

Potential

T1

T2

T3

T4

T5

1 2 3 4 5 6

1

2

φ

φφ

3

T1 T2 T3 T4 T5

Time

1

2

φ

φ

φ

3

(a)

(b)

Figure 2.4: Three Phase CCD (a) Transfer Mechanism (b) Clocking Scheme (Arora, 1976)

The potential outline corresponding to each gate is shown in Figure 2.4 (a). Initially,

in T1 there are two charge packets under gate 1 and 4, respectively. The packets

under both gates cannot move due to the potential barrier surrounding them. In T2

13  

the potent

to distribu

under gate

moved un

controlled

clock (Spr

tial barrier u

ute equally u

e 1 and 3 is

nder gate 2 a

d by reversin

ring et al., 2

under gate 2

under gates

s lowered, th

and 4, respe

ng the clock

2010; Arora

2 and 5 are

s 1, 2 and 4

he charge p

ectively. Th

k pulses and

a, 1976; Boy

lowered, wh

, 5 respectiv

packets unde

he direction

d the charge

yle & Smith

hich allows

vely. In T3,

er gate 1 an

n of charge

e packets ca

h., 1970).

s the charge

when the p

nd 3 are com

packet flow

an be delaye

packets

potential

mpletely

w can be

ed using

General a

sensor, th

transferred

architecture

he charge p

d simultane

of the CC

packets orig

ously along

CD imager

ginate from

g all the para

is shown i

m photo ind

allel CCD c

in Figure 2

duced charg

columns (Sp

2.5. In CCD

ge which w

pring et al.,

D image

would be

2010).

2.5 Comp

CMOS im

technology

Figure 2.5

parison betw

mages are now

y. Compared

5: CCD Im

ween CCD

w comparab

d to CCD i

14

mager Block

and CMO

ble to CCD

images, CM

k Diagram (Palakodetyy, 2007)

OS Image Seensors

images as m

MOS has so

more research

ome very cl

h is done on

lear advant

n CMOS

ages for

4  

instance on-chip integration of functionality, lower power consumption and reduced

cost. Despite of these advantages, CMOS image sensors have been plagued by worse

image quality when used in digital still cameras. This is because of the fact that

CMOS image sensors have generally higher temporal as well as Fixed Pattern Noise

(FPN), higher dark current (DC), lower spectral response and smaller full-wave

charge capacity. Therefore they cannot provide the same wide Dynamic Range (DR)

and superior Signal to Noise Ratio (SNR) that CCD image sensor does and their

application has until been limited to low end imaging applications.

Now, CMOS imagers are challenging the CCDs. In last few years, a great deal of

research and effort has been made because more functionality is added to the CMOS

sensors. Improvement in the CMOS architecture and processes has overcome early

limitations, especially with respect to sensitivity and noise (Blanc, 2001). CCD’s are

fabricated in a dedicated process while CMOS image sensors on the other hand are

fabricated in a standard process, which lessens the production cost. A detailed

comparison between CCD versus CMOS is shown in Table 2.1 (Calizo, 2005; Bigas et

al., 2006).

15  

Table: 2.1 CCD versus CMOS Image Sensor Technology (Calizo, 2005)

CCD CMOS

Power Consumption High Low

Cost High Low

Size Large Small

Noise Low High

Integration with CMOS No Yes

Scalability Yes Better than CCD

Fabrication Specialized Process Common Process

Voltage levels needed Many Few

2.6 Range Imaging

3D range imaging can be obtained using three different methods which are

triangulation, interferometery and TOF. The measured range versus range resolution

of the three methods is compared in Figure 2.6. It shows that, Interferometery offers

the resolution up to 10µm that can measure up to 10cm. Active Triangulation can be

used with resolution more 10mm and having the application range of 100m. Finally,

TOF technique allows resolution 10mm to 1m with application range from 10m up

to 10km. These range finding techniques explained here have their specific merits

and demerits thus it is application specific (Upendranath, 2005). For example, to

acquire range images of small objects, a microchip for instance, one may select

interferometery.

16  

10 10 10 10

10

10

10

10

INTERFEROMER Y

TRIANGULA TION

TIME OF FLIGHT

Application Range (m)

Res

olut

ion

(m)

-6 -3 0 3

-6

-9

-3

0

Figure 2.6: Measured Range versus Range Resolution for three Different Range

Imaging Techniques

Solid state range imagers are capable to measure size, shapes and locations of the

objects. Conventionally range imaging is divided into two different methods i.e.

active and passive 3D range imaging (Sansoni et al., 2009). In the active 3D image

sensors a suitable active illumination is used while in passive image sensors, in each

pixel only ambient light is used to obtain range images (Blanc, 2001).

The advantages of 3D range imaging cameras are as follows:

• 3D range imaging cameras can deliver amplitude, intensity map and range.

• These are safer and have particularly small data acquisition time with high

frame rate for instant range feedback.

• 3D range imaging cameras have wide field of view and can be used day as

well as night time.

17  

• These are handheld like small sized and have cheaper prices (Teizer, 2008).

2.6.1 Methods of Range Imaging

The following subsections will explain in detail about interferometery, triangulation

and TOF such that the suitable range imaging method may be selected according to

system requirements.

2.6.1.1 Interferometery

Interferometery is described by the addition of two different signals having certain

frequency, amplitude and phase resulting in another signal of the same frequency ν,

but with different amplitude and phase. Figure 2.7 shows the system setup of the

Michelson Interferometer.

Figure 2.7: Working Principle of Michelson Interferometer (Lange, 2000)

18  

A solid bar shown in the middle of the figure is a ray splitter which divides the laser

ray into two. One ray goes to a mirror of displacement a1 and the other ray is targeted

on the object of variable distance a2. These rays are reflected back towards the ray

splitter. The reference and object wave of Z1 and Z2 respectively are defined as:

eZ I (2.1)

eZ I (2.2)

where I1 and I2 are the optical intensities, By solving Equations (2.1   and  2.2 one

can obtain the interference equation, i.e.

cos2 2 2

    2 (2.3)

In Equation (2.3) we consider 2a1 and 2a2 respectively because the light signal travels

twice (Creath, 1988; Lange, 2000).

2.6.1.2 Triangulation

In literature triangulation is divided into two categories which are passive and active

triangulation. Figure 2.8 (a) and (b) shows the setup for the passive and active

triangulation.

19  

Sensor1 Sensor2

Object

Baseline

d

(a, b, c)

(a1,b1) (a2,b2)f

Sensor

Object

x

(a, b, c)

x'

f

α

α

Light Source

d/2

z

(a) (b)

Figure 2.8: Triangulation Setup (a) Passive Triangulation (b) Active Triangulation

Figure 2.8 (a) shows the system setup for passive triangulation. It is shown in figure

that two sensors, sensor 1 and sensor 2 are placed in a line on a common base line,

which is said to be an imaginary line connecting the two lens centre. To measure the

object distance, wide field of view is compulsory for cameras to locate related points

and object otherwise it is impossible to measured far objects and this is said to stereo

correspondence problem and can be resolved by the active triangulation setup which

is shown in Figure 2.8 (b).

In this setup, a light is pointed onto an objects and it reflects back to 2D image

sensor making an angle α. Two similar triangles are formed enabling absolute

distance measurement. To create a range image of the object, the laser dot is scanned

throughout the surface of the object by mean of a moving mirror. This method takes

time and because of circuitry complexity, it is not suitable for video rate 3D imaging

(Ohta, 2007; Lange, 2000).

20  

2.6.1.3 Timme of Flighht (TOF)

The Time

acquisition

fast, cost e

of the TO

principle o

e of Flight

n of range i

effective an

OF is also in

of a TOF ra

(TOF) is

images. The

nd has a sim

ncreasing s

anging syste

one of the

e main adva

mpler experi

teadily (La

em is shown

e potential

antage of T

imental setu

ange et al.,

n in Figure 2

methods f

TOF range im

up. The mea

2000; Ohta

2.9.

for the fast

maging is t

asurement a

a, 2007). Th

t optical

that, it is

accuracy

he basic

In this me

the object

sensing th

F

ethod time t

t and back

he roundtrip

Figure 2.9:

that the ligh

to the sen

TOF of lig

21

Time-of-F

ht requires t

nsor is calle

ght and is giv

12

1 

light (TOF

to travel fro

ed TOF. Th

ven by:

F) Method

om the meas

he range, L

surement sy

L is determ

ystem to

mined by

(2.4)

 

where c = 3 × 108 m/s is the speed of light and TD is the round trip TOF of light. Note

that TD is divided by 2 due to the fact that the light signal must travel twice the

distance of L.

Table 2.2 shows the relationship between the maximum measured distance for a

given delay time. According to Table 2.2, as delay time increases, the measured

distance decreases. For different time delays, the measure distance is calculated in the

Table 2.2.

Table 2.2: Relationship between Delay Time Measurement Resolution and Distance Resolution Based on the TOF Method

Delay Time Measure Distance

10µs 1.5km

1µs 150m

100ns 15m

10ns 1.5m

1ns 15cm

100ps 1.5cm

10ps 1.5mm

1ps 0.15mm

TOF range imaging itself could be subdivided into several categories which are pulse

modulation, sine wave modulation, and pseudo noise coded TOF. What

differentiates between these TOF methods are the active illumination light source

22  

used and sensing parameter used to extract time delay information (Lange et al.,

2000).

2.7 Types of CMOS TOF Sensors 2.7.1 Active CMOS TOF Pixel

Figure 2.10 shows the schematic of the TOF active pixel Sensor. In this circuit, the

photodiode labelled PD acts as the light sensing element. The photo current, Iph

induced by the photons collected on the PD serves as input to a charge integrating

amplifier configuration. The amplifiers high input impedance allows the photo

generated charges to transfer quickly to the feed back capacitors C1 and C2 on

closing the switches φ1 and φ2 respectively (Halin & Kawahito, 2004).

PD

C1

C2

Iph

1

2

R

AmpVout

φ

φ

φ

Figure 2.10: Schematic of the TOF Pixel Sensor (Halin & Kawahito, 2004)

23  

2.7.2 Gated CMOS TOF Pixel

In Gate-on-Field-Oxide (GOFO) TOF pixel all of the polysilicon gates are used to

control the direction flow of electrons and are fabricated on a layer of field oxide

(Kawahito et al., 2007). It operates by separating photo charge packets into two. In

each packet, amount of charge is determined by the TOF of the received light pulse.

The cross section of x and y plane of GOFO TOF pixel is shown in Figure 2.11 (a)

and (b).

p-type substrate

p-epitaxial layer

n-burried layerSiO2

p-wellp-welln+ n+n+n+

sel

PG Tx1Tx2VR VR

V1V21 1

p-type substrate

p-epitaxial layer

n-burried layerSiO2

p-wellp-welln+n+

PG CDCD

(a)

(b)

Figure 2.11: GOFO TOF Pixel Cross Section (a) x-Plane Cross Section (b) y-Plane Cross Section

24  

Figure 2.11 (a) shows the x-plane GOFO TOF pixel cross section. Here the signal

charge is readout when the select ‘sel’ goes high. The Reset Signal (VR) is used to

reset the pixel. In this structure the highly doped substrate neutralizes photo

generated electrons while electrons generated in the p-epitaxial layer are pushed to

the surface due to a potential gradient directed to the surface. The potential profile

that pushes electrons to the surface is generated from the doping concentration in the

p-epitaxial layer. After that, these moderately generated electrons move into the n-

buried layer which moves the electrons horizontally due to potential gradients

sloping towards V1 and V2 when gates TX1 and TX2 open.

Figure 2.11 (b) shows the y-plane GOFO TOF pixel cross section. It shows the

Photo-Gate (PG) is shown between two Charge Draining (CD) gates. These CD

gates are used to drain the background induced electrons (Kawahito et al., 2007).

2.8 Various CMOS Amplifier

In last few decades, the feature size of the MOS transistor has been extensively

reduced. Reductions in gate oxide thickness ‘tox’, channel width ‘W’ and length ‘L’

have been responsible for a revolutionary reduction in overall circuit size and power

consumption (Razavi, 2002). Now, CMOS amplifiers are very common in various

analog systems. There are various types of CMOS amplifiers such as the Two-Stage

OPAMP, Folded Cascode, Telescopic and Cascode. While designing a CMOS

amplifier, there are different characteristics like output swing, gain bandwidth,

power dissipation etc all have to be taken into consideration (Sedra & Smith, 2004).

25  

2.8.1 Two-Stage CMOS Operational Amplifier

CMOS Two-Stage OPAMP is widely used because of its very simple architecture.

Figure 2.12 shows the schematic diagram of a Two-Stage OPAMP. This amplifier

consists of two stages. The first stage is formed by the differential pair M1-M2 with

its current mirror loads M3 and M4. The differential pair is biased by the current

source NMOS transistor M5 and it must have doubled over drive voltage ‘VOD‘

when compared to the input devices. In second stage i.e. common source output

amplifier pair is cascaded with the first stage to increase the gain. The NMOS

transistors M7 or M8 must have large value of output resistance. Equalizing of

output resistance of the circuit will optimize the overall effective resistance, thus the

gain of the OPAMP (Razavi, 2002; Sedra & Smith, 2004).

8

CL

IB

Cc

Figure 2.12: Schematic Design of CMOS Two-Stage OPAMP

26  

2.8.2 Folded Cascode Amplifier

The word “Folding” originates from folding the PMOS cascoded active loads of a

differential pairs and then it is replaced by to NMOS (Baker, 2007). The folding idea

is shown in Figure 2.13 (a) and (b).

I1

Vin

Vb

M2

M1

Vout

VDD

Vin I1

I2

Vout

VDD

Vb

M1

M2

I1

Vin

Vb

M1

M2

Vout

VDD

Vin

I1

I2

Vout

VDD

VbM1 M2

(a)

(b)

Figure 2.13: Folded Cascode Circuits a) NMOS (b) PMOS (Razavi, 2002)

27  

In NMOS and PMOS Cascode amplifiers, the input device is replaced by the

opposite device and converting the input voltage to a current. In these circuits the

current generated by M1 flows through M2 and through the load, producing an

output voltage. The main advantage of the folded structures is the choice of the

voltage levels (Razavi, 2002).

The schematic representation of Folded Cascode Amplifier is given in Figure 2.14.

The advantages of the Folded Cascode amplifier are its large gain and high stability.

The main drawback of Folded Cascode is that it has extra cascaded circuitry and thus

consumes more power (Waltari, 2002; Razavi, 2002).

M1M1 M2M2

VDDDD

GNDGND

M9M9

M10M10

Vin-Vin-Vin+Vin+

Vb1Vb1

Vb2Vb2VoutVout

M3M3

M4M4 M5M5

M6 M6 M7M7

M8 M8

Vb3Vb3

Vb4Vb4

GNDGND

M11M11

I1

I2

I3

I4

I6

I5

I7

CL

Figure 2.14: Schematic Design of CMOS Folded Cascode Amplifier

28  

2.8.3 Telescopic Amplifier

A schematic diagram of the Telescopic amplifier design is shown in Figure 2.15. The

advantages of the Telescopic amplifier are its higher gain, higher frequency

capability and lower power consumption compared to other architectures. The

drawback of this architecture is its limited output swing. (Gulati et al., 1998).

VDDVDD

Vb2Vb2

Vin2Vin2

VoutVout

M1M1M2M2

M5 M5

GNDGND

M3M3

Vb1Vb1

M4 M4

Vin1Vin1

M6 M6

M7 M7 M8 M8

M9 M9 M10M10

M11M11 M12 M12

Vb3Vb3M13M13

CL

I1313

Figure 2.15: Schematic Design of CMOS Telescopic Amplifier

29  

2.8.4 Cascode Amplifier

Cascode amplifiers are used in the low frequency range as its gain is maximized here.

The triplic single ended Cascode amplifier design is shown is in Figure 2.16. The

main advantage of this type of amplifier is its very high gain and low power

consumption. The drawback is its limited output swing (Gulati et al., 1998).

VDDDD

M6M6

Vb5Vb5

VinVin

Vb1Vb1

Vb2Vb2

VoutVout

M1M1

M2M2

M5 M5

GNDGND

Vb3Vb3

M3M3Vb4Vb4

M4 M4

IDDDD

Figure 2.16: Schematic Design of CMOS Cascode Amplifier

30  

2.9 Charge Transfer Efficiency (CTE)

CTE is defined as the “ratio of output charge to the input charge”. It gives a measure

on how efficient an input charge is translated to the output. To calculate the CTE of

the proposed TOF sensor, Figure 2.17 is used (Halin & Kawahito, 2004).

AmpVoutVi

CFB

CPD Ci

FBφ

Figure 2.17: Charge Transfer Efficiency Equivalent Circuit The total input capacitance is the parallel combination of photodiode capacitance

CPD and gate input capacitance, Ci. The charges accumulated on CPD and CFB are

given as Equations (2.5) and (2.6), respectively:

QPD CPD C V CFB V V

QFB CFB V V

(2.5)

(2.6)

By solving these equations, CTE can be calculated as follows:

31  

 QFBQPD

1 ACFBCPD C 1 A CFB

η (2.7)

From Equation (2.7), if ACFB is much larger than CPD and Ci, then η depends mainly

on the amplifier's gain A, and almost 100% efficiency is achievable.

One of the most important finding to emerge from this study is that a very high speed

and highly efficient charge transfer circuit for TOF range imaging is also available in

standard CMOS technology by the use of high gain negative feedback inverting

amplifier circuit (Halin & Kawahito, 2004).

2.10 Charge Injection Cancellation

The method chosen here for charge injection cancellation is shown in Figure 2.18

(Razavi, 2002). In this configuration both the transistors used are NMOS.

CsVoutVin

M2

M1

Clk

Clk

Figure 2.18: Addition of Dummy Device to Reduce Charge Injection & Clock

Feed Through

32  

In this technique injected charge in transistor M1 due to clock feed through can be

removed by the transistor M2. Cs is just a model of the source capacitance of the

main switch's (transistor M1) source terminal. A dummy switch M2 is added by

combining the drain and source together to form a MOS capacitor. This dummy

switch is driven by the Clk, such that after M1 turns off and M2 turns on. The

channel charge is deposited earlier on the capacitor Cs and is absorbed latter to form

a channel. Since the charge injected from M1 into Cs is:

2 (2.8)

The size of transistor M2 should be ½ of M1 for it to effectively drain ΔQ1.

As, ΔQ2 = W2L2Cox ( - Vin - Vth2), if W2 is chosen half of the W1 and L1 = L2,

then ΔQ1 = ΔQ2.

Another approach used to reduce the effect of charge injection is by use of the

complementary switches which is shown in Figure 2.19 (Razavi, 2002). In this

configuration charge injection cancellation is obviously achieved by using

complementary clock signals.

33  

Vin

M1

M2 Cs

Clk

Vout

Clk

Figure 2.19: Use of Complementary Switches to Reduce Charge Injection

For perfect cancellation, both transistors must have the same size as explained by

Equation (2.9) (Razavi, 2002).

| | (2.9)

2.11 Summary

A brief explanation of CMOS and CCD image sensor is reviewed in the start of this

Chapter, after that a fundamental and the comprehensive survey of range image

methods including interferometery, triangulation and TOF is explained. Different

types of passive pixels and active TOF pixels are reviewed including their

advantages and disadvantages. The detailed explanation of active and passive pixel

sensors is also given. Various topologies of CMOS amplifiers included Two-Stage

Operational Amplifier, Folded Cascode, Telescopic and Cascode Amplifiers are

explained. The design methods for the pixel amplifier in this work are adopted from

34  

this chapter. A general overview of CTE and their equations are also derived.

Moreover, TOF active pixel and their configuration are discussed in detail.

35  

CHAPTER 3

RESEARCH METHODOLOGY AND DESIGN

3.1 Introduction

In this Chapter, research methodology and design is presented in detail. Four types

of amplifiers which are the Two-Stage OPAMP, Folded Cascode, Telescopic and

Cascode Amplifiers are designed and compared in terms of Charge Transfer

Efficiency (CTE). These designed amplifiers are shown in this Chapter. It gives a

measure on how efficiently an input charge is translated to the output. Moreover, the

configuration of the Active TOF pixel using CMOS amplifiers in general is

discussed in detail. The proposed pixel works using the pulse modulated TOF

method, where CTE method induced by a square light pulse is divided into two

capacitors controlled by the two switches connected in feedback path according to

the delay caused by the TOF. A flow chart outlining the design procedures for

designing the amplifier and TOF Active Pixel sensor is shown in Figure 3.1.

36  

F

3.2 Variou

Four diffe

Telescopic

two stages

this work.

consumpti

Figure 3.1: FA

us CMOS A

erent types o

c and Casco

s in choosin

The first s

ion. This sta

Flow CharActive Pixe

Amplifier D

of CMOS a

ode Amplifi

ng the best

stage is com

age makes u

37

rt Illustratinel Sensor u

Designs

amplifiers li

fiers are des

amplifier to

mparing amp

use of CTE

7 

ng the Desising Ampli

ike Two-Sta

signed for th

o be used in

plifiers acco

equation to

ign Procedifiers Topo

ures for thlogies

he TOF

age OPAMP

he active TO

n designing

ording to th

o shortlist am

P, Folded C

OF pixel. T

g the TOF p

heir gain an

mplifiers ac

Cascode,

There are

pixel for

d power

ccording

 

to their CTE. The final stage is to simulate the shortlisted amplifiers in the TOF pixel

to confirm the pixels functionality.

3.2.1 Design Specifications and Process Parameters

The target specifications of the amplifier design are given in Table 3.1.

• The voltage chosen here for design is 3.3V, because the technology used is

0.18µm TSMC, which allows the maximum of 3.3V (Euro Practice, 2010 b).

• The open loop gain must be greater than 120dB because, active TOF pixel is

already designed with the gain less than 120dB in literature (Halin &

Kawahito, 2004).

• The power dissipation should be as minimum as possible with minimum

number of transistors

Table 3.1: Target Specifications of Design

Specification Target Value Unit

Power Supply 3.3 Volts (v)

Open loop Gain Av ≥ 120 Decibels (dB)

Power Dissipation ≤ 1.64u Watts (W)

The process parameters of the PMOS and NMOS devices (TSMC 0.18µm) used in

analytical calculations for different types of amplifiers are tabulated in Table 3.2.

The ‘Vth(n,p)’ threshold voltage and ‘Kn,p’ is the process transconductance for the

NMOS and PMOS transistors respectively.

38  

Table 3.2: TSMC 0.18µm Process Parameters

Symbol PMOS NMOS Unit

Process Transconductance Kp, Kn 92.481 218.26 µA/V2

Threshold Voltage Vtp, Vtn -0.39 0.37 V

3.2.2 Two-Stage Operational Amplifier

The design of CMOS Two-Stage OPAMP is shown in the Figure 3.2. In the first

stage of OPAMP structural design, M1 and M2 are input NMOS transistors and their

transconductance appears in gain expression. The gate length of these transistors is

kept wide enough operating with very small overdrive voltage VOD so that they can

produce high gain and high Input Common Mode Rejection ratio (ICMR). The

PMOS transistors M3 and M4 must have high output resistance to fulfil the

requirement of high gain. Transistor M5 must have the doubled VOD voltage as

compared to the input devices. This confirms that all the transistors dimensions are

in similar order. Source follower configuration using PMOS transistors M6 & M8

and NMOS transistor M7 & M9 is cascaded as a second stage to increase the gain of

the amplifier (Razavi, 2002).

39  

Figure 3.2: Schematic Design of CMOS Two-Stage OPAMP

The design procedures regarding to the (W/L) values for the Two-Stage OPAMP are

as follows (Razavi, 2002; Sedra & Smith, 2004; Allen & Holberg, 2002).

To simulate this OPAMP design, it is necessary to kept all the PMOS and NMOS

transistors in saturation region. The W/L values for differential input NMOS pair,

M1 and M2 can be found through following equation as both transistors are

symmetric considering the minimum length of the 180nm process which is 0.18µm

(Euro Practice, 2010 b).

.

   ID12

WK L VGS V (2.1)

By rearranging Equation (2.1) simply it can be written as:

40  

WL ,

2IDK VGS V (2.2)

In Equation (2.2) Kn is the process transconductance for NMOS transistor, VGS is the

gate to source voltage and Vtn is the threshold voltage.

The W/L values of PMOS transistor M3 and M4 can be calculated as follows:

WL ,

2IDK VSG V (2.3)

In Equation (2.3) Kp is the process transconductance for PMOS transistor, VSG is the

gate to source voltage and Vtp is the threshold voltage.

The aspect ratio of the tail transistor M5 can be found through following equation:

WL

2IDK VGS V (2.4)

To increase the gain of the amplifier a Source Follower (SF) configuration using

PMOS transistors M6 & M8 and NMOS transistor M7 & M9 is cascaded as a second

stage. The aspect ratios of these transistors are calculated through the following

expressions as follows:

WL ,

IDK VSG V

WL

,,

IDK VGS V

(2.5)

41  

The total gain of the structure can be calculated as follows:

A   g , r ||r g , r ||r (2.6)

Where, gm1 is the transconductance of input transistor M1. The transconductance gm

and ro of MOS transistors are defined as:

at constant VDS

= 2 , (2.7)

where Kn,p = µCox = µ(εox/tox).

εox is the gate oxide permittivity and tox is the oxide thickness.

0  1

= 1/λID

(2.8)

where λ is the channel length modulation parameter. Finally, the total amplifier gain

and power must be checked against the specifications.

(2.9)

The aspect ratios of the Two-Stage OPAMP are tabulated in Table 3.3. Simulations

were performed with these calculated sizes of the MOSFETs to check the operating

42  

points of individual’s elements and the sizes were adjusted to get the appropriate

results.

Table 3.3: Aspect Ratios for Two-Stage OPAMP

Transistor Ratios of W/L (µm) (Calculated)

Ratios of W/L (µm) (Simulations)

M1, M2

M3, M4

M5

M6, M8

M7, M9

0.15/0.18

0.2/0.18

0.2/0.18

3/0.18

0.1/0.18

0.2/1.5

0.3/1.5

0.3/1.5

4/1.5

0.2/2.5

3.2.3 Single Ended Folded Cascode Amplifier

Figure 3.3 gives the schematic representation of Folded Cascode Amplifier. The

difference in this architecture lies in the folding of the input differential stage. The

main advantage of this architecture is its higher gain and the choice of different

voltage levels (Razavi, 2002). According the Figure 3.3, M1 and M2 are NMOS

input driver transistors which form the input differential pair and PMOS M6 & M7

are the cascode transistors. The transistors M1 and M2 act as a common source

amplifier. Thus for differential input signal each transistor pair M1-M7 and M2-M6

act as a Folded Cascode amplifier. Transistors M4 and M5 provide the constant bias

current and the tail transistor M3 gives the constant current which is used for biasing

the differential pair (Sedra & Smith, 2004).

43  

M1M1M2M2

VDDVDD

GNDGND

M9M9

M10M10

Vb3Vb3Vo2Vo2

Vin-Vin-Vin+Vin+

Vb1Vb1

Vb2Vb2

Vo1Vo1

M3M3

M4M4M5M5

M6 M6 M7M7

M8 M8

Vb4Vb4

GNDGND

M11M11

Vb5Vb5

I1I2

I3

I4

I6

I5

I7

Figure 3.3: Schematic Design of CMOS Folded Cascode Amplifier

All the transistors M1-M11 should be kept in saturation with proper bias values to

get the proper values of W/L.

The design approach for the Folded Cascode Amplifier is as follows (Razavi, 2002;

Allen & Holberg, 2002):

Bias currents I4 and I5, should be designed so that I6 and I7 never become zero i.e. I4

= I5 = 1.5I3. Avoid zero current in cascaded and maximum output voltage Vout (max)

will be:

44  

2,

2, (2.10)

where VSD5(sat) = VSD7 (sat) = 0.5[VDD - Vout(max)]

Now, for transistors M8, M9, M10 and M11, following expressions are used.

2,

2

(2.11)

(2.12)

where VDS9 (sat) = VDS11 (sat) = 0.5[Vout(min)-Vss] and for transistor M1and M2 the

aspect ratios can be calculated as follows:.

,2 , (2.13)

and for transistor M3:

2 (2.14)

Now, the differential gain can be found by knowing the gm and ro of the transistors.

The relationship between gm and ro with the aspect ratio of the transistors are defined

as follows.

45  

at constant VDS

= , =

(2.15)

where Kn,p = µCox = µ(εox/tox).

εox is the gate oxide permittivity and tox is the oxide thickness.

0  1

=1/λID

(2.16)

The differential gain of the the amplifier can be calculated as follows:

, , , , || , , , || , (2.17)

Finally, the power dissipation can be calculated through the following equation.

(2.18)

The aspect ratios in Folded Cascode amplifier are shown in Table 3.4. Simulations

were performed with these calculated sizes of the MOSFETs to check the operating

points of individuals elements and the sizes were adjusted to get the appropriate

results.

46  

Table 3.4: Aspect Ratios for Folded Cascode Amplifier

Transistor Ratios of W/L (µm) (Calculated)

Ratios of W/L (µm) (Simulations)

M1, M2

M3

M4, M5

M6, M7

M8, M9

M10, M11

0.08/0.18

0.02/0.18

0.9/0.18

0.2/0.18

0.03/0.18

0.03/0.18

1/2.5

0.4/4

1.2/1.5

0.4/1.5

1/1

0.4/2

Single Stage Folded Cascode amplifier is designed too and its schematic

representation is shown in Figure 3.4. This amplifier is further used in the pixel as

active element, because of high gain and low power and is best suited for TOF

pixels.

M1M1

VDDVDD

GNDGND

M5M5

Vb3Vb3

VinVin

Vb1Vb1

Vb2Vb2

VoutVout

M2M2

M3 M3

M4 M4

Vb4Vb4

GNDGND

Figure 3.4: Schematic Design of CMOS Single Ended Folded Cascode Amplifier

47  

The aspect ratios of single ended Folded Cascode amplifier are also calculated using

the methodology discussed above. These are shown in Table 3.5. Simulations were

performed with these calculated sizes of the MOSFETs to check the operating points

of individuals elements and the sizes were adjusted to get the appropriate results.

Table 3.5: Aspect Ratios for Single Ended Folded Cascode

Transistor Ratios of W/L (µm) (Calculated)

Ratios of W/L (µm) (Simulations)

M1

M2

M3

M4

M5

0.2/0.18

0.1/0.18

0.6/0.18

0.02/0.18

0.02/0.18

1.0/2.5

1.2/1.5

0.4/1.5

1.0/1.0

0.4/2.0

3.2.4 Telescopic Amplifier

The schematic representation of Telescopic amplifier is shown in Figure 3.5. One of

the main advantage of this architecture its higher gain because it gives a gain on the

order of (gmro)3 /2. The drawback of this topology is its limited output swing. With

six overdrive voltages (VOD) in one column line which includes the transistors M1,

M4, M6, M8, M10 and M12 are subtracted from VDD, it is far difficult to operate the

amplifier from the supply voltage of less than 3V while obtaining reasonable output

swing (Razavi, 2002; Gulati & Lee, 1998). In these configuration three PMOS

transistors and three NMOS transistors are cascoded in two columns and the tail

transistor M13 gives the constant current which is used for biasing the differential

48  

pair M1 and M2. All the transistors M1-M13 should be kept in saturation with

proper bias values to get the proper values of W/L.

VDDVDD

Vb5Vb5

Vin2Vin2

Vb1Vb1

Vb2Vb2

Vo1Vo1

M1M1M2M2

M5 M5

GNDGND

Vb3Vb3

M3M3

Vb4Vb4

M4 M4

Vin1Vin1

Vo2Vo2M6 M6

M7 M7 M8 M8

M9 M9 M10M10

M11M11 M12 M12

Vb6Vb6M13M13

Figure 3.5: Schematic Design of CMOS Telescopic Amplifier

The aspect ratios for this type of amplifier are calculated as follows (Razavi, 2002;

Sedra & Smith, 2004):

In fully differential version, for example, the output swing ‘Vosw’ can be calculated

using:

49  

2 VDD VOD VOD VOD VOD |VOD | |VOD | |VOD | (2.19)

where VOD is the overdrive voltage of the transistor M1, M4, M6, M13, M8, M10

and M12.

In second step the aspect rations of tail transistor M13 can be calculated as through

the following equation considering the minimum length of the 180nm process which

is 0.18µm:

2I13Kn VGS Vtn

2 (2.20)

For designing the differential pair transistors M1 and M2, saturation region drain

current equation is used.

,2I1

Kn VGS Vtn2 (2.21)

The common mode voltage that allows M9 to be in saturation will be Vin,CM ≥ Vsat13

+ VGS1. Similarly, the (W/L)3,4,5,6 can be determined from the same equation because

the same current is flowing through NMOS transistors M3, M4, M5, M6 but having

the different VGS value.

, , ,2I1

Kn VGS Vtn2 (2.22)

50  

The current passing through the cascode current mirror stage consisting of six PMOS

transistors M7, M8, M9, M10, M11 and M12 are same and their aspect ratios can be

calculated through the expression:

, , , , ,2I1

Kp VSG Vtp2

A gm ,   gm , ro , ro , ro , ||gm , ro , ro , ro ,

(2.23)

The total gain of the structure can be written as follows:

(2.24)

The transconductance gm and ro of MOS transistors are defined as:

at constant VDS

= 2 ,

=

(2.25)

where Kn,p = µCox = µ(εox/tox).

εox is the gate oxide permittivity and tox is the oxide thickness.

0  1

=1/λID

(2.26)

51  

Finally, the power dissipation can be calculated through the following expression.

(2.27)

s of individual’s elements and the sizes were

djusted to get the appropriate results.

3.6: A copic

Transistor Ratios of W/L (µm) (Calculated)

Ratios of W/L (

Simulations were performed with these calculated sizes of the MOSFETs shown in

Table 3.6 to check the operating point

a

Table spect Ratios of Teles Amplifier

µm) (Simulations)

M1, M2

M3, M4

M5, M6

M7, M8

M9, M10

M11, M12

M13

0.5/0.18

0.8/0.18 0.8/3.0

0.5/0.18

0.5/0.18

3/0.18

3/0.18

3/0.18

0.4/2.0

0.4/2.0

0.3/2.0

0.5/1.5

1.0/1.5

0.3/2.5

3.2.5 Cascode Amplifier

w power consumption. The drawback is its limited output

swing (Razavi, 2002).

Cascode configuration is widely used in the low frequency amplifiers because it

provides larger gain. The schematic representation of the triplic Cascode amplifier is

shown in Figure 3.6. The one of the main advantage of this type of amplifier is its

very high gain and lo

52  

VDDVDD

M6M6

Vb5Vb5

VinVin

Vb1Vb1

Vb2Vb2

VoutVout

M1M1

M2M2

M5 M5

GNDGND

Vb3Vb3

M3M3Vb4Vb4

M4 M4

Figure 3.6: Schematic Design of CMOS Cascode Amplifier

The design steps for the Cascode amplifier are as follows:

The output swing ‘Vosw’ can be calculated as through the given equation.

V 2 VDD VOD VOD VOD |VOD | |VOD | |VOD |   (2.28)

Here VOD1 to VOD6 are the overdrive voltages of the transistor M1 to M6

respectively. The aspect ratios of the three NMOS transistor, M1, M2 and M3 can be

calculated using Equation (2.29) as through the following expression as the same

current of 0.4µA is passing through them.

, ,2IDD

Kn VGS Vtn2 (2.29)

53  

And the aspect ratios of PMOS transistor M4, M5, M6 are calculated using the same

procedure because same current IDD flows through them. The aspect ratios are

calculated as follows.

, ,2I1

Kp VSG Vtp2 (2.30)

The total gain of the structure can be checked by calculating gm and ro of the

transistors. The relationship between gm and ro with respect to the rations of the

transistors are defined as follows:

at constant VDS

= , = (2.31)

where Kn,p = µCox = µ(εox/tox).

εox is the gate oxide permittivity and tox is the oxide thickness.

0  1

=1/λID

(2.32)

The gain of the design can be calculated using following equation:

    || (2.33)

54  

Finally, the power dissipation can be calculated through the following expression.

(2.34)

Simulations were performed with these calculated sizes of the MOSFETs to check

the operating points of individual elements and the sizes were adjusted to get the

appropriate results. The transistor sizes of are tabulated in Table 3.7.

Table 3.7: Aspect Ratios of Cascode Amplifier

Transistor Ratios of W/L (µm) (Calculated)

Ratios of W/L (µm) (Simulations)

M1

M2

M3

M4

M5

M6

1.3/0.18

1.3/0.18

1.3/0.18

0.06/0.18

0.06/0.18

0.06/0.18

0.3/2.5

0.4/2.5

0.3/2.5

0.3/1.5

1.0/1.5

0.3/3.0

3.2.5 Gain and Phase Measurement Method

An ideal OPAMP has an amplification of A = ∞ at every frequency but in reality

OPAMPs have only an amplification of approximately AV = 106 over a small

frequency range from DC to 10Hz. The application of negative feedback requires

analysis of the open loop gain. The output voltage Vo is defined by Vin × A (Vin =

Input voltage and A = Open loop gain). An amplifier has inverting and non-inverting

inputs and the input voltage is defined as the voltage difference between the

inverting and non-inverting input (Sedra & Smith, 2004).

55  

The phase margin of the amplifier is measured by simulating the plot of the gain in

decibel ‘dB’ over frequency. The frequency at which the gain went to 0dB (Gain =

1) was measured. The Phase Margin (PM) of the amplifier is obtained from the plot

of phase versus frequency. Also the –3dB frequencies were obtained from the plot of

gain (dB) versus frequency which gives the 3dB bandwidth (Sedra & Smith, 2004).

The gain and phase of all the designed amplifiers are shown in Chapter 4.

3.3 Amplifier Selection

A high performance amplifier is characterized by a high open loop gain, high

bandwidth, high input impedance, low input impedance and an ability to amplify

differential mode signal to a large extent and at the same time, rigorously attenuate

common mode signals (Sedra & Smith, 2004).

Initially, all the amplifiers are analyzed to find the various tradeoffs in terms of

power, gain and number of transistors. All these amplifiers are designed and

compared with the focus that current should be minimum possible and with

maximum possible gain while other parameters such as phase, slew rate, stability etc

are not taken into consideration. This is due to the operation of the pixel where

discrete photo charge are generated and transferred as the signal. Moreover the

signal is single polarity and can be assumed as DC. Two best amplifiers which are

Cascode and Folded Cascode are selected to be used in TOF active pixels because of

higher gain and minimum power dissipation.

56  

3.4 Charge Transfer Efficiency (CTE)

The schematic diagram of active pixel TOF sensor is shown in Figure 3.8. In this

circuit Photo Diode (PD) is a light sensing element and high gain amplifier is used as

an active element. The φ1, φ2 and C1, C2 are the feedback switches and capacitors

respectively while φR is the reset switch which will be activated only once in the

accumulation time. Incomplete charge transfer from the PD to the feedback

capacitors C1 and C2 when the switches φ1, φ2 turned on which contributes to non-

linearity, if the gain of the amplifier is not high enough. This is because the charge in

the photo diode that should be transferred to C1 is transferred to C2 as error charge

and vice versa shown in Figure 3.7. As an accumulation time TA increases, the effect

of these left over charge accumulations causes non-linearity (Halin & Kawahito,

2004).

PD

C1

C2

Iph

1

2

R

AmpVout

φ

φ

φ

Figure 3.7: Active Pixel TOF Sensor

Charge Transfer Efficiency (CTE) equivalent circuit representation is shown in

Figure 3.8. CTE is calculated as the ratio of output charge ‘Qout‘ to the input charge

57  

‘Qin’(no. of electrons). In standard CMOS technology, the method of choice for

achieving high speed and highly efficient charge transfer is declared to be negative

feedback inverting amplifier circuit. Linearity of circuit will get proportionally

increased with the improvement in gain amplifier.

AmpVoutVi

CFB

CPD Ci

FBφ

Figure 3.8: Equivalent Charge Transfer Efficiency Circuit (Halin & Kawahito, 2004)

Different amplifiers that are designed are used in this circuit, a capacitor CFB = 5fF

and a switch φFB respectively in its feedback. At the input, there is an input capacitor

Ci = 10fF and CPD = 20fF photodiode capacitor. The CTE or ‘η’ of TOF sensor is

given by:

QFBQPD

η

     1  ACFB

CPD C 1 A CFBHalin & , 2004

(3.35)

58  

3.4.1 Amplifier CTE Analysis

ons

sing Boltzmann’s Constant i.e. k = 1.602 × 10-19 C) in Section (4.3), Chapter 4.

Figure 3.9: CTE Amplifiers Analysis ircuit (a) Without Dummy Switches (b) With Dummy Switches

Keeping in view the requirement of high gain for maximum CTE, four different

architectures of CMOS amplifiers are considered in this work. The amplifiers are the

Two-Stage OPAMP, Folded Cascode, Telescopic and the Cascode Amplifiers.

Figure 3.9 shows the configuration of CTE amplifiers analysis with and without

dummy switches. At the input there is photo-diode equivalent circuit for simulation.

CTE of four designed amplifiers is plotted as Qout versus Qin (number of electr

u

AMPLIFIERo/p

CFB

IphAMPLIFIER

o/p

CFB

Iph

Iph

FB

Iph C

φφFB

FBφ

C

(a) (b)

C

59  

3.5 Active Pixel TOF Sensor Design and Functionality Simulation

ifier. These amplifiers are designed in Section (3.2.2) and (3.2.4)

spectively.

Figure 3.10 (a) and (b) shows the schematic representation of active TOF pixel with

and without dummy switches respectively. Two TOF pixels as in Figure 3.10 are

simulated. The configuration of both TOF pixels is the same except the amplifier.

The first pixel utilizes the Cascode amplifier while the second pixel uses the Folded

Cascode ampl

re

Both the amplifiers are chosen because of high gain, minimum power dissipation and

minimum numbers of transistors used. The time delayed photo generated charges

transferred to the feedback capacitors C1 = C2 = 10fF when the feedback switches (φ1

& φ2 are turned on respectively. The switches φ and φ are input for the dummy

switches for charge cancellation. The fast photo-charge transfer is also due to the

negative feedback configuration of the circuit.

Figure 3.10: Schematic of Simulated TOF Pixel (a) Dummy Switches in Pixel (b) No Dummy Switches in Pixel

Vo

C2

CoVin Vo

Iph Co

Vin

φ1

φ2

φ1

φ2

φ1

φ2

φR

φR

Iph

C1C1

C2

CPD CPD

AMP AMP

60  

The operation of the TOF sensor depends upon the control pulses which are shown

in Figure 3.11. The signals φ1 and φ2 are used to control the light TOF dependent

photo charge transfer while φR is used to reset the pixel at the beginning of the

accumulation time. Each pixel is simulated with an input light pulse of 1pA running

at 1MHz at a 10% duty cycle. Reflected light pulse is shown in figure which has also

the same duty cycle as the pulse φ1 and φ2 but with some delay TD.

100ns

200ns

1000ns

TA = 5ms

1

2

Rφ

φ

φ

100ns

TD

R L P

Figure 3.11: Control Signals for the TOF Active Pixel Sensor

3.6 Range Measurement Calculation for Active TOF Pixels

For one complete accumulation cycle, charges Q1 and Q2 depend on three known

time variables. These are the TA, the TOF time delay TD and width of light pulse T0.

The received pulse maintains the same frequency as the transmitted pulse but lags φ1

by TD and will induce a pulsing photo current that has the equal timing

characteristics as the arriving pulse. Since TD information is available in Iph range

61  

calculations could be carried out in the charge domain. The charges Q1 and Q2

depending on TD are given as:

(3.36)

(3.37)

As, from Equation (3.37), Iph = Q2 / TD, putting the value of Iph in Equation (3.36) i.e.

(3.38)

This equation can be written as:

2

(3.39)

By the fact that the TOF of light is TD, the time required for a photon to travel from

the TOF system to the object is (TD/2). To obtain the actual distance of the object L

this is shown in Equation (3.8) as:

(3.40)

Now, putting the value of TD in Equation (3.40) and also replacing charge Q1 and Q2

with the number of electrons in C1 and C2 as N1 and N2 respectively, distance L is

given by:

62  

2 (3.41)

It is obvious that Q1 and Q2 can also be replaced by the inverting amplifier outputs

V1 and V2 if C1 = C2 (Halin & Kawahito, 2004).

3.7 Photodiode Model and Required Light Intensity

The requirement for light intensity is mainly depends on the maximum range and

area. A PD model is shown in Figure 3.12. It includes a current source in parallel

with the capacitor ‘Cph’. The current source (with photocurrent Iph) represents the

current generated by the incident radiation. The actual light source or On-chip PD’s

cannot be simulated. This estimated PD model is used for simulation purpose.

Light Iph

Iph

VdCph

Figure 3.12: Photodiode Model for Simulation

If the TOF pixel is designed with a feedback capacitor Cs of 10fF, the signal swing

ΔV across Cs is 0.6V for the total number of electrons of 50000. The required photo

current Iph for one TA is calculated as:

63  

(3.42)

From Eq. (3.42), if TA = 5ms, Tp = 1μs and T0 = 100ns, Iph is calculated to be

approximately 0.92pA (Halin & Kawahito, 2004).

3.7 Summary

The current chapter describes the research methodology for preparing an Active TOF

range image sensor. The differences between the sensors are the use of four different

amplifiers which are Two-Stage OPAMP, Folded Cascode, Telescopic and Cascode

Amplifiers. Calculation of the light pulse is also described. CTE simulation is

detailed to analyze the most suitable design of TOF the pixel. Results of amplifier

design, CTE, TOF pixel functionality, linearity improvement using dummy switches

are explained in Chapter 4.

64  

CHAPTER 4

RESULTS AND DISCUSSION

4.1 Introduction

In this Chapter, the results obtained from the design described in Chapter 3 are

shown. The results of this research are presented and analysed. All the amplifiers

that are designed in Chapter 3 are simulated using a power supply of 3.3V in Mentor

graphics tool in 0.18µm TSMC process and select the best amplifiers in term of gain

and power (Euro Practice, 2010 a). The TSMC 0.18µm technology is used due to its

high transconductance, high output impedance and low threshold voltage and as well

as small chip area of the device. All these CMOS amplifiers are compared in terms

of Charge Transfer Efficiency (CTE) when used as a Time of Flight (TOF) range

pixel for range imaging. Moreover, Cascode and Folded Cascode TOF active pixels

are simulated and made a detailed comparison between them.

4.2 Amplifier Simulation Results

The parameters of gain and phase margin are measured by means of analysis of the

open loop AC response simulation. Results of the amplifiers that are designed in the

Chapter 3 i.e. Two-Stage OPAMP, Folded Cascode, Telescopic and Cascode

Amplifiers are described here in detail. All these amplifiers are simulated in 0.18 µm

TSMC process using Mentor Graphics tool using a supply voltage of 3.3V.

65  

The other results such as output swing, phase and slew rate are not important and are

not taken into consideration because the input for the active TOF pixel in which these

amplifiers are used as active element is square pulse. Moreover, the signal used is a

single polarity and can be assumed as DC.

4.2.1 Two-Stage OPAMP Simulation Results

In general, a good performing amplifier needs a gain greater than 10dB and phase

margin about 45-60 Degrees. Otherwise, the amplifier would possibly exhibit ringing

in the time domain and peaking artifacts in the frequency domain. These are the

artifacts that come out as fake signals near transitions in signals (Wikipedia, 2011).

In Figure 4.1 (a) and (b), it can be seen the frequency response of the used Two-

Stage OPAMP that is the gain is 69.44 dB and the phase margin is 42.20º. This Two-

Stage OPAMP is simulated using a 0.18µm TSMC using 3.3V CMOS process.

Further this amplifier is used as active element in the pixel. The phase is not

important in the active TOF pixel design because the input for the pixel is a square

wave. The dissipated power by this type of amplifier is 6.6µW. The simulated results

of the Two-Stage OPAMP are tabulated in Table 4.1.

66  

Figure

4.1: Frequ

Table

Perfo

Po

uency Resp

e 4.1: Simul

ormance TwOPAMP

PM

DC Gain

ower Dissip

67

onse of Tw(b) Ph

lated Resul

wo-Stage P

n

pation

7 

wo-Sage OPhase

lts of Two-S

Si

PAMP (a) G

Stage OPA

imulated V

42.20º

69.44 dB

6.6 µW

Gain Bandw

AMP

Value

B

width

 

4.2.2 Single Ended Folded Cascode Amplifier Simulation Results

The frequency response of the Single Ended Folded Cascode and Two-Stage Folded

Cascode Amplifiers are shown in Figure 4.2 (a) and (b). The Two-Stage Folded

Cascode amplifier has the higher gain of 117.21 dB as compared to Single Stage

Folded Cascode i.e. 87.23 dB. As the Two-Stage Folded Cascode amplifier has

higher gain and should be selected for Active TOF pixel, but the drawback of this

configuration is that it has 11 numbers of transistors and consumes 6.6µW of power.

The dissipated power of the single ended Folded Cascode is 2.64µW which is best

suited for active TOF pixel. Simulated results of these amplifiers are tabulated in

Table 4.2.

68  

Figure 4Folded

4.2: Frequed Cascode A

Cascode

ncy ResponAmplifier (Ge Amplifier

69

(a)

(b)

nse of FoldGain Bandr Design (G

9 

)

)

ded Cascodedwidth and Gain Bandw

e AmplifierPhase) (b)

width and P

r (a) Single 2-Stage Fo

Phase)

e-Stage olded

 

Table 4.2: Simulated Results of Folded Cascode Amplifier

AMP Parameter Simulated Value of Single Stage Folded

Cascode

Simulated Value of Two-Stage Folded Cascode

PM 54.47º 2.40º

DC Gain 87.23 dB 117.21 dB

Power Dissipation 2.64 µW 6.6 µW

4.2.3 Telescopic Amplifier Simulation Results

The AC response of the Telescopic Amplifier is shown in Figure 4.3 (a) and (b). It is

obvious that it has a gain of 106.73 dB and Phase of 86.82o. This high gain is best

suited for TOF active pixel, but the disadvantage of this type of configuration is that

it has more dissipated power which is 3.3µW. The number of transistors in this

configuration is 13, which definitely increase the size of pixel and said to be power

hungry. So, it is not used in the active pixel sensor. The simulated results of the

Telescopic Amplifier are tabulated in Table 4.3.

70  

Figure 4

4.3: Freque

Table

A

Po

ency Respo

e 4.3: Simu

MP Param

PM

DC Gain

ower Dissip

71

onse of Tele(b) Ph

ulated Resu

meter

n

pation

1 

escopic Amhase

ults Telesco

Simu

1

mplifier (a) G

opic Amplif

ulated Valu

86.82º

06.73 dB

3.3 µW

Gain Band

fier

ue

dwidth

 

4.2.4 Casccode Amplifier Simullation Resuults

To achiev

in section

µA. This

power dis

higher ga

amplifier

Amplifier

ve a high ga

3.2.4 is us

extremely

ssipation of

in and is b

is shown in

tabulated in

ain with sim

sed. A gain

small bias

f the TOF a

best suited

n Figure 4.4

n Table 4.4

mple configu

of 131.23

current pla

active pixel

for TOF P

4 (a) and (b

.

uration, a tr

dB is obtai

ays an imp

l sensor. Th

Pixels. The

b). The sim

riple Cascod

ined with a

portant role

his Cascode

e gain and

mulated resu

de amplifie

bias curren

in minimiz

e amplifier

phase plot

ults of the C

er shown

nt of 0.4

zing the

has the

t of this

Cascode

Figuree 4.4: Frequuency Respponse of Ca

72

(b) Phascode Ampplifier (a) GGain Bandwhase

width

2  

Table 4.4: Simulated Results of Cascode Amplifier

AMP Parameter Simulated Value

PM 84.38º

DC Gain 131.28 dB

Power Dissipation 1.32 µW

4.2.5 Comparison of Amplifiers

Four different types of amplifiers discussed above are analyzed in terms of gain,

power and number of transistors. Phase is not an important parameter, this is because

of pixel operation where discrete photo charge are generated and transferred as the

signal for the input of the amplifier. Comparison of these amplifiers is tabulated in

Table 4.5. In the subject study, the Two-Stage OPAMP has a very low gain and

Telescopic Amplifier has high dissipated power, so these amplifiers are neglected

and the Folded Cascode and Cascode amplifiers are chosen because of high gain,

minimum dissipated power and minimum number of transistors.

73  

Table 4.5: Comparison of Different Amplifiers

Amplifier’s Type Gain (dB)

No. of Transistors

Power (Watts)

Two-Stage OPAMP 69.44 9 6.6 µ

Folded Cascode 87.26 11 2.64 µ

Telescopic 106.73 13 3.3 µ

Cascode 131.28 6 1.32 µ

4.3 Charge Transfer Efficiency (CTE) Analysis

In order to find CTE, the gains of different amplifiers designed and discussed in

Chapter 2 and 3 i.e. Two-Stage OPAMP, Folded Cascode, Telescopic and Cascode

amplifiers are plotted as Qout versus Qin (no: of electrons using Boltzmann Constant

k = 1.602 × 10-19 C) using Matlab tool. Figure 4.5 shows the CTE plot calculated

using equation of CTE ‘η’ for the four amplifiers designed. The value of the

capacitors CPD, Ci and CFB associated with the pixel are 20fF, 10fF and 5fF,

respectively. From the plot, the Two-Stage Op-Amp which has a gain of 69.4dB

exhibits the lowest CTE, thus it is not considered for the TOF pixel design. Although

Figure 4.5 shows that the Telescopic amplifier has second highest gain of 106.73dB,

but it consumes the highest amount of power which is approximately 3.3µW.

Moreover, it also has the most number of transistors (13 transistors), thus would be

difficult to be used in the layout of the TOF pixel. The gain of the Cascode and

Folded Cascode amplifiers are 131.28dB and 87.26dB, respectively while their

power consumption is 1.32µW and 2.64µW, respectively. These initial results reveal

that the Cascode and Folded Cascode amplifier are the two most suitable amplifiers

74  

to be used in the TOF pixel.

CascodedTelescopicFolded Cascode 2-Stage Opamp

Qout

(no.

of e

lectro

ns)

Qin (no: of electrons)20k 40k 60k 80k 100k 120k 140k 160k 180k 200k 220k

200k

140k

20k

180k

50k

160k

80k

110k

Figure 4.5: Calculated Charge Transfer Efficiency

4.3.1 CTE Amplifier Simulation

In order to find CTE, the gains of different amplifiers designed and discussed in

Chapter 2 and 3, i.e. Two-Stage OPAMP, Folded Cascode, Telescopic and Cascode

amplifiers are simulated. The charge accumulated at feedback capacitors of different

amplifiers are tabulated in Table 4.6 and plotted in Figure 4.6.

75  

Table 4.6: Charge Accumulated at the Output of different Amplifiers

Qin (# of

electrons)

Cascode Q0

(# of electrons)

Telescopic Q0

(# of electrons)

Folded Cascode

Q0 (# of

electrons)

Two-Stage OPAMP

Q0 (# of

electrons)

3.74E+04 5.24E+03 4.12E+03 2.98E+03 1.77E+03

5.20E+04 8.17E+03 6.86E+03 5.08E+03 3.62E+03

6.87E+04 1.11E+04 9.12E+03 6.86E+03 4.92E+03

7.82E+04 1.35E+04 1.04E+04 8.17E+03 6.38E+03

9.48E+04 1.63E+04 1.34E+04 1.11E+04 8.97E+03

1.03E+05 1.87E+04 1.43E+04 1.24E+04 1.01E+04

1.11E+05 2.06E+04 1.63E+04 1.38E+04 1.14E+04

1.53E+05 2.94E+04 2.36E+04 1.99E+04 1.68E+04

1.76E+05 3.88E+04 3.04E+04 2.55E+04 2.20E+04

2.07E+05 6.79E+04 4.94E+04 3.87E+04 2.98E+04

CascodedTelescopicFolded Cascode 2-Stage Opamp

Qin (no: of electrons)

Qout

(no.

of e

lect

rons

)

20k 40k 60k 80k 100k 120k 140k 160k 180k 200k 220k

200k

140k

20k

180k

50k

160k

80k

110k

Figure 4.6: CTE Amplifiers Analysis

76  

The CTE simulation of the Folded Cascode and Cascode amplifiers are done

subsequently to obtain a better picture of their efficiency in the TOF pixel. Figure 4.6

shows the simulated CTE for the four amplifiers. The simulation was carried out

using the schematic in Figure 3.9 for a 10% duty cycle, 1MHz pulsed input photo-

current of 1pA, Ci = 10fF and CFB = 5fF for an integration time of 5ms. Figure shows

that it is not linear in the middle. The linearity can be improved by increasing the

gain of the amplifier. The resulting plot in Figure 4.6 shows that the Cascode

amplifier has an efficiency of 95.08% while the Folded Cascode amplifier has an

efficiency of 82.78%. it is shown in Figure 4.6

4.4 Cascode TOF pixel

To achieve a high gain with simple configuration, a triplic Cascode amplifier is used

as discussed earlier. A gain of 131.28dB is obtained with a bias current of 0.4μA.

This smaller bias current 0.4μA is necessary in reducing the power dissipation of the

whole TOF sensor. It operates at 1MHz with C1 = C2 = 10fF. Figure 4.7 shows the

transient simulation output of node Vout at 1MHz operation at a particular time delay

of TD=0ns. For this result, V1 and V2 are outputs that correspond to the clock φ1 and

φ2, respectively.

It can be seen in the Figure 4.7 that as accumulation time increases, V1 increases

fastly than V2. This corresponds to photo charge transfer only into C1, since Iph is

perfectly in phase with clock φ1 in this case. If TD is varied, the amplitudes of V1 and

V2 change resulting in the appropriate range.

77  

VrestV1 V1 V1 V1 V1 V1

V1 V1V1

V2V2V2

V2 V2 V2 V2 V2 V2

0.2v

0.4v

0.6v

1.5v

2.6v

Accumulation Time (sec)

Volta

ge (v

)

V1V1

V2V2

V1

V2

2.4v

0.00 5.00m2.00u 100u 200u 3.00m 3.50m 4.50m

2.2v

Figure 4.7: Cascode TOF Pixel Simulation Output for TD = 0ns

4.4.1 Error charge and Non-Linearity in Cascode TOF Pixel

The amplifiers finite gain relate to the input-output of the TOF pixel according to the

following expression i.e. Vo = −AVi. This indicates that the input node fluctuates

with respect to the output resulting in an error charge added to another capacitor.

This phenomenon is worsened if a simple NMOS switch is used as the feedback

switch. The channel charge present under the gate of the switch will add more error

charge to the input node. To resolve this type of issue, a dummy switch of the same

size as the feedback switch is added to the TOF pixel, the source and drain of theses

dummy switches are tied together. When the dummy switch turns off, it injects a

charge twice the amount of that injected by the feedback switch into the amplifier’s

input node. Because it operates using an inverse pulse, the polarity of the injected

charge is opposite to that injected by the feedback switch. The first half of the charge

effectively cancels the charge injected by the feedback switch. The remaining half

would reduce the error charge caused by the amplifier’s finite gain.

78  

Figure 4.8 (a) shows the simulation results of signal voltage versus accumulation

time of 5ms for a Cascode pixel without dummy switches. Through simulation, it is

obvious that the addition of dummy switches improves output linearity and TOF

pixel sensitivity. Figure 4.8 (b) shows the case when the dummy switches are added

and it is the signal voltage versus TD for the TOF sensor also operating at 1MHz and

5ms is the accumulation time. The linearity and sensitivity are improved by the use

of dummy switches. For TD=50ns, equal charge is transferred into C1 and C2 hence

the two outputs V1 and V2 are equal resulting in a zero difference between the two

output voltage signals. As TD increases from 50ns (TD=70ns, 80ns and 100ns), the

amount of charge transferred to C2 is more than the amount of charge transferred to

C1, thus shifting the plot downwards. As TD decreases from 50ns (TD=30ns, 20ns

and 0ns), the amount of charge transferred to C1 is more than the amount of charge

transferred to C2 decreases, thus shifting the plot upwards. This plot confirms the

functionality of the Cascode amplifier TOF pixel.

79  

(a)

(b)

Figure 4.8: Signal Voltage versus Accumulation Time in Cascode Pixel

(a) No Dummy Switches (b) With Dummy Switches

80  

4.5 Folded Cascode TOF pixel

The same configuration like Cascode TOF Pixel is adopted for the Folded Cascode

TOF Pixel. It operates at 1MHz and the accumulation time of 5ms with two feedback

capacitors C1 and C2. Ideally in the case that the transmitted photo-pulse is

completely in phase to φ1, all of the photo charge induced in the PD by the received

photo pulse should be transferred only to C1. In turn only a voltage drop V1 across C1

is observed. Figure 4.9 shows the transient simulation of V1 and V2 (voltage drop

across C2) versus accumulation time of 5ms at particular TD=0ns, It is seen that there

is also a small amount of increase in V2.

Vrest

V1 V1 V1 V1 V1 V1

V1

V1

V1V1

V2

V2V2V2

V2 V2 V2 V2 V2 V2

0.2v

1.0v

1.6v

0.00 5.00m2.00u 100u 200u 3.00m 3.50m

0.4v

0.6v

0.8v

Accumulation Time (sec)

Volta

ge (v

)

1.2v

1.4vV1

V2

V1

V2

4.50m

Figure 4.9: Folded Cascode TOF Pixel Simulation Output for TD = 0ns

The increasing V2 voltage which is shown in Figure 4.9 is because of the residual

charge which is transferred to from PD to feedback capacitors C1 and C2. This

residual charge is caused by incorrect transfer of charge due to a small gain of the

81  

folded cascade amplifier. At first all the photo charges accumulated in the PD are

partially transferred to the capacitor C1 when the switch φ1 is closed and a small

amount of charge is left in the PD. This left over residual charge is transferred to C2

when switch φ2 is closed leaving behind more residual charge. When a new amount

of photo-charge is accumulated in the PD, it will be added to the remaining residual

charge left behind after switch φ2 turns-off. This process is repeated during of the

signal integration cycle resulting in an accumulation of error charge in the feedback

capacitors.

The channel charge present under the gate of the switch will add more error charge

to the input node. To resolve this type of problem, dummy switches of the same size

as the feedback switch but where the source and drain are tied together is added to

the TOF pixel. It is operated using an inverse pulse. When the dummy switch turns

off, it injects a charge twice the amount of that injected by the feedback switch into

the amplifier’s input node. Because it operates using an inverse pulse, the polarity of

the injected charge is reverse to that injected by the feedback switch. The first half of

the charge effectively cancels the charge injected by the feedback switch. The

remaining half would minimize the error charge caused by the amplifier’s finite gain

to a great extent.

Figure 4.10 (a) shows the simulation results of signal voltage versus accumulation

time for a pixel without dummy switches. Through simulation, the addition of

dummy switches improves output linearity of the TOF pixel.

82  

(a)

(b)

Figure 4.10: Signal Voltage versus Accumulation Time in Folded Cascode Pixel (a) No Dummy Switches (b) Dummy Switches in Pixel

83  

Figure 4.10 (b) shows the case when the dummy switches and it is the signal voltage

versus TD for the TOF sensor also operating at 1MHz and 5ms accumulation time. It

is shown that a slight improvement is achieved with the addition of dummy witches.

Due to the low CTE, only 80% of the charge is transferred from PD and the output is

nonlinear. This is caused by imperfect charge transfer between C1 and C2. Initially,

the charge from PD is to be transferred into C1. When C2 is connected to the

feedback path, the charge left in PD is transferred to C2.This process of error charge

transfer is repeated throughout the accumulation time resulting more charge being

transferred to C1 even though TD>50ns. Moreover, the output difference starts to

saturate after 5ms. If a longer integration time is desired, this pixel will not output

correct values of V1 and V2 for range calculation.

4.6 Folded Cascode versus Gain Boosted

Both, the Folded Cascode and Gain Boosted amplifier are compared when used in

the TOF pixel. An extra stage in the gain boosting amplifier increase the overall gain

but this causes propagation delay. The comparison between the Folded Cascode and

Gain Boosted TOF pixels are shown in Figure 4.11. The solid line shows the Folded

Cascode Pixel while the dashed line shows the Gain Boosted TOF Pixel. In gain

boosting the charge transfer is not synchronized with the TOF of the light pulse due

to the propagation delay of two amplifier stages. This results in the nonlinear charge

transfer.

84  

0 1 2 3 4 5-0.02

0.00

0.02

0.04

0.06

0.08

0.10

0.12

0.14

0.16

Vol

tage

V1-

V2

(V)

AccumulationTime (msec)

TD (*0ms) TD (*20ms) TD (*40ms) TD (*60ms) TD (*80ms) TD (*100ms) TD (0ms) TD (20ms) TD (40ms) TD (60ms) TD (80ms) TD (100ms)

Figure 4.11: Comparison between Folded Cascode and Gain Boosted

4.7 Summary

In this Chapter, the results described in Chapter 3 from the design of Active TOF Pixels

have been discussed. The results of this research are presented and simulated using a power

supply of 3.3V in Mentor graphics with 0.18µm process. The simulation and analysis of

each building block used in design TOF Active Pixel Sensor proffered. The results confirm

that a high gain Cascode amplifier is best suited for TOF APS having the gain of 131.28dB

with the power dissipation of 1.32µW. Moreover, Cascode amplifier also gives the best

CTE which is 95.08%.

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CHAPTER 5

CONCLUSION AND FUTURE WORKS

This Chapter concludes this thesis and a summary of the research and the

contribution of the thesis are mentioned. In this Chapter, the future work that can be

extended to this research is also suggested and discussed.

5.1 Conclusion

This thesis suggests that a high-speed and highly efficient charge transfer circuit for

TOF range imaging is also available in standard CMOS technology by the use of a

very high gain negative feedback inverting amplifier circuit. A swift and efficient

charge transfer is made possible by the use of a very high gain inverting amplifier

and at the feedback there are capacitors connected alternatively. For that, different

types of CMOS amplifiers which are the Two-Stage OPAMP, Folded Cascode,

Telescopic and Cascode Amplifiers are compared and analyzed in terms of CTE,

when used in time of flight TOF range pixels. All these types of amplifiers are

simulated and analyzed. Through our analysis it is found that the Cascode and

Folded Cascode Amplifier has a highest gain and minimum dissipated power which

are best suited for Time of Flight (TOF) imaging pixels. Analyses on CTE has

shown that a high gain amplifier is necessary to obtain a nearly 100% efficient

charge transfer.

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Two Active TOF Pixels using the Cascode and the Folded Cascode amplifiers are

designed and simulated for this work and these are called the CMOS Active Pixel

Time of Flight (TOF) range image sensor. Signal charge are integrated on a

Photodiode (PD) and quickly separated into two feedback capacitors connected by

switches that is modulated to the TOF operating frequency. Computer simulations

show that charge injection from the feedback switches degrades output linearity.

Dummy switches of the same size as feedback switches are necessary to cancel the

effects of the charge injection. Folded Cascode Amplifier with second stage i.e. Gain

Boosting has been analyzed too and during analysis it is found that by adding the

second stage probably caused non linearity, which results in non-linearity, when

used in the Active TOF Pixels.

The results conclude that the Cascode Amplifier is the most suitable amplifier when

used in the Active TOF Pixel due to its high gain which is 131.28dB, low power

consumption such that 1.32µW and circuit simplicity. The CTE of Cascode

Amplifier is approximately 95.082% is enough for time delay dependent charge

separation required for TOF range imaging. The design is totally CMOS compatible

due to the fact that all of the components used are of standard CMOS circuit building

blocks.

5.2 Limitations and Future Work

There are some limitations accomplishing this research. One of the most important

limitations of this design is the use of higher supply voltage, because lowering the

voltage causing the low gain, which is not suitable for Active TOF pixel. By using

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the low voltage, it is difficult to Cascode more transistors that’s why it is impossible

to get high gain with small number of transistor in Cascode.

The future research to this work would concentrate in gain improvement and

fabrication of the Active Cascode Amplifier TOF Pixel.

5.3 Benchmarking

A highly efficient charge transfer circuit for TOF range imaging is also available in

standard CMOS technology by the use of a very high gain amplifier circuit. In

literature the Active TOF pixel is designed by using the Cascode amplifier as an

active element having a gain of 116dB and with the bias current of 0.4μA (Kawahito

& Halin, 2004). But in this case different types of CMOS amplifiers like Two-Stage

OPAMP, Folded Cascode, Telescopic and Cascode amplifiers are compared and

analyzed in terms of CTE, when used in time of flight TOF range pixels. Through

our analysis it is found that the Cascode amplifier has a highest gain which is

131.28dB as compared to previously designed amplifiers having the efficiency of

95.082 % and is best suited for Time of Flight (TOF) imaging pixels.

Moreover, Active TOF Pixels using Folded Cascode amplifier is also designed and

simulated. Signal charge are integrated on a PD and quickly separated into feedback

capacitors connected by switches that are modulated to the TOF operating frequency.

Computer simulations show that charge injection from the feedback switches

degrades output linearity. Dummy switches of the same size as feedback switches

are necessary to cancel the effects of the charge injection. Folded Cascode amplifier

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with second stage i.e. Gain Boosting has been analyzed too and during analysis it is

found that by adding the second stage probably caused propagation delay, which

results in non-linearity, when used in the Active TOF Pixels.

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REFERENCES

Allen, P. E., Holberg, D. R., CMOS Analog Circuit Design, Oxford University Press, USA, 2002. Arora, R. K., (1976). Charge coupled devices – Basic operation and principle. Microelectronics Reliability, Vol. 15, Issue 5, pp: 475-483. Baker, R. J., CMOS Circuit Design, Layout, and Simulation, Revised Second Edition. Wiley-IEEE Press, 2007. Bigas, M., Cabruja, E., Forest, J., Salvi, J., 2006, Review of CMOS image sensors, Microelectronics Journal, pp. 433-451. Boyle, W.S., Smith, G. E., (1970). Charge coupled semiconductor devices. Bell Sys. Tech. J., vol. 49, pp: 587-583. Blanc, N., CCD vercus CMOS has CCD imaging come to an end?, Photogrammetric week01, 2001 Wichmann verlag. Heidelberg. Brockhaus, ‘Naturwissenschaften und Technik’, Bd. 3, ISBN 3-7653-0450-6, Mannheim, (1989). Catrysse, P. B., The Optics of Image Sensors, Stanford University, June 2003. Calizo, I. G., Reset Noise Image Sensor, San Jose State University, 2005. Creath, K., “Phase-Measurement Interferometry Techniques”, Progress in Optics, Vol. XXVI, E. Wolf (Ed.), Elsevier, 1988 Din, A. U. et al., Photo Charge Transfer Efficiency of CMOS Amplifiers for Time of Flight (TOF) range imaging, Conference on Engineering and Technology Education. WEC2010 2-5th August 2010, Kuching, Sarawak, Malaysia. Euro Practice, 2010 a, Retrieved 25 December, 2010 from http://www.europracticeic.com/technologies_TSMC.php?tech_id=018um Euro Practice, 2010 b, Retrieved 25 December, 2010 from http://www.europractice-ic.com/libraries_TSMC.php Galilei, G., Discorsi e dimostrazioni matematiche, intorno a due nuove scienze atteninti alla mecanica & i movimenti locali, Leyden, at the Elzeviers, 1638. Gulati, K. and Lee, H., (1998). A High-Swing CMOS Telescopic Operational Amplifier, Solid-State Circuits, IEEE Journal of solid State Circuits, pp. 2010-2019.

90  

Gulati, K. and Lee, H., (2000). Corrections, A High-Swing CMOS Telescopic Operational Amplifier, Solid-State Circuits, IEEE Journal of Solid State Circuits, p p. 129-129. Guo, J., CMOS Image Sensors for Scientific Imaging Application and Implementation of Portable Electronic Nose, Tufts University, 2009. Hynecek, J., (1997). Low Noise and High Speed Charge Detection in High Resolution CCD Image Sensors, IEEE Transactions on Electron Devices, Vol. 44, No. 10. Halin, I. A. A study on CMOS time of flight Range Image sensors, Shizuoka University, 2006. Hoffmann, B., Ideen, E., Verlag, S. A. (1997), translation of: Relativity and Its Roots, Scientific American Books, New York. Kawahito, S. Distance Image Sensor, United States Patent, 14 October, 2008. Kawahito, S., Halin, I. A., (2004). Design of a Charge Domain CMOS Time-of-Flight Range Image Sensor, IEICE transactions on Electronics, 4. Vol.E87-C No.11: pp.1889-1896. Kawahito, S., et al., (2007). A CMOS Time-of-Flight Range Image Sensor with Gates on Field Oxide Structure, IEEE Sensors Journal, Vol. 7, No. 12. Kawahito, S., (2007). CMOS Imaging Devices for New Markets of Vision Systems. IEICE Transactions on Electronics, Vol.E90-C No.10: p. pp.1858-1868. Kawahito, S. and Halin, I. A., Active pixel circuits for CMOS time-of-flight range image sensors, Three-Dimensional Image Capture and Applications VI. Proc. of SPIE-IS&T Electronic Imaging, SPIE Vol. 5302, 2004. Keller, M. and Kolb, A., (2009). Real-time simulation of time-of-flight sensors, Simulation Modelling Practice and Theory, pp. 967-978. Lange, R., Seitz, P. A., Biber and Lauxtermann, S., Demodulation Pixels in CCD and CMOS Technologies for Time of Flight Ranging, Proc. SPIE, Vol. 3965A, pp.177-188, San Jose, January 2000. Lange, R., 3D Time-of-Flight Distance Measurement with Custom Solid-State Image Sensors in CMOS/CCD-Technology, Ph.D. Thesis., University of Siegen, 2000. Moore, G. (1965). Cramming more components onto integrated Circuits. Electronics Journal. vol.38, no. 8, pp.114–117.

91  

Miyagawa, R. and Kanade, T., CCD-Based Range-Finding Sensor, IEEE Trans. Electron Devices, Vol. 44, No. 10, pp. 1648-1652, October 1997. Niclass, C.L., et al. A CMOS single photon avalanche diode array for 3D imaging, IEEE International Solid-State Circuits Conference, 2004. Digest of Technical Papers. San Francisco, CA, 2004. Ohta, J., Smart CMOS image sensors and application, Taylor and Francis Group, 2007. Palakodety, A., CMOS Active Pixel Sensors for Digital Cameras: Current State-of-the-Art, University of North Texas, 2007 Penrose, R., The Road to Reality: A Complete Guide to the Laws of the Universe. Vintage Books, 2004. Razavi, B., Design of Analog CMOS Integrated Circuits, McGraw-Hill Science, 2002. Sansoni, G., et al., (2009). State-of-The-Art and Applications of 3D Imaging Sensors in Industry, Cultural Heritage, Medicine, and Criminal Investigation, Sensors Journal, pp: 568-601 Sedra A. S. and Smith, K. C., Microelectronic Circuits. Oxford University Press, New York, 2004. Suat. U. Ay., Electrical Property Modelling of Photodiode Type CMOS Active Pixel Sensor (APS), IEEE/IET Electronic Library (IEL), VDE VERLAG Conference Proceedings, Vol. 1, pp. 371 – 375, August 2005. Spring, K. R., Fellers, T. J. and Davidson, M. W., Introduction to Charge-Coupled Devices (CCDs), 2010. Strand, T., Optical three-dimensional sensing for machine vision, SPIE’s Optical Engineering, Vol. 24 (1), pp. 33-40, (1985). Teizer, J., (2008). 3D Range Imaging Camera Sensing for Active Safety in Construction, ITcon Vol. 13. Pp: 103-117. Theuwissen, A. J. P., CMOS or CCD Image Sensor for Consumer Digital Still Photography?, IEEE Proceedings of Technical Papers, invited paper, Proc. VLSI-TSA Symposium, Hsinchu, Taiwan, 2001. Upendranath, V., Smart CMOS Image Sensor for 3D Measurement, DIT - University of Trento, 2005.

92  

Waltari, M., Circuit Techniques for Low-Voltage and High-Speed A/D Converters , Helsinki University of Technology, 2002. Wikipedia, May 2011. The free Encyclopedia, Retrieved 16 July, 2011 from http://en.wikipedia.org/wiki/Phase_margin Xiao, F., DiCarlo, J. M., Catrysse, P. B., Wandell, B. A., Image Analysis using Modulated light Sources, In SPIE proceeding of Sensors and Camera Systems for Scientific, Industrial, and Digital Photography Applications II, Vol. 4306, pp.22-30, 2001. Yavari, M., (2005). Hybrid Cascode Compensation for Two-Stage CMOS Opamps, IEICE Transactions on Electronics, Vol.E88-C No.6: p. pp.1161-1165.

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BIODATA OF STUDENT

The researcher was born in Dera Ismail Khan, N-W.F.P, Pakistan on 12 May 1980.

He received his secondary and intermediate education from Government School and

Colleges of Dera ismail Khan, in 1996 and 1998, respectively. He obtained first

Class in BSc (Physics, Math A, B) in 2000 from native university i.e. Gomal

University, Dera ismail Khan, Pakistan and MSc Electronics in 2004 from one of the

highly reputable University of the country named Quaid-i-Azam University,

Islamabad, Pakistan.

The researcher started his professional career in August 2005 as a Design Engineer

in Elektro Control Industries (pvt) Ltd, Islamabad, Pakistan and serves the

organization almost two years. After that he joined a local university as a Lecturer /

Incharge Electronics Lab in Department of Software Engineering/Computer

Sciences, Fatima Jinnah Women University, Rawalpindi, Pakistan in April 2007.

The researcher has taught Advanced Digital Electronics, VLSI, and Computing

System in the University.

In December 2008 the researcher enrolled in the Master of Science program in

Electrical and Electronics Engineering, Faculty of Engineering, Universiti Putra

Malaysia.

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LIST OF PUBLICATIONS

A. U. Din, I. A. Halin, S. B. Shafie, ‘A Review on Solid State Time of Flight (TOF)

Range Image Sensors’, IEEE Student Conference on Research and Development (IEEE-SCOReD 2009),(Published).

A. U. Din, I. A. Halin, I. b. Aris, M. Bt. Mohd. Isa, ‘Efficient Charge Transfer

CMOS Amplifiers for low illumination Time of Flight (TOF) Imaging Pixels’, A poster presentation at Asia-Pacific Symposium on Applied Electromagnetic and Mechanics 2010, 28 - 30 July 2010.

A. U. Din, S. B. Shafie, W. Z. b. W. Hasan, I. A. Halin, ‘Photo Charge Transfer

Efficiency of CMOS Amplifiers for Time of Flight (TOF) range imaging’, Conference on Engineering and Technology Education. World Engineering Congress 2010. 2-5th August 2010, Kuching, Sarawak, Malaysia.

A. U. Din, I. b. Aris, M. Bt. Mohd. Isa, S. Kawahito, I. A. Halin, ‘Selection of

amplifier for optimized charge transfer in active pixel CMOS time of flight (TOF) image sensors’ Journal of Elex IEICE, 2011, (Submitted)