design of vlsi circuits and systemsicslwebs.ee.ucla.edu/dejan/classwiki/images/6/63/lec-01... ·...

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EE M216AFall 2010

Design of VLSI Circuits and Systems

Prof Dejan MarkovićProf. Dejan MarkovićUniversity of California, Los Angeles, USA

Email: [email protected]

Course Description

This course focuses on advanced concepts of VLSI circuit and system design in state‐of‐the‐art CMOS technologies.

Topics include:Topics include:– Circuit‐level optimization using gate size, supply and threshold voltage;

layout of circuit blocks optimized for speed, power, or area. – Advanced concepts of retiming, place and route will be employed in class

projects, in addition to the design of custom blocks. – The applications include micro‐processors, signal and multimedia

processors, portable devices, memory and periphery. Course topics are continuously updated to track unique technological

D. Markovic / Slide 2

– Course topics are continuously updated to track unique technological features such as power leakage, interconnect, clock and power distribution, impact of device variability on the design.

– This quarter, special focus will be given to design optimization and scaling.

EEM216A .:. Fall 2010 Lecture 1: Introduction | 2

2

EE115C vs. EEM216A

EE115C (introductory material)– Basic transistor and circuit models– Basic circuit design styles and logic gates– Design of custom blocks (adders, memories,…)g ( , , )

EEM216A (advanced material)– Transistor models of varying accuracy– Design under constraints: power, area, performance, robustness– More advanced design techniques– Learning challenges in the coming years


– Creating new solutions to challenging design problems


Class Topics

Fundamentals– Technology and modeling– Scaling and limits of scaling

Design for nano‐scale CMOSDesign for nano scale CMOS– Static CMOS, transistor sizing, buffer design, high‐speed CMOS design styles,

(dynamic logic)– Process variations, leakage

Design techniques for low power and low voltage– Power minimization at technology, circuit, architecture levels– Energy‐delay optimization

i h i i i


Arithmetic circuitsSystem‐level issues– Timing strategies, logic synthesis– Clock and power distribution– Physical design


3

Teaching Staff

Instructor– Prof. Dejan Marković– Office hours

T & Th 10 30 11 45● Tu & Th 10:30‐11:45am● 56‐147E Eng‐IV Bldg.

– Email: [email protected] TA– Fang‐Li Yuan

ReaderTBD


– TBDAdmin– Kim H– Office: 56‐127CC Eng‐IV


Class Material

Textbook:– J. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits:

A Design Perspective, (2nd Edition), Prentice Hall, 2003.

Other books:Other books:– N. Weste, D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective,

(3rd Edition), Addison Wesley, 2004. – A. Chandrakasan, W. Bowhill, F. Fox, Design of High‐Performance

Microprocessor Circuits, IEEE Press, 2001. – W.J. Dally and J.W. Poulton, Digital System Engineering, Cambridge

University Press, 1998. – B. Wong, A. Mittal, Y. Cao, G.W. Starr, Nano CMOS Circuit and Physical


g, , , , yDesign, Wiley‐Interscience, 2004.

Selected papers:– Available on classwiki

● Linked from IEEE Xplore (http://ieeexplore.ieee.org)(need to be logged in to a campus machine)


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Other Sources

Core material– IEEE Journal of Solid‐State Circuits (JSSC)– IEEE International Solid‐State Circuits Conference (ISSCC)– European Solid‐State Circuits Conference (ESSCIRC)p ( )– Symposium on VLSI Circuits (VLSI)– Custom Integrated Circuits Conference (CICC)– Other conferences and journals

CAD topics– International Conference on Computer Aided Design (ICCAD)


– Design Automation Conference (DAC)


Class Organization & Grading

Grading:– Homeworks (4) 15%– Labs (2) 4%– Project 30%j– Midterm 25%– Final exam 25%– Course survey 1%

Class project

Phase‐1 Final PPTPhase‐2

1Week 2 3 4 5 6 7 8 9 10 11

D. Markovic / Slide 8EEM216A .:. Fall 2010

H1 H2 H3 H4

M

Fri10/8

Mon10/18

Fri10/29

Fri11/12

Wed11/3

Lecture 1: Introduction | 8

F

Fri12/10

SL1

Mon11/22

L2

Fri11/26

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Class Website

EEweb: grades onlyClasswiki: notes, handouts, assignments, CAD tools, references, …

classwiki

D. Markovic / Slide 9EEM216A .:. Fall 2010 Lecture 1: Introduction | 9

Classwiki

Create an account: use your UCLA username!


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Homework #0 / Action Items

Get an EE account (if you haven’t already)

Sign up for classwikiUse your ee/seas username to sign up– Use your ee/seas username to sign up

– Once you sign up, I need to add you to ee216a group

Server and CAD tool info is on the wiki


CAD Tools

Cadence & Synopsys software− Phased out Electric software− Online documentation and tutorials

90nm CMOS technology − Cadence gpdk090 & gsclib & Synopsys generic 90nm library− 9 metal layers

Important tools / skills from EE115C


− Design Capture: Virtuoso Schematic / Layout Editor− Circuit Simulation: Spectre / Ocean− Design Verification (DRC, LVS, Extraction): Assura/Diva/QRC


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EEM216A Goals

Understanding the basic building blocks of VLSI– Transistors/Wires– Logic Gates and Layout– Datapath Blocksp

Be able to conceptually model a system– Logic Optimization– State Machine Design (RTL)

Be able to build a system (using a subset of the tools)– Verilog Modeling– Synthesis


– Place and Route

Understanding the constraints and tradeoffs– Delay analysis (gates and interconnects)– Clocking methodology– System integration issues (Power/Ground routing, Noise)


EE M216A .:. Fall 2010Lecture 1

Digital Integrated Circuit Design:

Trends and Challenges

Prof. Dejan Marković[email protected]

8

Moore’s Law

In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months

He made a prediction that semiconductor industry will double itsHe made a prediction that semiconductor industry will double its effectiveness every 18 months

“The complexity for minimum component costs has increased at a rate of roughly a factor of two per year. Certainly over the short term, this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit


[G. Moore, Electronics, 1965]

more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years. That means by 1975, the number of components per integrated circuit for minimum cost will be 65,000.”

Moore’s Law – 1965


9

Moore’s Law – 2005


Evolution in Complexity


10

Microprocessor Examples

M ’ lMoore’s law− Number of transistors− Logic density− Die size− Frequency− Power


#1: Number of Transistors

Transistors on lead microprocessors double every 2 years

1000

2X growth in 1 96 years!

80808085 8086 (P1)

286 (P2)386 (P3)

486 (P4)Pentium® (P5)

Pentium Pro (P6)

0 01

0.1

1

10

100

Tran

sist

ors

(MT)

2X growth in 1.96 years!

Source:

Pentium 4


40048008

8080

0.001

0.01

1970 1980 1990 2000 2010Year

S. Borkar(Intel)

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#2: Logic Density

Shrinks and compactions meet density goals− New micro‐architectures drop density

1000

Pentium (R)Pentium Pro (R) 486

38610

100

Logi

c D

ensi

ty2x trend

gic

Tran

sist

ors/

mm

2

Pentium II (R)


i860

1

1.5µ

1.0µ

0.8µ

0.6µ

0.35

µ

0.25

µ

0.18

µ

0.13

µ

Log Source: Intel

#3: Die Size Growth

Die size grows by 14% to satisfy Moore’s law

100

40048008

80808085

8086286

386486 Pentium ®

Pentium Pro

10

Die

siz

e (m

m)

~7% growth per year~2X growth in 10 years Source:

S B k


4004

11970 1980 1990 2000 2010

Year

2X growth in 10 years S. Borkar(Intel)

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#4: Frequency

Lead microprocessor frequency doubles every 2 years

10000

Pentium ProPentium ®

48638628680868085

8080

10

100

1000

Freq

uenc

y (M

hz)

Doubles every2 years

Source:

Pentium 4


8080800840040.1

1

1970 1980 1990 2000 2010Year

F Source:S. Borkar(Intel)

Processor Frequency Trend

Frequency doubles each generation− Number of gates/clock reduce by 25%

10 000 100

Pentium Pro(R)

Pentium(R) IIMPC750

604+604

21264S

2126421164A

2116421064A

21066

100

1,000

10,000

Mhz 10

100

ate

Del

ays/

Clo

ck

Intel

IBM Power PC

DEC

Gate delays/clock

Processor freq scales by 2X per

generation Game over!


386486

Pentium(R)(R)601, 603

10

100

1987

1989

1991

1993

1995

1997

1999

2001

2003

2005

1

G

Source:V. De, S. BorkarISLPED’99

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Technology Roadmap (2002)

International Technology Roadmap for Semiconductors (ITRS)

Year 2001 2003 2005 2007 2010 2013 2016

DRAM ½ pitch [nm] 130 100 80 65 45 32 22

MPU transistors/chip 97M 153M 243M 386M 773M 1.55G 3.09G

Wiring levels 8 8 10 10 10 11 11

High-perf. phys. gate [nm] 65 45 32 25 18 13 9

High-perf. VDD [V] 1.2 1.0 0.9 0.7 0.6 0.5 0.4

Local clock [GHz] 1.7 3.1 5.2 6.7 11.5 19.3 28.8

High-perf. power [W] 130 150 170 190 218 251 288


Node years: 2007/65nm, 2010/45nm, 2013/32nm, 2016/22nm

Low-power phys. gate [nm] 90 65 45 32 22 16 11

Low-power VDD [V] 1.2 1.1 1.0 0.9 0.8 0.7 0.6

Low-power power [W] 2.4 2.8 3.2 3.5 3.0 3.0 3.0

Technology Scaling

100 x1.4 / 3 years1000 ∝ κ 0.7

ISSCC data

0.1

1

10

Pow

er D

issi

patio

n (W

)

x4 / 3 year

s

MPU

10

100 ∝ κ 3

Pow

er D

ensi

ty (m

W/m

m2 )


(a) Power dissipation vs. year.

959085800.01

Year

DSP

Scaling Factor κ （normalized by 4µm design rule）

1011

P

(b) Power density vs. scaling factor.

Source: T. Kuroda

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New Trend: Parallel Hardware

Higher logic throughput, yet lower power

Freq = 1Vdd

Logic BlockFreq = 1Throughput = 1Active Power = 1SD Lkg Power = 1

Logic Block Freq = 0.7

0.7 x Vdd


g qThroughput = 1.4Active Power = 0.7SD Lkg Power = 0.7

Logic BlockSource:S. Borkar(Intel)

Dual Core

Voltage Frequency Power Performance

1% 1% 3% 0.66%

Rule of thumb

Core

Cache

Core

Cache

Core

V lt 1 V lt 15%

In the same process technology…


Voltage = 1Freq = 1Area = 1Power = 1Perf = 1

Voltage = ‐15%Freq = ‐15%Area = 2Power = 1Perf = ~1.8

Source:S. Borkar(Intel)

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Future Multi‐core Platform

Heterogeneous Multi‐Core Platform—SOC

GP GP

GP

GP GP

GP

GP

GP GP

GP

GP GP

General Purpose Cores

SP SP

SP SP

Special Purpose HW

CC

CC

CC

CC

CC

CC

CC

CC Interconnect fabric


GP GP GP GPCCCC Interconnect fabric


Software Challenge


Source: ITRS 2007


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Impact of Process Variations

130nm data (getting worse with scaling)

1.4y


30% FrequencyFrequency~30%~30%

LeakageLeakagePowerPower~5~5‐‐10X10X

1 0

1.1

1.2

1.3

orm

aliz

ed F

requ

ency


5X

0.9

1.0

1 2 3 4 5Normalized Leakage

No

Implications

Reliability– Extreme variations (Static & Dynamic) will result in unreliable

componentsImpossible to design reliable system as we know today– Impossible to design reliable system as we know today● Transient errors (Soft Errors) ● Gradual errors (Variations)● Time dependent (Degradation)

Test– One‐time‐factory testing will be out



One time factory testing will be out– Burn‐in to catch chip infant‐mortality will not be practical– Test HW will be part of the design– Dynamically self‐test, detect errors, reconfigure, & adapt


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In a Nut‐shell…

100

100 BT integration capacity

Billions unusable (variations)

100 Billion

Transistors

Some will fail over time

Intermittent failuresSource:S. Borkar(Intel)


Yet, deliver high performance in the power & cost envelope…


( )

Parallel Data Processing

Power limited technology scaling– Increased impact of process variations– More leakage power, multiple threshold devices

Single dimensional Multidimensional data

Multi-core Processors MIMO Communications Neuroscience


www.sci.utah.eduIBM / Sony / Toshiba Belkin

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Energy‐Delay Optimization

Same principle, different optimization goals

ProcessorsM i i f V scalingy− Maximize performance

− Highest VDD required

Communications− Minimize energy & area− Typically, sensitivity ~ 1

VDD scaling

Communications

Ener

gy

Neural

Processors


Neuroscience− Power density: 0.8mWmm2

− Aggressive VDD scaling


0 Delay

ASICs on The Road to Extinction?


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The Age of Concurrency and Flexibility

Xilinx Vertex 4

Intel Montecito

HeterogeneousHeterogeneousreconfigurablereconfigurable

fabricfabric

HeterogeneousHeterogeneousreconfigurablereconfigurable

fabricfabric

UCB Pleiades

C t

ARMARMARMARM

AMD DualCore

Courtesy: J. Rabaey (UCB)


IBM/Sony Cell ProcessorIBM/Sony Cell Processor

NTT Video codec(4 Tensilica cores)


FPGAs going Multi‐core…

BEE2 compute module

14”x17” 22 layer PCB


Courtesy:J. Wawrzynek (UCB)


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Moore’s Law and the Long Term

What level?


1965 2005

Moore’s Law and the Long Term

What level?

Within your working life?


When?1965 2005?

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Silicon Technology Reaches Nanoscale

Source: Intel


Sub‐wavelength Optical Lithography


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Scaling Toward 10 nm Node

Bulk/SOI CMOS Multi‐gate CMOS Post‐Silicon

5 nm

22nm45nm

65nm

32nm16nm

12nm

5 n m5 n m


Technology: scaling, alternative structures and materials, post‐silicon devices

Design: billion transistors, GHz operation

EEM216A .:. Fall 2010

Source:K. Cao(ASU)


Design of Nanoelectronics

[TI]

???Carbon Nanotube

FET

1948 1958

1993 2006

[IBM]


1993 2006


[UCB] Coming soon

2008 2010

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Moore’s Law Challenge

Double transistors every two yearsStay within the expected power trendStill deliver the expected performanceP li it d li iPower‐limited scaling regime

Two key issues:– Design complexity– Power efficiency


Looking at solutions to these challenges iswhat this course is all about!


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