design&implementationofparalleloperationof...

Design & Implementation of Parallel Operation ofInverters with Instantaneous Current Sharing SchemeUsing Multiloop Control Strategy on FPGA Platform

A thesis submittedin partial fulllment of the requirements

for the degree ofMaster of Technology

byShahil Shah

to theDepartment of Electrical Engineering

Indian Institute of Technology, Kanpur

July 2008

Certicate

This is to certify that the work contained in the thesis entitled Design &Implementation of Parallel Operation of Inverters with Instantaneous Current SharingScheme Using Multiloop Control Strategy on FPGA Platform, by Shahil Shah, hasbeen carried out under my supervision and that this work has not been submittedelsewhere for a degree.

July 2008 (Dr. Partha Sarathi Sensarma)Department of Electrical Engineering,Indian Institute of Technology,Kanpur.

Tomy dear

Mummy-Papa

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AbstractIn these days of acute shortage of conventional energy resources, the harness of

renewable energy has received considerable attention. In general, power obtained fromRenewable Energy Sources(RES) is not of the form which is directly deliverable to theAC load or the utility grid. Voltage Controlled Voltage Source Inverters (VCVSI) formsthe interface link which conditions power to the form deliverable to grid or load. Tomodularize the system, instead of a single inverter, the use of number of parallel invertersof reduced rating is proposed. The parallel operation of inverters in RES system oersadvantages like reliability and redundancy in addition to the low maintenance cost ofa low power unit compared to that of high power unit. However there is a need ofcontrol strategy to strictly hold the amplitude, phase and frequency of output voltagesof inverters at the same values in order to avoid circulating currents through invertermodules and make them share load currents equally even during transients.

In this thesis work a control scheme is proposed and implemented for paralleling ofthree phase inverters which enables the inverters to share load currents equally evenduring transients (instantaneous current sharing), and also track the sinusoidal voltagereference. This voltage reference is either free running or is derived from grid voltage soas to feed AC load or to synchronize the module with any utility grid. The design issuesfor designing of multiloop control structure are analyzed at length with the discussionof active damping to increase the damping and relative stability of system. Design ofouter current sharing controller has been done and its design intricacies are included inthe work.

FPGAs can be used to control power electronic systems. They have advantages likehigh speed, parallel processing capability, and rich digital I/O interface. In this thesis,basic modules required for development of controllers for power electronic systems aredeveloped and tested with standard signals. The proposed control scheme for paralleloperation is implemented for two 3-phase inverters using this FPGA platform.

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AcknowledgementI take this opportunity to express my sincere gratitude to my supervisor Dr. Partha

Sarathi Sensarma for his invaluable guidance. It would have never been possible for meto take this project to completion without his innovative ideas and his relentless supportand encouragement. I consider myself extremely fortunate to have had a chance to workunder his supervision. In spite of his hectic schedule he was always approachable andtook his time o to discuss my problems and give his advice and encouragement. It hasbeen a very learning and enjoyable experience to work under him.

I acknowledge the infrastructure support provided by Ministry of Communication andIT, Government of India, through CDAC, Trivendrum under the NAMPET project.

My special thanks to my friends in lab Samir, Sabarish, Suresh, Madan, Anindya,Poonam and Prachi for their invaluable help, suggestions and support during the courseof my thesis. I specially thank my juniors Kapil and Lalit for helping me in performingexperiments. I thank to my senior Jyotheeswar Reddy for his invaluable suggestions.

I express my deep gratitude towards Prakash, Ritesh and close friends for makingmy stay at IIT kanpur an unforgettable experience of my life.

I like to thank all the faculty members of the Department of Electrical Engineeringfor the invaluable knowledge they imparted to me during course work and for teachingthe principles in an exciting and enjoyable way.

I would like to thank Mr. Kole for his enthusiastic support for PCB fabrication anddesign. I would like to thank Mr. Tiwari of the department workshop for their assistancein fabrication of various components needed for the thesis. I specially thank here Mr.Amit Basu for his enthusiastic support, in providing infrastructural support wheneverI needed. I would like to thank Mr. Salman Khan for his support in fabrication ofinductors.

I express my deep sense of reverence and gratitude to my parents, brother and familymembers without whose love, aection and blessings I wouldn't have reached this stage.

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List of Figures

1.1 (a) Frequency and (b) voltage droop characteristics. . . . . . . . . . . . . 71.2 Distributed Generation Conguration of Parallel Inverters. . . . . . . . . 101.3 Per phase schematic of Whole Control Strategy with Current Sharing

Control & DC Bus Control. . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1 PWM Inverter with LC Filter . . . . . . . . . . . . . . . . . . . . . . . . 122.2 Bode plot of typical LC lter . . . . . . . . . . . . . . . . . . . . . . . . 132.3 Bode plot of lter for 5kHz . . . . . . . . . . . . . . . . . . . . . . . . . . 162.4 Bode plot of lter for 10kHz . . . . . . . . . . . . . . . . . . . . . . . . . 172.5 Inductor current at rated load for 5kHz . . . . . . . . . . . . . . . . . . . 192.6 Capacitor current at rated load for 5kHz . . . . . . . . . . . . . . . . . . 192.7 Output Voltage of Filter at Rated Load for 5kHz . . . . . . . . . . . . . 20

3.1 Single Phase Equivalent of Inverter with LC Filter . . . . . . . . . . . . . 223.2 Bode plot of lter for 5kHz . . . . . . . . . . . . . . . . . . . . . . . . . . 253.3 Possible positions of damping resistors . . . . . . . . . . . . . . . . . . . 263.4 Equivalent circuit with active damping . . . . . . . . . . . . . . . . . . . 283.5 Bode Magnitude plot with and without active damping . . . . . . . . . . 293.6 Per phase schematic of Voltage Control Loop. . . . . . . . . . . . . . . . 323.7 Typical representation of close loop system. . . . . . . . . . . . . . . . . 343.8 Bode Plots of Sensitivity Transfer Function for dierent controllers. . . . 373.9 Bode Plots of Loop Transfer Function with Controllers & Active Damping. 373.10 Bode Plot of Loop Transfer Function with Robust PI Controller & Active

Damping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

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3.11 Calculated response for Output phase voltages with optimized PI VoltageController and kc = 3Ω. Nominal parameters are considered. . . . . . . . 38

3.12 Simulated response for Output phase voltages with optimized PI VoltageController and kc = 3Ω. Transients in load and reference are simulatedto show their eects on output voltage. Nominal parameters are used. . . 39

3.13 Simulated response for Output phase voltage with optimized PI VoltageController and kc = 3Ω. Transients in load and reference are simulatedto show their eects on output voltage. Perturbed parameters are used. . 39

3.14 Bode Plot of Loop Transfer Function with Controller & Active Damping. 403.15 Calculated Response of Plant to 50Hz sinusoid . . . . . . . . . . . . . . . 413.16 Output phase voltage waveform with Voltage Controller. Transients in

load and reference are simulated to show their eects on output voltage.(b) shows the eect of reduced damping on Phase-A voltage. . . . . . . . 42

3.17 Modulation Signal with Carrier Wave . . . . . . . . . . . . . . . . . . . . 443.18 Bode Plot of Zero Order Hold(ZOH) . . . . . . . . . . . . . . . . . . . . 453.19 Block Diagram of Inner Loop with Compensation for ZOH phase Delay

in Active Damping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.1 Per phase schematic of Whole Control Strategy with Current SharingControl & DC Bus Control. . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.2 Bode Plot of Close Loop Transfer Function of VCVSI. . . . . . . . . . . . 494.3 Block diagrammatic representation of multi-inverter system with current

sharing controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504.4 Isolated perturbation model of any inverter in multi-inverter system. . . . 514.5 Output Currents from three phases of two inverters superimposed on

each other - Shows sharing during load transient at t = 0.04sec and t =0.06sec - Load Resistance decreased by 80% at t=0.04 and again restoredat t=0.06. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.6 Waveform of Correction ∆V for Instantaneous Current Sharing - Containsfrequency components up to 1500Hz. . . . . . . . . . . . . . . . . . . . . 52

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4.7 DC link voltage Vdc response to step reference of 380Volts at t = 0.1secand corresponding DC bus current Idc delivered. . . . . . . . . . . . . . . 54

4.8 Waveform of Correction ∆E for DC bus voltage control - Contains mostlyfundamental frequency component (50Hz). . . . . . . . . . . . . . . . . . 55

5.1 Layout diagram of test setup of parallel inverters with LC lter. . . . . . 585.2 Reference(red) and Output Voltage(blue) for phase-A and kc = 3Ω. . . . 595.3 Step response to application of reference. . . . . . . . . . . . . . . . . . . 605.4 (a) Output Voltage(50V/div) (b) Load Current(5.55A/div). . . . . . . . 605.5 (a) Phase-A Capacitor current(0.44 Amp/div) (b) FFT(5kHz/div). . . . 615.6 (a) Phase-A Capacitor current(2.22 Amp/div) (b) FFT(250Hz/div). . . . 625.7 Output Voltage without active damping(50 V/div). . . . . . . . . . . . . 625.8 Step response of 2nd order voltage controller(50 V/div). . . . . . . . . . 635.9 Reference(red) and Phase-A Voltage(50 V/div)(blue) without load. . . . 645.10 Reference(red) and Phase-A Voltage(50 V/div)(blue) with load. . . . . . 645.11 Load Current - phase A(1.2 Amp/div). . . . . . . . . . . . . . . . . . . . 655.12 Three phase output Voltages. . . . . . . . . . . . . . . . . . . . . . . . . 655.13 (a) Voltage dierence between two VCVSI outputs running on synchro-

nized reference(2.50 V/div) (b) FFT(500mV/div, 50Hz/div). . . . . . . . 675.14 (a) Voltage dierence between two VCVSI outputs running on synchro-

nized reference(2.50 V/div) after inclusion of correction voltage (b) FFT(100mV/div,50Hz/div). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.15 Current sharing during switching on of load(1.5Amp/div). . . . . . . . . 685.16 Current sharing during load transients(1.5Amp/div). . . . . . . . . . . . 69

6.1 FPGA Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 736.2 Control Implementation in FPGA . . . . . . . . . . . . . . . . . . . . . . 76

A.1 PI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

B.1 Experimental Setup for parallel inverters with LC lter . . . . . . . . . . 89B.2 Altera Cyclone-I FPGA kit with Interface card . . . . . . . . . . . . . . . 89

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B.3 Three phase LC lters for two inverters. . . . . . . . . . . . . . . . . . . 90B.4 ADC buer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92B.5 Power Supply portion circuit . . . . . . . . . . . . . . . . . . . . . . . . . 93

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List of Tables

2.1 LC Filter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1 Filter Parameters Used for Control Design . . . . . . . . . . . . . . . . . 253.2 Nominal Parameter Values for 3-phase Inverter and LC Filter . . . . . . 32

4.1 Perturbed Parameter Values of Two Inverters Used For Simulation . . . . 51

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Contents

1 Introduction 11.1 Requirements to Operate Inverters in Parallel . . . . . . . . . . . . . . . 31.2 Problems Associated with Parallel Operation of Inverters . . . . . . . . . 41.3 Control Strategies Available in Literature . . . . . . . . . . . . . . . . . . 5

1.3.1 Droop Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.3.2 Master-slave Control . . . . . . . . . . . . . . . . . . . . . . . . . 71.3.3 Instantaneous Current Sharing Methods . . . . . . . . . . . . . . 8

1.4 Thesis Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.5 Layout for Parallel Inverters fed from RES . . . . . . . . . . . . . . . . . 91.6 Organization of Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2 LC Filter Design 122.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.2 Filter Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.2.1 Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.2.2 Resonant Peak . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.2.3 Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3 Design of LC Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.3.1 For fs = 5kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.3.2 For fs = 10kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.4 Passive Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172.4.1 Calculation Of Harmonics Through Passives . . . . . . . . . . . . 18

2.5 Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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3 Modeling & Design of Multiloop Voltage Controller 213.1 Modeling of Plant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213.2 Damping of Resonant Frequency Oscillations . . . . . . . . . . . . . . . . 24

3.2.1 Passive Damping . . . . . . . . . . . . . . . . . . . . . . . . . . . 263.3 Active Damping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.3.1 Features of Active Damping . . . . . . . . . . . . . . . . . . . . . 293.4 Control Requirements for Inner Voltage Loop . . . . . . . . . . . . . . . 303.5 Multi-loop Inner Voltage Controller . . . . . . . . . . . . . . . . . . . . . 31

3.5.1 Robust Tuning of P-I Voltage Controller . . . . . . . . . . . . . . 323.5.2 High Bandwidth Second Order Voltage Controller Design . . . . . 40

3.6 Issues in Digitization of Controller . . . . . . . . . . . . . . . . . . . . . . 433.6.1 Selection of Sampling frequency . . . . . . . . . . . . . . . . . . . 433.6.2 Eect of Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . 43


4 Design & Stability Analysis of Instantaneous Current Sharing Loopand DC Bus Control 474.1 Design of Current Sharing Controller . . . . . . . . . . . . . . . . . . . . 48

4.1.1 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494.1.2 Simulation Results for Current Sharing . . . . . . . . . . . . . . . 51

4.2 DC Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534.2.1 Simulation Results for DC Bus Control . . . . . . . . . . . . . . . 54


5 Experimental Setup and Results 565.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.2.1 Robust P-I Controller . . . . . . . . . . . . . . . . . . . . . . . . 595.2.2 Active Damping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615.2.3 Second Order Voltage Controller . . . . . . . . . . . . . . . . . . 635.2.4 Synchronization of Inverters . . . . . . . . . . . . . . . . . . . . . 665.2.5 Instantaneous Current Sharing . . . . . . . . . . . . . . . . . . . . 68

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6 FPGA based Control and Implementation 706.1 Control Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

6.1.1 Analog platform . . . . . . . . . . . . . . . . . . . . . . . . . . . 716.1.2 Digital platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.2 Features of FPGA Board . . . . . . . . . . . . . . . . . . . . . . . . . . . 726.3 FPGA Modules for Power Electronics Applications . . . . . . . . . . . . 746.4 Implementation of Control System in FPGA . . . . . . . . . . . . . . . . 75

6.4.1 Selection of Base Values . . . . . . . . . . . . . . . . . . . . . . . 756.4.2 Sensor Gains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776.4.3 Per-unitization Block . . . . . . . . . . . . . . . . . . . . . . . . . 77

6.5 Serial and Parallel Implementations on FPGA . . . . . . . . . . . . . . . 786.6 Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

7 Conclusions 797.1 The Present Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797.2 Scope for Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

A Fixed Point Representation of Real Numbers 83A.1 Selection of Number Format . . . . . . . . . . . . . . . . . . . . . . . . . 83A.2 ADC Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85A.3 PI Controller Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

B Specications of Hardware Modules 88B.1 Protection Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88B.2 Interface Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

B.2.1 ADC Buer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91B.2.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91B.2.3 FRC Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

B.3 Voltage Sensor Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92B.4 Current Sensor Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

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References 95

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Chapter 1

Introduction

The non-availability of conventional energy resources in abundance and also the risingenergy demands has turned the attention of power sector industries towards eectiveutilization of non-conventional and renewable energy resources. The optimisation ofcosts has become an even more vital aspect of the electric energy provision. At thesame time, some technological advances have enabled that distributed and renewableenergy sources provide a growing part of the power supply. Environmental concernsare driving forward the accelerated growth of renewable technologies, some of whichare characterised by the variable nature of their resource. A last trend is the searchfor power quality and reliability of the supply adjusted to the customers needs. Thesetrends have important implications for the operation of the grid.

Renewable energy resources(RES) like solar, wind, bio-mass are not available roundthe clock to supply energy. Also the intensity of power available from such sourcesvaries with time at large. Power from RES is random in nature and unsuitable fordirect utilization by domestic consumer loads. Hence means are required to store theenergy available from RES during no load or light load condition and also to processthe power to a form suitable for grid or domestic AC load. Batteries are invariablyused to store energy from RES. Also the amount of power from single RES module isnot sucient to form grid and dierent RES modules delivers power during dierentperiods of time. This has motivated the idea of distributed generation. In distributedgeneration, dierent small power units are coupled and combined to form a micro-grid.This needs the operation of processing converters in parallel to supply power to common

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ac grid. The grid can be operated alongwith local utility grid or in island mode. Inisland mode, the distribution generation has to have battery back-up to meet the loaddemand in the absence of non-conventional energy.

Apart from being non-compatible with local grid, the amount of energy harnessedfrom RES varies with certain parameters. In Solar Photovoltaic(SPV) module, theamount of energy harnessed depends on the voltage at the terminal of the module,whereas the wind energy varies with the speed of wind turbine. Power electronic con-verters are used to vary dc voltage across the solar cell module, or to vary ac voltageat the terminal of induction generator used for wind turbine to extract the maximumpower. The Maximum Power-point Tracking(MPPT) algorithms require sti DC linkfor their operation[1]. Hence alongwith power processing unit, a DC link support is alsoneeded.

Inverters are predominantly used as interface link and to process power from RESand convert it to the form suitable for utility because of the control exibility theyprovide. Inverters convert power from dc to ac with controllable voltage and variablefrequency. For battery interface applications, inverters are used as bidirectional link tocharge batteries during power surplus periods and to discharge them in absence of powerfrom RES. Hence inverters take power from dierent modules and deliver it to commonac grid, which is either synchronized with local utility grid or is in islanded mode.

This requires the parallel operation of inverters along with sinusoidal voltage track-ing. Also parallel inverters can be used in place of one large single unit. The Paralleloperation of small inverters gives modularity to the system and provides extra relia-bility, redundancy and the power level of the plant can be upgraded without the needof complete reconguration. Increase in number of inverters increases the stiness ofthe system and makes it more stable against external disturbances. Hence the paralleloperation of inverters in RES system oers several advantages in addition to low mainte-nance cost of low power unit compared to that of high power unit. Also low power unitscan be switched at higher frequencies compared to large power units and provides morebandwidth for operation and better quality of power with less ltering requirements.However there is a need of control strategy to strictly regulate the amplitude, phase and

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frequency of output voltages of inverters to avoid circulating currents through invertermodules and make them share load currents equally even during transients. Apart fromparallel operation, a major problem is synchronization of these inverters while bringingthem in operation or getting them out of grid. As inverter forms a weak grid, the chancesof system getting unstable are very likely.

In this thesis work an attempt has been made to solve the problem of current sharingfor parallel operation with synchronized voltage tracking and DC link voltage control.The synchronization method for inverter is also designed and implemented.

1.1 Requirements to Operate Inverters in Parallel

The main appeal of parallel-connected inverter systems lies in their reliability and exi-bility, making them very attractive for the various demanding applications. The aim forreliability and exibility imposes the following requirements:

• The operation of parallel-connected inverters should be fault-tolerant and robust,requiring a truly redundant operation. Thus, the parallel inverters should notshare any critical control function. Controls of all inverters must be independentto each other.

• Load sharing between the inverters should be achieved without large-scale com-munication, as the need for communication infrastructure reduces both exibilityand reliability. Only information of load current can be used as common to allmodules.

• The system should be modular and easily expandable.

• The parallel-connected inverters should be able to operate both in parallel withthe grid as well as in an isolated system. The connection and disconnection of anisolated system with the mains occurs without communication with the parallel-connected inverters. Ideally, the inverters should not have dierent operatingmodes for grid-connected or island operation, thus eliminating the need for eachinverter to know the state of the grid section. Alternatively, if dierent modes for

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grid-connected and island operation are desired, each inverter should on its ownbe able to accurately detect whether the system is grid-connected or operating inislanded mode.

1.2 Problems Associated with Parallel Operation ofInverters

Various problems are associated with parallel operation of inverters, which have to beaddressed to meet the requirements mentioned in previous section. Distributed gener-ation has generally no back-up grid and also it is devoid of any xed reference voltagefor inverters. This requires to have a synchronised reference wave for the output voltageof all inverters. Also the inverters must share the active and reactive demand of loadequally during steady state as well as during dynamic variations in load. The switchesthat are generally used in inverters have very low overload capacity. Hence the correc-tive actions must be included in the control algorithm to limit switch currents in theevent of dynamic conditions like starting inrush current of induction motors or in faultyconditions like short circuit. This can be achieved by decreasing the output voltage ofinverters temporarily in the event of fault, to limit the current ow through switchesbelow specic level. Also the voltage of the standalone unit has to be controlled preciselywithin specied zone of declared value for proper operation of consumer loads. Synchro-nization must be maintained between various inverter units during steady state as wellas during dynamic conditions. This needs all inverters to be operated at same frequency.Connection of inverter module with other inverters(synchronization) and removal of in-verter from grid has to be done without undue transients in voltages and currents at theterminals of other inverters. This avoids the mal-operation of other inverter modules.Also the small voltage dierence in the output of inverters will give rise to large circulat-ing currents due to very low value of line impedances oered by the transformers(basiclayout shown in g.1.2. Hence some corrective mechanism is required to control thevoltage dierences by observing the current dierences between inverters. This can beachieved by observing the dierences between inverter currents from a common current

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reference and utilizing it to decrease them.Apart from problems associated with parallel operation of inverters, the DC bus

control has to be achieved without the need of any auxiliary converter. This requiresto control active power ow through inverter from ac side. All these requirements aresummarized below

• Synchronized reference for output voltage

• Equal sharing of active and reactive power

• Overload protection

• Strict voltage tracking

• Frequency of operation has to be maintained

• Synchronization with other inverters or grid

• Minimization of circulating currents

• DC bus control.

1.3 Control Strategies Available in Literature

The simplest method to connect inverters in parallel is to employ coupled inductorsat the output end of the inverters. The coupled inductors can reasonably balance theoutput currents of the individual inverter. However, such a bulky inductors greatlyincrease the size and cost of the system. In case the load current contains harmonics,the output voltage will also get distorted by the inductors. In addition, it is inconvenientto add more inverters to the system.

The technology to parallel multiple inverters has matured to an appreciable extent inpast two decades from simple employment of inductors to instantaneous current sharingcontrols. For operation of multiple inverters in parallel, various methods available canbe briey summed up into coupled inductors, droop control, current sharing control,master-slave control and virtual impedance emulation[2]-[11]. The droop methods [2]-[6]

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has an advantage that there is no need of control interconnections among inverters, butit cannot be applied to share harmonic components of load current. Master-slave method[7]-[8] employs one voltage controlled VSI acting as master and remaining (n-1) currentcontrolled VSIs as slaves which share equal currents. But the system has to be shutdown if master unit fails. With advent of new semi-conductor technologies, the responseof converters has become faster and therefore instantaneous current sharing schemeshave been proposed [9]-[11]. These schemes are based on nding the duty ratio of eachinverter instantaneously using a control mechanism to share the information of currentsshared by individual inverters. Even if the output current contains harmonics, it can beshared equally by inverters. Some DC bus voltage control methods using inverters arealso documented in literature[16][17].

Broadly the control for parallel operation of inverters is classied into two categories.viz.,

• Coupled or Centralized control

• De-coupled or Decentralized control

Various methods for paralleling multiple inverters are as described below.

1.3.1 Droop Method

Droop methods have an advantage that their controls do not rely on communicationbetween dierent inverter units. The peculiar aspect of these methods is that they onlyhave a proportional controller for frequency and voltage, lacking any form of integralor other control. Hence droop methods require less computing facilities and simplecheap micro-controllers can be used for their control purpose. Basically the principleof droop method depends upon the power equations applicable to any synchronousgenerator connected to the grid through impedence[3]. Voltage and frequency are decidedusing droop characteristics as shown in g.1.1. For two ac sources connected throughimpedance, the active power ow between them can be controlled by controlling theangle between their synchronously rotating voltage phasers and reactive power ow canbe controlled by controlling the magnitude dierence of their voltage phasers. Same

6

Figure 1.1: (a) Frequency and (b) voltage droop characteristics.

principle is being used to control the active and reactive power ow through invertersconnected to ac grid. For same active and reactive power ow as demanded by load, thevoltage and frequency at which they must operate is decided using droop characteristics.Also the slope of droop characteristic can be updated online to have adaptive droopcontrol[6].

Hence droop methods inherently introduce the voltage and frequency sag in thesystem. This deteriorates the voltage regulation and renders it useless where there is nosti grid to correct the voltage dips. Also, by droop method only active and reactivepower can be shared eciently by inverters. There will not be any control on sharing ofharmonic currents of load and also transients may hamper the reliability of this method.

1.3.2 Master-slave Control

This method employs one inverter as master, which operates in voltage-controlled modeand dictates the output voltage of multi-inverter system. Remaining (n-1) invertersact as slaves and they operate in current-controlled mode and their current referenceis derived from average of load current. It is just like connecting one voltage source inparallel with (n-1) current sources[7]. This method oers an advantage that the system isexpandable just with CCPI(Current-Controlled PWM Inverter). The use of this methodis justiable only if the number of inverters to be paralleled are large.

But on the other hand the reliability, which is the driving cause for using multiplesmall units in place of single large unit, is compromised. The system has to be shutdown on the event of failure of master unit. Usual solution to this is to take maximum

7

rated unit as master or to take larger value of factor of safety(FOS) for master unit.

1.3.3 Instantaneous Current Sharing Methods

Methods described above, are all decoupled methods for parallel operation of inverters.Those methods do not require control interconnection for their operation. But this makesthem incompatible to share harmonic components of load current. In instantaneouscurrent sharing methods, the sharing is achieved by utilizing the information about thecurrent shared by all inverters. It has centralized control and modulation signals arederived utilizing the information about all variables. This method possesses variouscategories depending upon the way, the current references are derived viz., averagecurrent sharing, maximum current sharing, and rotating reference current sharing.

Current sharing methods have been evolved in past few years, which utilize theinformation about the current shared by dierent units to achieve instantaneous currentsharing. As this method involves the current information from other inverters, the systemcomes under the class of multi-input multi-output(MIMO) systems. This complicatesthe stability analysis and controller design for individual inverter. As this method usescentral control strategy, it comes under the class of centralized control and it looses theadvantage of independent control.

1.4 Thesis Work

In this thesis, the design approach for designing various controllers for instantaneouscurrent sharing is described and implemented. The controls of all inverters have beenretained independent of each other. This amalgamates the advantage of harmonic shar-ing from current sharing methods and of independence of control of each inverter fromdecoupled methods. Also the DC bus voltage control is demonstrated without any needof auxiliary converter by controlling the power ow through inverters.

Motivation of the work is to achieve instantaneous current sharing without usingthe information regarding remote variables and making the control of each inverterindependent and redundant. The control should be based solely on information that is

8

available locally at the inverter, because of the following factors

• In many applications, the distance between the various units makes communicationof information between inverters impractical and costly.

• The absence of (fast) communication needs enables easy system expansion by theaddition of new loads and inverter units at any desired location in an interconnectedac system.

• Reparation, maintenance or replacement of inverter units having no signal inter-connection is easily achieved without interrupting system operation.

• Also, if the control is critically dependent on the operation of the communicationlink, the reliability of the distributed system as a whole is reduced. A truly fault-tolerant conguration requires that there are no vital points common to all invertermodules.

The communication of information can be used to enhance system performance, aslong as it is not critical for system operation. This implies that the critical, inner controlloops at each inverter should be based on terminal quantities only, such as local voltageand current measurements, while non-critical, optimizing outer control loops could usecommunicated information, if desired. Furthermore, each inverter unit should have equalimportance from the point of view of control, giving rise to truly distributed, 'master-less' operation. Hence the inner voltage control loop in the method proposed utilizesonly terminal quantities, whereas, the current sharing outer loop uses the load currentinformation only. Other oine information required by the outer current sharing loop isthe number of inverters operating in parallel to derive the average instantaneous currentreference.

1.5 Layout for Parallel Inverters fed from RES

Fig.1.2 shows the proposed conceptual layout of n parallel inverters fed from variousRES modules. The RES moudles for their proper operation require constant DC linkvoltage and it has to be maintained from inverter side. The modulation signals for all

9

in

nfC

1lX1

2

n nlX

no

DC Link

To grid or AC Load

System*PMSG = Permanent Magnet Synchronous Generator

2lX

Voltage−controlled Inverters with LC Filter

DC

DC

SPV Module

Wind Turbine

AC/DCInverter

PMSG

1Lf

fC

V 1o

V

3−φ

1

1Ti1

2TV 2o

L 2f

2fC

2

fnnTL

i

Figure 1.2: Distributed Generation Conguration of Parallel Inverters.

three phase inverters have to be generated through control scheme to satisfy the followingobjectives

• Voltage Control: To track the sinusoidal reference voltage derived from a freerunning synchronous wave or from grid in presence of load transients. All invertersshould hold their amplitudes, phase and frequencies equal to avoid circulatingcurrents.

• Instantaneous Current Sharing: Load currents are to be shared equally by allinverters even during transients in the load. This is done by introducing correction∆V in voltage reference Vref

∗ (Fig.1.3).

• DC Link Voltage Control: DC voltage is regulated within small range by controllingthe real power ow though inverters. This is obtained by adding another correction∆E (refer Fig.1.3) to the normal voltage reference Vref

∗.

This forms a sort of parallel control rather than the usually employed hierarchial controlwhich introduces the hierarchy in the dynamic responses of states of system. The innervoltage controller forms the driving loop and controller is designed to ensure sucientbandwidth to share upto 21st order harmonics (1050Hz for 50Hz system). Proper cor-rection voltages are derived for current sharing and DC bus control, and are added tothe reference.

10

*vop vop

∆Epiop*Qref

refP

Idcin

Vdc vop iop

iop

ic

Synchronised Reference Voltage − Same For All Inverters

Calculation Block

Kc

pK curr+ K curris

Averaging Block

iav

io1

P Inverter

∆vp

Vref*

inner loopActive Damping

H(s)

io2

iop

ion

Reactive Power Demand From Load

Power Input to DC Bus

M

From Different InvertersLoad Currents

+

Current Controller

+ +

+

++

++

+

Vdc

Vdc*

th

iLm

Inner Voltage Controller

Plant

vi

P in

ControllerCurrent Sharing

Outer voltage−feedback loop

iop

L s1

Rf

1

fC sf

Figure 1.3: Per phase schematic of Whole Control Strategy with Current SharingControl & DC Bus Control.

Per phase control schematic of proposed strategy for two 3-ph inverters is as shownin Fig.1.3. It can be appreciated that same strategy is applicable for (n+1) congura-tion, oering redundancy in operation. Hence same decentralized control algorithm isapplicable to all inverter modules.

1.6 Organization of Thesis

Design of LC lter is discussed in chapter two. The parametric values for passive el-ements are decideed in this chapter to meet various requirements like attenuation andbandwidth. Modeling of basic plant for parallel operation of inverters consisting of in-verter with lter is explained in chapter three. Two methods for designing inner voltageloop are also explained with their design requirements. The design of outer loop forcurrent sharing loop and dc bus voltage control loop are discussed in chapter four. Amethod to analyze the interaction between parallel inverter is also included in this chap-ter. The details of experimental setup and experimental results are included in chapterve. The results are discussed and are compared with analysis. The implementationof control algorithms on FPGA platform is discussed in chapter six with ow of dataand computation blocks. Also various blocks prepared, for interface and development ofpower elctronic applications are discussed in the same chapter. Chapter seven concludeswith the enhancement achieved in the thesis work along with issues noted during thecourse of design. Also the scope for extension of work is discussed in the same chapter.

11

Chapter 2

LC Filter Design

Before paralleling the inverters, the switching harmonics from its output must be re-moved by ltering them. Inverter output contains high frequency switching harmonicson top of fundamental voltage component. This are required to be ltered out beforesupplying voltage to the load. Hence a ltering stage is included between inverter andload. Harmonics in output voltage are of order of switching frequency or their multi-ples. The LC lter is a good choice for lter as it is a second order ler and has higherattenuation at any given frequency compared to rst order lter of same bandwidth.The inverter in combination with the LC lter forms the basic plant which has to becontrolled. In this chapter the design of passive elements like inductor and capacitorsfor LC lter is described for switching frequency of 5kHz and 10kHz.

2.1 Introduction

Fig.2.1 shows the layout of PWM inverter with LC lter, which forms the primaryplant for design of any control algorithm. LC lter is a second order lter with second

ViaCdcdc

fL R f

Cf V

ob

oc

Voa

V

V

Vib icV

Figure 2.1: PWM Inverter with LC Filter

12

order transfer function and hence its gain decreases at the rate of 40dB/decade aftercorner frequency. As LC lters are inherently undamped systems due to absence ofany physical resistive component in the circuit, they have large resonant peak at theircorner frequency. The corner frequency of LC lter is also called resonant frequency(ωo).Apart from attenuation required at switching frequency, the other factors deciding theselection of passive components are availability of components, size of inductor(economy)and the control bandwidth as needed for specic application. This factors are discussedin following sections.

2.2 Filter Design Considerations

Typical bode plot of any LC lter is shown in g.2.2 with indication of resonant fre-quency, resonant peak and attenuation slope. Dotted line shows the ideal asymptoticplot of second order transfer function. The overall transfer function of LC lter is

40 dB/decade

ο

resonantfrequency

rad/sec

dB

Q − resonant peak

ω

Figure 2.2: Bode plot of typical LC lter

G(s) =Voa(s)

Via(s)=

1 + Rc.Cf .s

Lf .Cf .s2 + (Rc + Rf ).Cf .s + 1(2.1)

where,Lf = Filter inductance in Henry(H)Cf = Filter capacitance in Farad(F)Rf = Parasitic resistance of inductor in ohms(Ω)

Rc = Parasitic resistance of capacitor in ohms(Ω).

13

This is typical second order transfer function and comparing it with standard secondorder transfer function

G(s) =1

( sωo

)2 + sQωo

+ 1(2.2)

we get, the corner frequency

ωo =1√LC

rad/sec (2.3)

and the resonant peak magnitude as

Q =1

Rf

√Lf

Cf

. (2.4)

Various aspects regarding the lter design are discussed in subsections to follow.

2.2.1 Attenuation

The inverter will produce mainly harmonics of order of switching frequency and of itsmultiples and they are required to be attenuated. Sucient attenuation has to be pro-vided for switching frequency components and for higher frequencies. For this purposelter is designed to provide attenuation of atleast 30dB or more for frequencies aboveswitching frequency(fs). The gain of LC lter will start to decrease from corner fre-quency at the rate of 40dB/decade and we need gain to be atleast -30dB at switchingfrequency(fs). This sets the criteria for selection of corner frequency(ωo). Hence cornerfrequency will be decided according to the attenuation requirement.

2.2.2 Resonant Peak

The magnitude of resonant peak depends upon the value of inductance(Lf ), capacitance(Cf )and parasitic resistance(Rf ) as in eqn.(2.4) and this may amplify any component of volt-age around corner frequency produced by the inverter to a large extent. Resonant peakhas to be retained as low as possible by properly selecting the values of lter parametersto avoid resonating oscillations in system during dynamic conditions. Also the value ofcapacitance should be low enough to have capacitor current within limit. This restrictsthe use of high value of capacitance for decreasing resonant peak. Whereas, the inductorvalue is xed by attenuation requirement. So the only way to decrease the resonating

14

peak is by increasing the value of resistance in lter. This is same as increasing dampingin lter transfer function. Increase in resistance will increase the losses in lter whichdeteriorates the eciency of system as whole, as well as it will give rise to cooling prob-lems. Hence virtual implementation of inserting a resistive eect in lter without usingexternal resistance is used. This is called "active damping" and is explained in nextchapter. Hence while designing the lter, the resonant peak need not be included indesign criteria and it will be taken care of by active damping.

2.2.3 Bandwidth

The inner-loop controller bandwidth decides the maximum corner frequency of LC lterthat can be used. The application is meant for instantaneous current sharing and itrequires the bandwidth of inner loop to be atleast 1050Hz as explained in sec.(1.5). Alsothe occurrence of resonant peak must be before crossover of the open-loop bode diagramof inner loop voltage controller. This will simplify the controller design, especially fromthe phase margin point of view. Hence the resonant frequency must be less than 1050Hz.This is explained in next section.

The resonant frequency(ωo) is limited by the bandwidth of inner loop voltage con-troller, whereas, the latter is limited by the maximum sampling frequency that can beused for digital realization of controller. This is because, the sampling frequency mustbe 15 to 20 times higher than the bandwidth of loop which has to be implemented ondigital platform[21].

2.3 Design of LC Filter

The design of LC lter is discussed for switching frequency of 5kHz and 10kHz.

2.3.1 For fs = 5kHz

Considering design for 30dB attenuation the value of corner frequency(ωo) can be cal-culated using:

30 = 40 log(2π fs

ωo

) (2.5)

15

Table 2.1: LC Filter ParametersParameters fs=5kHz fs=10kHz Unit

Attenuation at fs 30 40 dBωo 889 998 HzLf 680 540 µHCf 47 47 µFRf 0.25 0.25 ΩQ 23.4 22.4 dB

Table.2.1 shows the lter parameters designed with given attenuation requirement.It also shows corresponding the resonant frequency and resonant peak.

102

103

104

105

106

107

−180

−135

−90

−45

0

Pha

se (

deg)

Bode Diagram

Frequency (Hz)

−150

−100

−50

0

50

System: gsFrequency (Hz): 889Magnitude (dB): 23.4

Mag

nitu

de (

dB)

System: gsFrequency (Hz): 5.07e+003Magnitude (dB): −29.9

Figure 2.3: Bode plot of lter for 5kHz

The bode plot of the corresponding lter is as shown in g.2.3. From bode plot itcan be seen that if the cross-over frequency of inner loop is after the corner frequencyof lter, then phase margin is nearly zero in absence of any compensation at cornerfrequency. This is because the phase after corner frequency is almost equal to −180o.Hence a lead compensator or a zero at or below corner frequency will provide sucientrise in phase at the cross-over frequency, satisfying the phase margin requirement ofcontrol design[refer g.(3.14)].

16

2.3.2 For fs = 10kHz

Considering design for 40dB attenuation the value of corner frequency(ωo) can be cal-culated using:

40 = 40 log(2π fs

ωo

) (2.6)

The designed values are given in Table.2.1. The bode plot for lter for 10kHz is as shown

102

103

104

105

106

107

−180

−135

−90

−45

0

Pha

se (

deg)

Bode Diagram

Frequency (Hz)

−140

−120

−100

−80

−60

−40

−20

0

20

40


System: gsFrequency (Hz): 1e+004Magnitude (dB): −40

Mag

nitu

de (

dB)


in g.2.4.

2.4 Passive Ratings

In last section the parametric values of inductance and capacitance for lter were de-signed. Here the method is discussed for selection of maximum current rating of induc-tors and capacitors. The lter designed for 5kHz is used for simulation with inverter ofrating as follows

Rating of Inverter is 20KVADC Bus Voltage Vdc = 400VOutput Line-Line Voltage VL−Lrms = 220V

17

For this rating, the rms value of rated load current is ILrms= 52.48Amps i.e ILpeak=75Amps.

On top of this load current, inductor will also carry the harmonic currents of order ofswitching frequency and its multiples. To determine the continuous peak and short timesurge current rating of inductor and capacitor, the analysis is done assuming sine-trianglemodulation at switching frequency of 5kHz and simulation results are presented to sup-port the mathematical analysis.

2.4.1 Calculation Of Harmonics Through Passives

From reference[20], the peak amplitudes of the switching frequency component and sec-ond multiple of that at the outside of inverter for worst case of modulation index(ma)=0.9is given by :

Via(fs) = 0.7095Vdc

2

Via(2fs ± 2f) = 0.269Vdc

2. (2.7)

The other higher order components can be neglected for analysis, as their contribution ismuch lower compared to fundamental. Also as the frequency modulation index mf = fs

f

is quite higher than 15, the higher order harmonics in the output voltage of inverter arenot dependent on mf . Hence the peak amplitude of harmonic voltage Via(fs) in bothcases of switching frequency remains same.

The peak of harmonic currents through inductors and capacitors are calculated bydividing the harmonic voltages calculated earlier with inductor reactance. The capacitorreactance is neglected while calculation, because its value is very low for high frequencyharmonics compared to inductor reactance. Hence the total peak current that can rideon top of fundamental current through inductor is 7.864A for fs=5kHz and 4.98A forfs=10kHz.

The peak current carried by inductor at rated load with fs=5kHz equals

i(inductor) = ILpeak+ iL(h) ≈ 75 + 8 = 83Amps

and capacitor will carry only harmonic current of

i(capacitor) ≈ 8Amps.

18

0 0.02 0.04 0.06 0.08−80

−60

−40

−20

0

20

40

60

80

Time(seconds)

Cur

rent

(Am

ps)

Inductor current superimposed on load current

Inductor currentLoad current

Figure 2.5: Inductor current at rated load for 5kHz

0 0.02 0.04 0.06 0.08−10

−5

0

5

10Capacitor Current Ic at Rated Load

Time(seconds)

Cur

rent

(Am

ps)

phase a

Figure 2.6: Capacitor current at rated load for 5kHz

The analytical results regarding ow of harmonic currents are veried through simu-lation for fs=5kHz with inverter and LC lter in presence of voltage controller at ratedload with power factor of 0.8. Inductor current and capacitor current are as shown ing.(2.5) and g.(2.6) respectively.

It is seen from g.2.6 that peak of harmonic component owing through the lteris nearly equal to 8 Amps as calculated. This veries the analysis. Also the outputvoltage Vo is as shown in g.2.7. It is to be noted that output voltage does not containappreciable harmonic component.

19

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08−150

−100

−50

0

50

100

150

Time(seconds)

Out

put V

olta

ge(V

olts

)

Output Voltage of Filter

Figure 2.7: Output Voltage of Filter at Rated Load for 5kHz

2.5 Concluding Remarks

The requirements and design issues for LC lter were discussed in this chapter. Thedesign is demonstrated for switching frequencies of 5kHz and 10kHz. Design of lterfor 5kHz frequency was veried using simulation with standard inverter. Also, as theminimum bandwidth required by instantaneous current sharing method is 1050Hz(21×50), the lter designed for 5kHz switching frequency is used for further design, simulationand experimental implementation. The lter designed for 5kHz has resonant frequencyof 889Hz, which is well below the required bandwidth of inner-loop bandwidth and itcan be used as lter for inverter in application for instantaneous current sharing method.The lter designed for 5kHz is capable of attenuating switching harmonics for higherswitching frequencies. The LC lter forms a linear plant and hence its parametric designis independent of rating for which it can be used. Hence same lter parameters can beused for dierent ratings of system, provided the switching frequency is either same orhigher than the one for which the lter is designed.

20

Chapter 3

Modeling & Design of MultiloopVoltage Controller

Instantaneous current sharing scheme presented in this thesis employs a common volt-age controller to regulate the lter output voltage. The corrections are added on topof synchronized reference to the reference of voltage controller. Hence voltage controllerforms inner loop of strategy. It forms the driving loop for instantaneous current shar-ing strategy and the proper operation of current sharing, dc bus control and sinusoidalvoltage tracking depends on its design. In this chapter two methods for the design ofinner voltage loop are discussed. Their relative performance parameters like bandwidth,disturbance rejection and transient response are also discussed. The method of activedamping to decrease the resonant peak of lter transfer function to improve relativestability of the system is included. Modeling of system is done in two phase stationarytime-domain. This reduces the computational requirement of digital resources withouthampering the control algorithm performances. The chapter concludes with the dis-cussion of how the issues which arises while digital realization of analog controllers areaddressed.

3.1 Modeling of Plant

As shown in g.3.1, inverter with LC lter forms the basic plant module in parallel

conguration. The inverter is modeled as an algebraic gain of Vdc/2. It is assumed to

21

be constant while designing the voltage controller, because of its slow dynamics. The

modeling of inverter as simple dc gain is valid, because the switching frequency is very

high compared to fundamental frequency of modulation signal[20]. Hence the model

of inverter with LC lter reduces to the product of lter transfer function and inverter

gain. The dynamic equations for the basic module for equivalent single phase are

Figure 3.1: Single Phase Equivalent of Inverter with LC Filter

vi = ilrf + Lfdildt

+ vo (3.1)

vo = (il − io) Rc +1

Cf

∫(il − io) dt (3.2)

This equations are same for all the three phases and writing them in compact form forall three phases we get the following equations

d

dt

voabc

ilabc

=

−Rc

Lf

1Cf− RcRl

Lf

− 1Lf

−RL

Lf

voabc

ilabc

+

Rc

Lf

1Lf

viabc

+

1Cf

0

ioabc

. (3.3)

Here the subscript `abc' represents the three phase quantities. The information of three-wire three-phase quantities can be equivalently represented by two phase quantities

22

which are phase displaced by 900. Here all three phase quantities are converted to twoorthogonal phase quantities to reduce the computational requirement, as same controlwill get reduce from three phases to two phases without loss of accuracy. The threephase variables are transformed to stationary orthogonal axes (α − β), using followingtransformation

xα

xβ

= [K1]

xa

xb

xc

(3.4)

where,

[K1] =2

3·

1 −12

−12

0 −√

32

√3

2

. (3.5)

As the system is 3-wire three phase, the zero sequence components are absent.Converting the three phase system of (3.3) into α− β domain using transformation

(3.5) yields the following dynamic system equtation.

d

dt

X︷︸︸︷

voα

voβ

ilα

ilβ

=

A︷︸︸︷

−Rc

Lf0 1

Cf− Rc.Rl

Lf0

0 −Rc

Lf0 1

Cf− Rc.Rl

Lf

− 1Lf

0 −RL

Lf0

0 − 1Lf

0 −RL

Lf

X︷︸︸︷

voα

voβ

ilα

ilβ

+

B︷︸︸︷

Rc

Lf0

0 Rc

Lf

1Lf

0

0 1Lf

U︷︸︸︷

viα

viβ

+

Bd︷︸︸︷

− 1Cf

0

0 − 1Cf

0 0

0 0

Ud︷︸︸︷

ioα

ioβ

(3.6)

where,

23

X : States of System

A : Statetransition Matrix

B : Input Matrix

U : Inputs to System

Bd : Disturbance Matrix

Ud : Disturbance Inputs.

From matrix (3.6) in α−β domain, it is seen that no quantity of alpha axis is depen-dent on beta axis quantities and vice-versa. Hence they form two completely decoupledsystems in alpha and beta domain with same single phase equivalent ckt as in g.3.1and they can be controlled independently. This provides exibility of designing controlalgorithm for three phase system in single phase domain. The control and disturbancetransfer function for plant can be derived from eqn.3.6.

vo(s)

vi(s).= Gc(s) =

1 + RcCfs

LfCfs2 + (Rc + Rf )Cfs + 1(3.7)

vo(s)

io(s).= Gd(s) = − Lfs + Rf

LfCfs2 + (Rc + Rf )Cfs + 1(3.8)

The control input or the signals generated by control algorithm are modulation signals tothe inverter shown in g.3.1. The controls are designed based on lter transfer functionsgiven in (3.7). But control transfer function Gc(s), is between lter input voltage vi andlter output voltage vo. Hence the output from controller is same as vi and modulationsignals for inverter are generated by multiplying it with inverse of inverter gain(i.e.,Vdc/2).

3.2 Damping of Resonant Frequency Oscillations

The lter parameters used for design of controls and its implementation are same as thoseused for designing of lter for switching frequency of 5kHz. This parameters are producedhere in Table.3.1. This will give resonant frequency suciently lower than the bandwidthrequired for inner-loop(1050Hz). Simple zero at or before resonant frequency can providesucient phase margin at cross-over frequency. Hence the resonant frequency must be

24

Table 3.1: Filter Parameters Used for Control Designfs Lf Cf Rf ωo Q

> 5kHz 0.68mH 47µF 0.25Ω 889Hz 23.4dB

lower than cross-over frequency required by the inner-loop and the chosen lter satisesthis criteria. Also as the inverter can be modeled as constant gain, the control designsare independent of switching frequency and they will be valid for switching frequenciesof 5kHz or higher.

The bode plot of control transfer function without any external damping is as shownin g.3.2. It has high resonant peak, which will amplify any noise component of resonant

102

103

104

105

106

107

−180

−135

−90

−45

0

Pha

se (

deg)

Bode Diagram

Frequency (Hz)

−150

−100

−50

0

50


Mag

nitu

de (

dB)

System: gsFrequency (Hz): 5.07e+003Magnitude (dB): −29.9


frequency and drastically reduces the relative stability of the system. Also high reso-nant peak signies oscillatory behavior of the system during dynamic situations. Thisoscillations will hamper the proper operation of the inverter or it will lead to loss of syn-chronism with other inverters. The damping is required to avoid the disturbing eectsof oscillations induced by any transients. Hence resonant peak has to be decreased be-fore applying any control, to improve relative stability to the plant. The resonant peakis dependent on parasitic resistance of inductor and capacitor and can be decreasedby inserting extra resistance in lter. Physical inclusion of extra resistance to increasedamping is called Passive Damping and is explained subsequentely.

25

3.2.1 Passive Damping

Passive damping can be achieved by introducing a lossy element like resistor into thelter circuit. The damping resistor can be placed either in series or parallel with theinductor or capacitor of lter circuit. Fig.3.3 shows dierent positions for dampingresistors. The eects of inclusion of resistance at dierent positions in lter circuit is as

f L

C

R

sh

se

f

f

R

R

Figure 3.3: Possible positions of damping resistors

follows.

Resistance in series with inductor Resistance in series with inductor of LC lter ismost suitable from damping point of view. This is because, it will add the resistiveterm with Rf of control transfer function(3.7), without aecting any other portionof transfer function. Hence it is truly inclusion of damping in circuit. But themain ow of load current will ow through inductor and this increase the lossestremendously. Not only it will deteriorates the eciency of module as whole, butalso it raises the need of expensive cooling arrangements.

Resistance in series with capacitor From (3.7) it is seen that the inclusion of re-sistance in series will not only increase the damping, but it will also change theposition of zero in numerator. With increase in resistive component in series withlter capacitor, the numerator zero will come closer to the imaginary axis of s-plane. The zero near imaginary axis will decrease the attenuation provided bylter to high frequency signals. Hence judicious choice must be done while se-lecting the damping resistor, so that it will not aect the attenuating capacity oflter.

26

Resistance in parallel with capacitor Resistance in parallel with capacitor is not agood option to provide damping to the system. This is due to the fact that forhigh frequency voltage signals, the impedance of capacitor will be substantiallylow compared to resistor and hence resistor will be inecient to provide dampingfor resonant frequency oscillations.

Power Losses due to Passive Damping

Since a lossy element(resistor) is introduced into the circuit, power loss is inevitable.The power loss due to passive damping is given by eqn.(3.9).

Ploss = I2dRd (3.9)

where Ploss is the power loss in damping resistor (Rd), Id is the current through Rd.In high power applications, the damping power losses will be still higher and demands

forced cooling and decreases the eciency of the converter. So these losses should eitherbe minimized or completely eliminated.

3.3 Active Damping

An undamped LC lter has a resonant peak as shown in g.3.2. Disturbances in load

current or grid voltage may trigger resonance. So conventional passive damping tech-

niques like adding damping resistors are employed to damp the resonance. But it is

inecient as there will be considerable power loss in damping resistors. So passive

damping is not suitable for high power converters. In such cases active damping tech-

niques are employed, in which damping is achieved by the control algorithm instead

of physically adding resistors. This increases the eciency of the converter since no

physical element is involved in damping. Dierent active damping techniques have been

proposed in literature[18]. The virtual resistor concept is very attractive as it provides

extra damping to the system without incurring losses and need for physical component.

It emulates the eect of a resistor added to the lter circuit. The virtual resistor can

be added at dierent positions, either in series or parallel with inductors or capacitor.

27

In this thesis, active damping is achieved by adding a virtual resistor in series with the

lter capacitor (Cf ), because current owing through capacitor mostly contains resonant

frequency components and switching harmonics. So with resistor in series with capac-

itor apparently damps the resonant frequency oscillations without aecting the other

part of frequency spectrum. The virtual resistor is emulated by subtracting a voltage

proportional to lter capacitor current (Ic) from the inverter output voltage(Filter input

voltage). The resultant inverter output voltage (vi) is given by (3.10), where Kc is the

damping factor.

vi = vi −Kcic (3.10)

The equivalent circuit with active damping is shown in g.3.3. The transfer function isgiven by (3.11).

Gc(s) =Voa(s)

Via(s)=

1 + RcCfs

LfCfs2 + (Rc + Rf + kc)Cfs + 1(3.11)

From (3.11), it can be observed that even for Rf = 0, sucient damping is providedby Kc. The bode plot of control transfer function in g.3.5 shows the eect of activedamping.

c L

C

R

f

fR

c

f

Vo

k

+ −

ic

ic

Vi Vi~

Calculated within Digital platform

Figure 3.4: Equivalent circuit with active damping

28

−80

−60

−40

−20

0

20

40

Mag

nitu

de (

dB)

101

102

103

104

105

−180

−135

−90

−45

0

Pha

se (

deg)

Without Active DampingWith Active Damping

Figure 3.5: Bode Magnitude plot with and without active damping

3.3.1 Features of Active Damping

Active damping introduces an inner loop to voltage controller loop. It will subtract thevoltage proportional to capacitor current, hence emulating the eect of resistor in serieswith lter capacitor. Active damping not only saves the need of extra component fordamping, but also avoid the losses which might occurs in damping resistor. Also theadvantage of active damping will be more prominent for hight power converters, whereeciency is crucial issue in design. Active damping implementation is very easy as nophysical installations are required. However, this technique requires accurate measure-ment of capacitor current. Although, apparently a disadvantage, this requirement can bemet by proper estimation of capacitor current or by extracting the information regard-ing capacitor current. Instantaneous current sharing method requires to measure theamount of load current shared by each inverter unit, whereas, active damping requiresthe information regarding capacitor current. The information regarding both these cur-rents is contained in lter inductor current(il). Hence sensing the inductor current, willreduce the number of current sensors required by half. Also no extra means are requiredto extract the information regarding capacitor current. This is because, the resonant fre-quency components of inductor current are same as that of capacitor currents, whereas,

29

the low frequency components mainly comprise the load current. The various featuresof active damping are summarized below.

√ Emulation of virtual resistor

√ Ecient compared to passive damping

√ Simple to implement - no extra hardware and cooling are required

× Accurate information regarding capacitor current is required.

3.4 Control Requirements for Inner Voltage Loop

Cross-over frequency ωc of Inner Loop For instantaneous current sharing betweenparallel inverters, it is not only the fundamental component of load current whichhas to be shared but also harmonic components upto 21st order is required to beshared. This requires the bandwidth of inner loop to be suciently higher thanωb = 21× 50 = 1050Hz = 6597rad/sec, which decides the cross-over ωc frequencyof inner loop.

Phase Lag at Operating Frequency The phase lag of inner voltage loop has be lowenough in the operating zone of frequency so that during the design of outer loop,inner loop can be modeled as unity gain.

Steady-State Error To decrease the steady state error between magnitudes of inputand response the gain of inner loop must be atleast 20dB at operating frequencyand also it is to be maintained high upto 17th harmonic.

Type of Controller The control problem is of tracking the sinusoidal input and thetype of plant is 'zero' as seen from transfer function (3.7). Hence controller isrequired to have atleast one integrator and hence type-1 controller is required forinner loop.

30

3.5 Multi-loop Inner Voltage Controller

Voltage control loop forms the vital loop as the operation of other loops depends on itsaccuracy. The proper design of voltage controller ensures the tracking of voltage com-mand by VCVSI(Voltage Controller Voltage Source Inverter). The centralized control isrequired to improve both current sharing and voltage regulation and this need intercon-nections between inverters. The information sharing is done to know the deviation ofindividual share of all inverters from the desired average value. Only load current infor-mation is used for centralized control. Various design methods are available in literaturefor designing voltage controller for inverters[12]-[15].

Apart from normal reference of fundamental frequency, the inner voltage controlloop also requires to track the correction voltage ∆V and ∆E to compensate for currentimbalance between inverters and for DC bus control respectively. The functions ofthis corrections and there properties are explained in the successive chapter. Here twomethods are analyzed to design the driving voltage controller loop for inverters to makethem VCVSI(Voltage Controlled Voltage Source Inverter).

As described earlier, the PWM inverter is modeled as simple gain. The controlleris multiloop, which has inner capacitor current loop providing active damping to thesystem and an outer voltage feedback loop for feedback controller. The inner capacitorcurrent loop decreases the resonant peak and increases the robustness of the system. Toachieve the control requirements for inner loop, various methods for designing are triedand described in following sections and their performances are analyzed with simulinkof Matlab.

The per phase block diagram schematic of multi-loop voltage controller for 3φ inverteris as shown in Fig.3.6. In addition to active damping gain kc, a low pass lter(LPF) isincluded in capacitor current loop with corner frequency suciently higher than resonantfrequency(ωr=889Hz) to provide damping only for selective zone of frequency. Thisprovides damping upto frequency of choice and it avoids the sensor noise of currentsensor used to measure capacitor current from creeping in the control loop. Cornerfrequency of LPF is too high to degrade the phase plot of voltage control loop and can

31

+

ic

Kc

disturbanceLoad


+ vi

iop

H(s) M

*vo vo

inner loop

Inner Voltage

LPFActive Damping

iLm

Controller

Plant

1

fC sfL s1

Rf

Figure 3.6: Per phase schematic of Voltage Control Loop.

Table 3.2: Nominal Parameter Values for 3-phase Inverter and LC FilterParameter Value(Unit) Parameter Value(Unit)

Output Power 2.28 kVA Inductor(Lf ) 0.68 mHDC Link Voltage Vdc 300 Volts Inductor ESR 0.1 Ω

Output Voltage Vo(L-L) 110 Vrms Capacitor(Cf ) 47 µFSwitching frequency(fs) 10 kHz Capacitor ESR 0.001 Ω

Fundamental 50 Hz Active Damping 4.5 Ωfrequency(f) constant(kc)

be avoided from analysis without any loss in accuracy.System and lter parameter values designed to attenuate switching frequency har-

monics and which are also used for analysis and simulation are given in Table 3.2.

3.5.1 Robust Tuning of P-I Voltage Controller

Voltage loop controller is designed using H∞ norm(Robust PI Controller), which pro-vides the stability against parameter deviations and is optimized for good tracking per-formance and disturbance rejection. In this method a set of P-I controllers are extractedwhich satisfy the Routh stability criteria. From this set, a controller is selected whichyields robust stability and robust performance. Here H(s) of g.3.6 is P-I controlleroptimized for robust stability and performance.

32

Design

Simple P-I controller having kp & ki as proportional and integral gain is used in place ofH(s)[9]. A feed-forward gain of kf (=1) is included to decrease the phase error betweeninput and output. Transfer function of loop gain with this controller is given in (3.12).

vo

vo∗ =

(kf+kp+RcCf )s+ki

LfCfs3+(Rc+Rf+kc)Cfs2+(1+kp)s+ki(3.12)

Here such values of kp, ki&kf are selected, which will make the system as robustas possible. A system is robust if it remains stable and achieves certain performancecriteria in presence of uncertainties like parameter deviations, load and other externaldisturbances. This is generalized method for tuning of PI controller. An importantsubproblem to this approach is to nd the region in space of kp, ki and kf in which theclose loop system is stable[19].

The stated problem of designing a robust PI controller is to nd a set of controllerparameters K = K∗, such that the close loop system of (3.12) satises the followingspecications:

• Routh-Hurwitz stability criterion(Asymptotic stability) - Ensures all closed looppoles in left half of s-plane.

• Robust Stability - Notion of robust stability can be described as follows. Supposethe plant transfer function Gc(s) of (3.11) belongs to a set ℘ which is a set ofall possible plants that will form due to deviation in plant(Gc(s)) parameters likeLf , Cf and Rf from their nominal values or due to any other uncertainty. Aproposed PI controller C(s) is robust stable if it stabilizes nominal plant Gc(s),and stability also hold for every plant which belongs to set ℘.

• Robust Performance - Notion of robust performance is that the internal stabilityand performance of specied type viz. - tracking, disturbance attenuation, noiserejection, less control eort - should hold for all plants in ℘[23].

33

The equivalent closed loop block diagram depicting system and controller with ref-erence(r), error(e), disturbance(d) and output(y) is shown in Fig.3.7. Reference(r) iseither any sinusoidal free running reference for Vo or is derived from the grid if VCVSI ismeant to couple with grid. Disturbance d contains the information regarding actual dis-turbance to system - Load current io, m is controller output and is same as modulationsignal whereas y is output voltage Vo.

With chosen system parameter values from Table 3.2 the close-loop transfer function(3.11) reduces to (3.13).

vo

vo∗ = (kf+kp)s+ki

3.196×10−8s3+1.457×10−4s2+(1+kp)s+ki(3.13)

Using Routh stability criteria on (3.13), following conditions for kp and ki are obtainedto have asymptotic stability and it also denes the region of controller gain values, inwhich the close loop system is stable.

ki > 0

4560 · kp > ki − 4560

Apart from these constraints, there are practical limitations on gain values imposed bythe digital platform and number format to be used for implementation. Assuming useof 2.14 Q number format[Refer Appendix. A], for implementation on digital platform,the maximum proportional gain kp that can be implemented is 2. In digital platformthe eective value of ki to be used for calculations is

ki(fixed point format) = kiactual ×Ts

2. (3.14)

Also in 2.14, maximum number that can be represented accurately is 2. Hence with

(s)+ +

+d(disturbance)

mer(reference)

y(Output Voltage)C(s) G

c

Figure 3.7: Typical representation of close loop system.

34

assumed sampling frequency of 10kHz and anticipating eqn.(3.14), the maximum integralgain ki that can be implemented is 40,000.

With above constraints and range, there forms a set of stabilizing PI controllerswhich satisfy the Routh(asymptotic) stability criteria. From this set, a controller willbe selected which serves the robust stability and robust performance.

Robust Stability

To nd the criteria for robust stability, the plant is modeled in one of the four uncertaintymodels[23]. In plant transfer function of (3.11), the value of Rc is negligibly smallcompared to kc which is xed. Hence the uncertainty in co-ecient of s is not worthconsidering. Henceforth the uncertainty in coecient of s2 is only considered with itsnominal value equal to ao = Lf o · Cf o. The set of plant transfer functions(℘) is

℘ =1

as2 + bs + 1; | ∆ |≤ 1. (3.15)

where, a = ao + (0.2Lf o × 0.1Cf o)∆, 20% uncertainty in inductance and 10% un-certainty in capacitance is considered as worst case deviation of parameters from theirnominal values. ∆ is circle of perturbation[22] and it can assume any value from -1 to1. b ≈ kcCf . Here a is only uncertain parameter.

Here the ℘ is modeled as inverse additive perturbation model[22][23] with Po asnominal plant.

℘ =1

as2 + bs + 1=

Po

1 + ∆W2Po

(3.16)

From (3.16) and acknowledging the fact that | ∆ |≤ 1, the weighting function is obtainedto be W2 = 1.45× 10−8s2.

Only those controllers from the range obtained earlier will provide the robust stabilityfor which ‖ W2PoS ‖∞ < 1, where S is sensitivity or error transfer function[23].

S =1

1 + Gc(s)C(s)(3.17)

Those combinations of kp and ki are extracted from the range found for Routhstability which satisfy the condition for robust stability. It will for a set of controllersproviding robust stability - stability for any plant from set ℘.

Subsequently, the controller giving optimized performance will be extracted.

35

Robust Performance

There are various performance parameters that can be considered like tracking per-formance, disturbance rejection, noise rejection, steady state performance, optimum orminimum control eort etc. Here the problem is voltage tracking in presence of loadcurrent as disturbance. Hence optimization for tracking performance and disturbancerejection are considered. From Fig.3.7 following relationships are available.

y = (1 + GcC)−1GcC · r + (1 + GcC)−1 · dm = C(1 + GcC)−1 · r − C(1 + GcC)−1 · de = (1 + GcC)−1 · r − (1 + GcC)−1 · d. (3.18)

Reference r and disturbance d in this case are sinusoidal reference voltage and loadcurrent respectively, which are energy bound signals as they represent variables of prac-tical system. To have good tracking performance and disturbance rejection, we needto minimize the ∞-norm, the gain, of corresponding transfer function[22],ch-3. Henceoptimal controller(K = K∗) will be determined from the set of robust controllers foundin last section, which optimizes for the following.

• Tracking : This needs to minimize ∞-norm of the transfer function from refer-ence(r) to error(e) = ‖ (1 + GcC)−1 ‖∞.

• Disturbance Rejection : This needs to minimize ∞-norm of the transfer functionfrom disturbance(d) to output(y) = ‖ (1 + GcC)−1 ‖∞.

The innity norm of sensitivity transfer function is minimized to get optimal PI con-troller. Innity norm of any transfer function is same as the peak of their magnitudeplot for frequency response(Bode Plot). That controller is extracted which providesrobust stability with minimum peak of magnitude plot of sensitivity transfer function.Fig.3.8 shows the bode plots of sensitivity transfer function for dierent controllers. It isnotable that in operating range, the gain plot lies substantially below 0dB line, showinggood tracking and disturbance rejection. Fig.3.9 shows the bode plots of loop gain for

36

−80

−60

−40

−20

0

20

Mag

nitu

de (

dB)

100

101

102

103

104

−45

0

45

90

Pha

se (

deg)

Bode Diagram

Frequency (Hz)

Figure 3.8: Bode Plots of Sensitivity Transfer Function for dierent controllers.

dierent controllers. It can be noted that there is very little change in crossover fre-quency, with controllers. Hence while optimizing the tracking and disturbance rejection,the bandwidth of system is not compromised.

−150

−100

−50

0

50

100

Mag

nitu

de (

dB)

100

101

102

103

104

105

−225

−180

−135

−90

−45

0

Pha

se (

deg)

Bode Diagram

Frequency (Hz)

Figure 3.9: Bode Plots of Loop Transfer Function with Controllers & Active Damping.

Final controller providing robust stability and optimized performance is kp = 0.3 andki = 1475 with minimized ∞-norm of sensitivity transfer function S equal to 1.3774.Bode plot with robust PI controller obtained is as shown in Fig.3.10. Controller providesphase margin of 92.8o at cross-over frequency of 266Hz. Gain margin is 37.2dB. Thisbandwidth is sucient enough to track any reference signal consisting of up to 5th

harmonic components. However, this bandwidth is not sucient for voltage controller

37

Bode Diagram

Frequency (Hz)10

010

110

210

310

4−225

−180

−135

−90

−45P

hase

(de

g)

−100

−50

0

50

100

Mag

nitu

de (

dB) Phase Margin : 92.8 degat 266Hz

Gain Margin : 37.2dB

Figure 3.10: Bode Plot of Loop Transfer Function with Robust PI Controller & ActiveDamping.

0 0.01 0.02 0.03 0.04 0.05−100

−80

−60

−40

−20

0

20

40

60

80

100

Time (sec)

Outpu

t Volt

age(V

)

Reference Voltage

Output Voltage

Figure 3.11: Calculated response for Output phase voltages with optimized PI VoltageController and kc = 3Ω. Nominal parameters are considered.

to be used for instantaneous current sharing scheme.

Simulation Results

Fig.3.11 shows the calculated response of system with robust PI controller and parame-ters as in Table 3.2 with corresponding simulated response as in Fig.3.12.

As a worst case scenario, the system is simulated with 20% increase in inductance(Lf )value and 10% increase in capacitance(Cf ) value. Corresponding waveforms are shownin Fig.4.1.

Output voltage responses are same, both with nominal parameters and perturbedparameters and also the transients due to load current disturbance die rapidly. Hence

38

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07−150

−100

−50

0

50

100

150

Output Voltage Tracking of Three Phase Inverter with LC Filter

Time(Seconds)

Vo

ltag

e(V

olt

s)Step Change of 20% in VoltageReference Peak

Sudden Application of load from noload to load of 15 Amps RMS

Figure 3.12: Simulated response for Output phase voltages with optimized PI VoltageController and kc = 3Ω. Transients in load and reference are simulated to show their

eects on output voltage. Nominal parameters are used.

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07−150

−100

−50

0

50

100

150

Vo

ltag

e(V

olt

s)

Time(Seconds)

Step Change of 20% in VoltageReference Peak


Figure 3.13: Simulated response for Output phase voltage with optimized PI VoltageController and kc = 3Ω. Transients in load and reference are simulated to show their

eects on output voltage. Perturbed parameters are used.

39

−60

−40

−20

0

20

40

60

Mag

nit

ud

e (d

B)

Bode Plot of Open Loop Gain including Controller H(s) and Plant with Active Damping

Frequency (Hz)10

110

210

310

410

5−180

−135

−90

−45

System: olpPhase Margin (deg): 31.8Delay Margin (sec): 6.48e−005At frequency (Hz): 1.36e+003Closed Loop Stable? YesP

has

e (d

eg)

Phase Margin(deg) = 31.8Cross−over Frequency(Hz) = 1360

Figure 3.14: Bode Plot of Loop Transfer Function with Controller & Active Damping.

the designed controlled has decreased the sensitivity towards parameter by minimizingthe sensitivity transfer function.

3.5.2 High Bandwidth Second Order Voltage Controller Design

Simple P-I controller is not able to provide sucient bandwidth to use it for instan-taneous current sharing. Hence a second order voltage feedback controller is designedusing bode plot to have crossover frequency of inner loop higher than 1300Hz and thegain of atleast 20dB is maintained in operating zone of frequency to have low trackingerror. Also one integrator is included in the feedback controller to have type-1 open looptransfer function as the system has tracking problem. The controller is designed andintegrated with LC lter such that the output of LC lter vo can track any signal vo

∗

consisting upto 21st order harmonics(refer Fig.3.6).Designed controller H(s) has format of 2nd order controller as in (3.19).

H(s) =K(s + z1)(s + z2)

s(s + p)(3.19)

The bode plot for loop gain including voltage controller and active damping loop is asshown in Fig.3.14.

Loop has phase margin of 31.8o with cross-over frequency of 1360Hz(8545rad/sec).This bandwidth is sucient for inner loop of instantaneous current sharing scheme. The

40

0 0.005 0.01 0.015 0.02 0.025 0.03−1.5

−1

−0.5

0

0.5

1

1.5Analytical Response to 50Hz Sinusoid(Vo)

Time (sec)

Vol

ts(p

.u.)

Figure 3.15: Calculated Response of Plant to 50Hz sinusoid

gain is higher than 20dB limit in operating zone of frequency. Hence it satises allcontrol specications of section.3.4.

Simulation Results

Analytical response of plant with controller to 50Hz sinusoid command is as shown iong.3.15.

Fig.3.16 shows the response of voltage controller for system with parameters as inTable 3.2. Fig.3.16(b) shows the response of controller with reduced active damping con-stant. This demonstrates the eectiveness of active damping in damping the oscillationsinduced in system, due to any dynamic condition.

Bilinear transformation(based on trapezoidal rule of integration) used for convertingcontinuous domain controller into digital form is :

s =2

Ts

z − 1

z + 1(3.20)

The digital controller using above transformation is:

Hd(s) =2.918z2 − 3.583z + 1.013

z2 − 1.006z + 0.00591(3.21)

41

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07−150

−100

−50

0

50

100

150

Output Voltage Tracking of Three Phase Inverter with LC Filter

Time(Seconds)

Vo

ltag

e(V

olt

s)

Step Change of 20% in VoltageReference Peak


(a) kc = 3.0

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07−150

−100

−50

0

50

100

150

Time(Seconds)

Pha

se A

Vol

tage

(Vol

ts)

(b) kc = 0.5

Figure 3.16: Output phase voltage waveform with Voltage Controller. Transients inload and reference are simulated to show their eects on output voltage. (b) shows the

eect of reduced damping on Phase-A voltage.

42

3.6 Issues in Digitization of Controller

There are certain issues that need to be resolved while realizing a digital controller,which has been designed using emulation techniques. Discretization of controller willsurely lead to errors in the system due to quantization and approximation(zero orderapproximation of signal between sampling period) eects. It is worthy to note thatthe single most important impact of implementing a control system digitally is delayassociated with hold. A delay in any feedback system degrades the stability and dampingof the system.

3.6.1 Selection of Sampling frequency

In Power Switching Converters realized with digital controllers, a convenient choice ofsampling frequency is the switching frequency. Another driving issue in selection forsampling frequency is the fact that to implement any continuous controller in discretedomain, the system must be sampled at atleast 20 times higher rate than bandwidth ofsystem[21].

Inner loop of system requires bandwidth substantially higher than 1050Hz(21× 50)for instantaneous current sharing operation. From this the sampling frequency is chosenas 20kHz →, double than the switching frequency.

To avoid false switching due to the fact that sampling frequency is higher thanswitching frequency, the modulation signals are synchronized with carrier wave suchthat they are updated at the middle of triangular wave as shown in waveform-3.17.

3.6.2 Eect of Sampling

The signal in digital system is sampled continuously at sampling frequency and signalinformation is available only during sampling instants. Higher will be the samplingfrequency, digital system will better resembles the continuous counterpart. The approx-imated or extrapolated signal will be used between sampling instants and extrapolationis done using ZOH(Zero Order Hold).

Zero Order Hold introduces a phase delay in signal which is proportional to the

43

0.025 0.0251 0.0252 0.0253 0.0254 0.0255 0.0256 0.0257 0.0258 0.0259 0.026−1

−0.8

−0.6

−0.4

−0.2

0

0.2

0.4

0.6

0.8

1

Time(secs)

Mod

ulat

ion

Sign

al

Figure 3.17: Modulation Signal with Carrier Wave

frequency component of signal. The low frequency components of signal will be passedwithout introduction of much phase delay. The Bode plot of ZOH is as shown in g.3.18.From bode plot it is seen that substantial phase lag is introduced to the frequencycomponents which are logarithmically near to the sampling frequency(ωs). The operatingfrequency is far below the sampling frequency, but the resonant frequency is nearer toit and it is found that the active damping provided in continuous domain will not workin discrete domain without any compensation incorporated for this lag. This is due tothe fact that the resonant frequency components will experience a phase lag, which willhamper the operation of active damping loop.

Upto sampling frequency the phase lag introduced by ZOH varies linearly from 0 to180o. Also the resonant frequency(ωo) of lter is 889Hz and the phase lag introduced byZOH to resonant frequency components is given by

∆θ = (889

20000) · 180 = 8o. (3.22)

The lead compensation must be provided at resonant frequency for active damping,when controller is implemented on digital platform. This lead compensation at resonantfrequency makes it possible to have low sampling frequency without incurring phaseerrors in signal frequencies of major interest. Block diagram of inner control loop withlead compensation at resonant frequency for active damping is as shown in g.3.19.

44

Figure 3.18: Bode Plot of Zero Order Hold(ZOH)

o*

Mvo

Kc

io−

f fC s

f

1 1

Plant

+

Active Damping inner loop

iciL

vi

−

m


R

+v −

− L s

ωr

Lead of 8


o

at

Figure 3.19: Block Diagram of Inner Loop with Compensation for ZOH phase Delay inActive Damping

45

In literature for parallel operation of inverters, the techniques employing instanta-neous current sharing are forced to operate with high switching frequency of 40kHz orhigher, but with above two modications instantaneous current sharing can be achievedwith low switching frequency of 5kHz or 10kHz.


The modeling of inverter with LC lter has been explained alongwith its representationin two phase orthogonal axes domain. Specications for inner voltage loop have beendiscussed. Two methods for designing inner voltage loop were discussed with their designintricacies and responses. The chapter concludes with issues regarding digital realizationof designed controllers in continuous domain.

46

Chapter 4

Design & Stability Analysis ofInstantaneous Current Sharing Loopand DC Bus Control

In parallel operation of inverters, if all inverters are identical, the output current willbe equally shared automatically. However in practical circuits, the parameters of theinverters as well as lters have deviation from nominal values. Also inverters behave likesinusoidal voltage sources and mismatch between their voltage templates will lead tolarge circulating currents which may damage the BIM(Basic Inverter Module) or derateit. The parameter deviations cause the output current of the inverter to change fromnominal one(average of load current). The amount of loading also aects the sharingof currents among inverters. The loading will increase the voltage dierence betweeninverters and give rise to more circulating currents. Hence output voltage of paralleledinverters must be strict in amplitude, phase and frequency to avoid large circulatingcurrents, which may damage the system. Some current sharing technique is required tominimize the mismatch in load currents among inverters. Also their is a need of slowDC bus control to use these parallel modules of inverters to harness energy from RES,which are running with MPPT.

In this chapter the interaction between inverters which are paralleled is analyzedand current sharing loop is designed. The DC bus control is also incorporated alongwithcurrent sharing by using a correction voltage. The current sharing loop and DC bus

47

*vop vop

∆Epiop*Qref

refP

Idcin

Vdc vop iop

iop

ic

Synchronised Reference Voltage − Same For All Inverters

Calculation Block

Kc

pK curr+ K curris

Averaging Block

iav

io1

P Inverter

∆vp

Vref*

inner loopActive Damping

H(s)

io2

iop

ion

Reactive Power Demand From Load

Power Input to DC Bus

M

From Different InvertersLoad Currents

+

Current Controller

+ +

+

++

++

+

Vdc

Vdc*

th

iLm


Plant

vi

P in

ControllerCurrent Sharing


iop

L s1

Rf

1

fC sf

Figure 4.1: Per phase schematic of Whole Control Strategy with Current SharingControl & DC Bus Control.

control loop will give correction voltages, which will be added to synchronized referenceframe.

The overall control schematic from section(1.5) is reproduced over here in g.4.1which includes current sharing control loop and DC bus control loop.

4.1 Design of Current Sharing Controller

The imbalance in currents shared by dierent inverters is unavoidable due to inherentparameter mismatch from their nominal values. The common reference for load currentof each inverter is generated by averaging unit, which is equal to the average of loadcurrents carried by all inverters. A simple proportional(P) controller suces the purposeto track this reference, as the plant for current control is line admittance with controlinput as Vo. Here the grid voltage forms the disturbance input. This is a rst orderplant with transfer function as shown below

Gind(s) =1

Rl + Lls(4.1)

where, Rl and Ll are line impedance parameters(including coupling transformer). TheP current sharing controller output gives the correction ∆V on top of synchronizedreference to track the command iav shown in Fig.4.1.

48

Bode Diagram

Frequency (Hz)

−80

−60

−40

−20

0

Mag

nitu

de (

dB)

101

102

103

104

105

−180

−135

−90

−45

0

Pha

se (

deg)

Figure 4.2: Bode Plot of Close Loop Transfer Function of VCVSI.

4.1.1 Analysis

The combination of inverter with LC lter and second order controller designed in pre-vious chapter can be used as controlled voltage source. The VCVSI with the designedvoltage loop controller can track any voltage reference, provided it is within its band-width i.e., 1300Hz. So the VCVSI can be represented by its close loop transfer functionof lter with voltage controller and active damping(Gclp(s)). Bode plot of this close looptransfer function is shown in g.4.2. It is evident from the bode plot that VCVSI actssimply as unity gain if inputs are within the bandwidth and the phase lag is not consider-able and can be avoided conveniently in analysis of other outer loops for current sharingand dc bus control without sacricing accuracy. The block diagrammatic representationof multiple inverters in parallel with their corresponding transformers feeding to grid andcurrent sharing controller is shown in g.4.3. A correction in voltage reference is addedto the reference of each VCVSI which is proportional to the error between instantaneousaverage of load currents from all inverters and the load current supplied by this specicVCVSI. The adequateness of simple proportional controller for instantaneous currentsharing is analyzed by taking the perturbed model of plant.

49

+

+

+

vo

vo

vo

vo

G (s)clp

G (s)clp

G (s)clp

G (s)clp

1Ll1l1R + s

1Rl3

Ll3+ s

1Rln

Lln+ s

v2*

v3*

vn*

v1*

v1

v2

v3

vn

++

+

+

+

Kcorr

Kcorr

Kcorr

Kcorr

avg

n

VCVSI

s

i+

+

+

+

∆v1

i1

i2

i3

in

iavg

iavg

iavg

iavg

i1

i2

i3

in

Summation

Zl

vo

1/niavg

AveragingBlock

Vo*

Vo*

Vo*

Vo*

Loadimpedance

io

1Rl2

Ll2+

∆ i1+

transformeradmittances

∆v2

∆v3

∆v

Figure 4.3: Block diagrammatic representation of multi-inverter system with currentsharing controller

In g.4.3 all VCVSI would have shared load currents equally if their lter, line andcontrol parameters were exactly identical and the correction in voltage reference wouldbe zero. But due to inherent mismatch in parameters and other non-idealities, therewill be mismatch in their currents. As shown for the rst inverter in g.4.3, apart fromaverage current(iavg) that each inverter should share for given load current, each inverterwill carry a perturbation current(∆in). The perturbation currents in inverters representthe mismatch of current shared by inverters from instantaneous average of load current.

Here the multi-inverter plant is represented by super-positioning of two plants -one with identical inverters sharing equal currents(iavg) and other carrying mismatchcurrents(∆in). These two portions of same plant can be analyzed separately, as theinverter with LC lter, transformer and voltage controller forms a linear plant. Thisassumption is valid, as far as modulation signals are maintained within unity.

This portion of plant is analyzed as if the perturbations are riding on top of idealplant in which currents are equally shared. From g.4.3, the perturbation in current

50

(s)clp

1Ll1l1R + s

∆ i1Kcorr

∆v1

G

Figure 4.4: Isolated perturbation model of any inverter in multi-inverter system.

shared by rst inverter is ∆i1 and the isolated perturbation model of rst inverter afterdropping the plant with identical voltages and currents is as shown in g.4.4.

All inverters will share equal currents if perturbation currents(∆in) will die down orsettles down to low value. From g.4.4, it is evident that this reduces to a regulatorproblem with rst order plant(assuming Gclp(s) = 16 00) and xed point reference aszero. As plant is high gain rst order transfer function, a small gain which makes systemstable is sucient and errors ∆in will die down eventually. Value of kcorr for P controlleris chosen to stabilize the close loop of g.4.4 and by considering the typical range of lineparameters values.

4.1.2 Simulation Results for Current Sharing

Fig.4.5 shows the current sharing by two inverters under dierent load transients simu-lated. The various perturbed parameters of two inverters used for simulation are givenin Table 4.1.

Table 4.1: Perturbed Parameter Values of Two Inverters Used For SimulationInverter - I Inverter - IILf Cf Lf Cf

Phase-A 0.75mH 52µF 0.61mH 50µFPhase-B 0.56mH 39µF 0.68mH 47µFPhase-C 0.68mH 47µF 0.56mH 47µF

Isolation Transformer ParametersXl 0.121 Ω 0.17 ΩRl 0.0363 Ω 0.0242 Ω

Simulated waveform of the correction voltage ∆V added to the reference Vref∗ (Fig.4.1)

for instantaneous current sharing is shown in Fig.4.6. It is to be noted that it contains

51

0 0.02 0.04 0.06 0.08 0.1−20

−10

0

10

20

Time(Seconds)

Phas

e A

(Am

p)

0 0.02 0.04 0.06 0.08 0.1−20

−10

0

10

20

Time(Seconds)

Phas

e B

(Am

ps)

0 0.02 0.04 0.06 0.08 0.1−20

−10

0

10

20

Time(Seconds)

Phas

e C

(Am

ps)

Inverter 1Inverter 2

Figure 4.5: Output Currents from three phases of two inverters superimposed oneach other - Shows sharing during load transient at t = 0.04sec and t = 0.06sec - Load

Resistance decreased by 80% at t=0.04 and again restored at t=0.06.

high frequency components which have to be tracked for proper sharing. This forms therequirement for designing inner voltage control loop with higher bandwidth of 1300Hz.These high frequency reference components ensure sharing of high order harmonics andhence instantaneous current sharing.

0 0.05 0.1 0.15 0.2

−0.5

0

0.5

Time(Seconds)

Del

ta V

(Vol

ts)

Figure 4.6: Waveform of Correction ∆V for Instantaneous Current Sharing - Containsfrequency components up to 1500Hz.

52

4.2 DC Bus Control

Most of the MPPT algorithms for RES systems invariably presume a constant or regu-lated DC link voltage within a small range irrespective of the amount of power deliveredby them[1]. Hence slow control on DC link voltage is required which is usually achievedby using auxiliary inverter to supply or extract power from DC bus to regulate itsvoltage[16]. Here the adding of correction ∆E to voltage reference as shown in Fig.4.1 isproposed to control the DC link voltage by controlling the active power drawn from DClink without any need of auxiliary inverter. Control of active power is means to controlidc of Fig.1.2 from ac side.

In Fig.1.2 the output voltages(Vo) are sensed and are fed back for the voltage con-troller. Utilizing these voltages, the instantaneous current references io

∗ for a given activepower ow are estimated. This active power is in turn calculated from the error betweenDC link voltage(Vdc) and reference(Vdc

∗) and from power input to DC link. Hence theproblem of controlling the DC link voltage reduces to control of output current, whichis current tracking problem. This is same as that of current sharing control describedin last section, but with reduced bandwidth. Here only fundamental reference is neededto be tracked. Also the idcin(current input from MPPT block) is approximated to beconstant for design purpose, as the variation of power output from MPPT is rather slowcompared to that in inverter module[17].

Current Reference Calculation

Power equation for three phase system in α− β domain is as shown:

p

q

=

voα voβ

−voβ voα

ioα

ioβ

(4.2)

where,p is instantaneous active power(W) ow andq is instantaneous reactive power(VA) ow.

References for output currents for given active and reactive power ow are obtained from

53

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8360

380

400

420

Vdc

(Vol

ts)

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.80

5

10

15

20

Time(Seconds)

I dc (A

mps

)

Reference of Vdc

ref = 380 Volts

applied at t=0.1 sec.

Momentary rise in DC link Current tofollow reference DC bus voltage.

Figure 4.7: DC link voltage Vdc response to step reference of 380Volts at t = 0.1sec andcorresponding DC bus current Idc delivered.

(4.3) which is direct consequence of (4.2).

ioα∗

ioβ∗

=

1

voα2 + voβ

2

voα −voβ

voβ voα

p

q

(4.3)

Reactive power q is obtained from the reactive power demand of load and referencefor active power p is derived from output of proportional-integral(P-I) controller andpower input to DC link as shown in Fig.3.6. Plant for current control is same, both forDC bus control and current sharing control.

4.2.1 Simulation Results for DC Bus Control

The DC bus tracking to a step reference of 380Volts at t=0.1sec and the correspondingincrease in Idc delivered to track reference is shown in Fig.4.7. It is noteworthy fromg.4.8 that the magnitude of correction ∆E for DC bus control is quite higher than itscounterpart ∆V and also it contains mostly the fundamental component of frequency.This is because of the fact that it is meant to control active power from AC side toregulate the DC bus voltage.

54

0.26 0.28 0.3 0.32 0.34 0.36 0.38 0.4

−10

0

10

20

Time(Seconds)

delta

E (V

olts

)

Figure 4.8: Waveform of Correction ∆E for DC bus voltage control - Contains mostlyfundamental frequency component (50Hz).


In this chapter the eect of voltage corrections added to synchronized reference forinstantaneous current sharing and DC bus control were discussed. Method to modelthe parallel inverters with mismatch in parameter is discussed with design of controlparameters for instantaneous current sharing. A method to control active power owthrough inverters to control DC link voltage was also discussed.

55

Chapter 5

Experimental Setup and Results

The instantaneous current sharing strategy and voltage controller loops described inprevious chapters have been implemented on two 5kVA inverters forming a weak grid.The grid is weak, because it has low short circuit fault supplying capability(low shortcircuit ratio). This situation essentially emulates the condition which is observed indistributed generation which predominantly utilizes RES. As grid is fed by inverters, itis weak and disturbances may induces voltage sag and distortions in the grid voltagewaveform. Delta-star 3-φ transformers have to be used to provide isolation and also asinverters are devoid of neutral wire they can not supply zero sequence currents requiredby unbalanced loads. Hence delta connected winding can be used at inverter side andstar at load side(grid side) to supply zero sequence currents to unbalanced loads. Rec-tier load is used to demonstrate the eect of loading and sharing of load currents byboth inverters during transients and steady state. Rectier loads are inherent distortivein nature, as they draw huge amount of harmonics from source. Hence they can beconsidered as worst possible load situation and are best suitable for demonstration ofeectiveness of instantaneous current sharing. Eectiveness of active damping is alsodescribed and the eect of change in values of kc is discussed in this chapter. A methodfor synchronizing the incoming inverter with the grid is also presented.

56

5.1 Experimental Setup

Fig.5.1 shows the basic layout of experimental setup. Altera Cyclone-I FPGA is usedas digital platform for the implementation of control strategy. It is programmed usingVerilog HDL with Quartus GUI available from altera website[26].

Two 5kVA Semikron inverters with built-in gate drivers are used for implementationof test setup. It generates four active low error signals corresponding to four limbs. A SCfault through any of the limbs forces the corresponding error signal to go low. Only threelimbs of inverters are utilized, as inverters are used as three phase three wire inverters.Each inverter has its own protection card which processes the PWM signals coming fromFPGA kit and also provides protection features like overload protection, shortcircuitprotection, DC bus undervoltage protection & overvoltage protection. Protection cardalso preprocesses the sensor outputs before giving it to ADC channels of FPGA kit. AnLED card is interfaced with protection card which indicates the type of fault wheneverit occurs and also it has start and reset switch. Current Sensor and voltage sensor cardsare fabricated and are used for the measurement of voltages and currents as indicatedin g.5.1. Outputs of sensors are carried to protection card through shield wires whoseshields are grounded equidistantly to avoid the distortion of signal information due toEMI(Electromagnetic Interference) eects. Further details about experimental setupand cards used are given in appendix.B.

All three output voltages of LC lters are sensed to convert them into alpha-beta axesinside FPGA. Whereas, only two load currents and two capacitor currents are sensed,as due to absence of neutral wire, the information regarding the third phase current isdirectly calculated by application of KCL. DC bus is maintained at 300 Volts by a singlephase rectier.

5.2 Experimental Results

In this section the experimental results are presented for robust P-I controller, secondorder voltage controller and instantaneous current sharing. The results are comparedwith their analytical counterparts in this section. DC bus voltage is maintained at

57

VSCard

PWM signals

Lf

fC

3

dc

R

Y

B

Weak Grid formed by Parallel Inveters

Digital I/O Pins

Altera Cyclone −I FPGA Board(EP1C12Q240C8)

4 Analog O/P Channels(12−bit DAC)16 Analog I/P Channels(12−bit ADCs)

16 10

To Oscilloscopefor debugging

14 2

Protection Cards for two Invertes

LED Cardwith Start/Reset Switch

PWM signals

3

LC Filter

LC Filter

CS Card−2

a b c a b c

DiodeRectifier

ResistiveLoad

SW1 SW2

SW3

Six Voltage Sensor Cards

CS Card−1

ica1

2 x 5 KVA SemicronInverters with builtin Gate Driver

3−ph

ase

Del

ta−

Sta

r T

rans

form

er

3−ph

ase

Del

ta−

Sta

r T

rans

form

er

V

ica2icb2

ila2ilb2

ica1icb1

ila1ilb1

ica2icb2

ila2ilb2

ilb1ila1

icb1

ic

il

1vb 1vca1v a2v vc22vb

a1v 1vb 1vc a2v 2vb vc2

a2v 2vb vc2a1v 1vb 1vc

300 V DC Link

Figure 5.1: Layout diagram of test setup of parallel inverters with LC lter.58

Figure 5.2: Reference(red) and Output Voltage(blue) for phase-A and kc = 3Ω.

300Volts, so the peak of ac voltage that can be achieved without over-modulation isVdc/2(=150V). Here the peak ac voltage is restricted to 110 volts in steady state, toprovide some margin for overshoot during transients. Also, as the system is linear, itcan be tested for any voltage level and current level as long as modulation signals aremaintained within limit.

5.2.1 Robust P-I Controller

Fig.5.2 shows the reference and actual voltage without any load with the designed robustP-I controller described in section.3.5.1. It can be seen that there is large phase lagbetween reference and output voltage as expected. This is due to low bandwidth of innerloop. The experimental result is same as simulated one shown in g.3.11. Step responsewith direct application of reference is shown in g.5.3. Dynamics during switching ofload are shown in g.5.4.

59

Figure 5.3: Step response to application of reference.

Figure 5.4: (a) Output Voltage(50V/div) (b) Load Current(5.55A/div).

60

Figure 5.5: (a) Phase-A Capacitor current(0.44 Amp/div) (b) FFT(5kHz/div).

5.2.2 Active Damping

Fig.5.5 shows the capacitor current with no load operation. It can be seen as there areno disturbances like load, it contains only switching frequency components. Whereas,g.5.6 shows capacitor current when VCVSI is supplying a rectier load. As rectier loadinduces transients, the resonant frequency components can be observed in the waveform.This information of capacitor current near resonant frequency is used for active dampingto decrease the eective resonant peak, imparting stability to whole voltage loop. Lowervalues of active damping constant(kc) will make system underdamped and it hampers therelative stability of the system. Also with low kc values, oscillations will take longer timeto die out. Whereas, higher values of it will make system non-linear during transients.So judicious selection of damping constant is necessary. Fig.5.7 shows the eect ofremoving active damping on the output voltage waveform quality. Not only it introducesharmonics in system, but also it increases the loses in passive components. This explainsthe importance of damping in inherent undamped systems like LC lter. They dampthe destabilizing transients without incurring extra loses, which would have occurred ifpassive damping had been used.

61

Figure 5.6: (a) Phase-A Capacitor current(2.22 Amp/div) (b) FFT(250Hz/div).

Figure 5.7: Output Voltage without active damping(50 V/div).

62

Figure 5.8: Step response of 2nd order voltage controller(50 V/div).

5.2.3 Second Order Voltage Controller

It is evident from results and analysis of robust P-I controller that its bandwidth islower and has phase lag between output and reference. This renders it useless as innervoltage loop for instantaneous current sharing. Hence a second order voltage controllerwith higher bandwidth is designed and implemented and its experimental results arepresented in this section.

Fig.5.8 shows the step response of controller to the sinusoidal reference with peak of110 Volts. The output voltage follows the reference with very small lag. Also transientsdie out rapidly due to presence of active damping. This shows the conrmation betweendesign and experimental implementation.

Fig.5.9 and g.5.10 demonstrates the performance of controller without load andwith rectier load respectively. Fig.5.11 shows the corresponding load current.

Three phase output voltage is shown in g.5.12.

63

Figure 5.9: Reference(red) and Phase-A Voltage(50 V/div)(blue) without load.

Figure 5.10: Reference(red) and Phase-A Voltage(50 V/div)(blue) with load.

64

Figure 5.11: Load Current - phase A(1.2 Amp/div).

Figure 5.12: Three phase output Voltages.

65

5.2.4 Synchronization of Inverters

The synchronization of an incoming inverter with the operating inverter is analysed.A method to reduce the voltage dierence between the operating and the incominginverters is discussed. This emulates the situation similar to that of synchronizationof inverter with weak grid in distributed generation. In order to prevent a disturbanceduring connection of incoming inverter, it has to be synchronized with the operatinginverter prior to closing the switch. Extra voltage is injected to incoming inverter tosynchronize it with operating inverter before closing the paralleling switch. Voltageacross the switch is decreased by extra voltage injection.

Before bringing VCVSI's in parallel they must be properly synchronized to avoid largetransients or fallout of inverter. The dierence between output voltage of two VCVSI willbe there due to inherent parameter mismatch. As the magnitude of transformer leakageimpedance is very low, even a small voltage dierence will give rise to huge circulatingcurrent. In g.5.1 the SW1 is closed and inverter-1 is supplying to grid and load isnot being supplied before bringing the other inverter. Both switches SW2 and SW3 areopen. Before bringing the second inverter and switching on SW2, it is synchronized withgrid to avoid the circulating currents.

Fig.5.13 shows the voltage dierence between phase-A voltages of both inverter run-ning with same reference and which are not yet paralleled. It can be seen from waveformand corresponding FFT that the voltage dierence consists of frequency componentswhich are well within the bandwidth of second order controller used. The dierence islarge enough to induce huge circulating currents. As voltage dierence is within thebandwidth of VCVSI, a extra voltage can be injected in incoming inverter to counterthis dierence and reduce it. Switch SW2 is closed after counteracting the voltage dif-ference. The voltage dierence has reduced to good extent after inclusion of injectionvoltage. Fig.5.14 shows the voltage dierence between output of both VCVSI's afterinclusion of correction voltage in inverter-2. With the reduction in dierence of voltage,the SW2 can be closed to parallel both inverters to share load equally. The transformersare not included in the test setup thereby emulating a worst condition. Due to absenceof transformer leakage impedances, the circulating currents will tend to be larger.

66

Figure 5.13: (a) Voltage dierence between two VCVSI outputs running onsynchronized reference(2.50 V/div) (b) FFT(500mV/div, 50Hz/div).

Figure 5.14: (a) Voltage dierence between two VCVSI outputs running onsynchronized reference(2.50 V/div) after inclusion of correction voltage (b)

FFT(100mV/div, 50Hz/div).

67

Figure 5.15: Current sharing during switching on of load(1.5Amp/div).

5.2.5 Instantaneous Current Sharing

Fig.5.15 shows the current sharing for phase-A during switching of rectier load fromno-load to full-load. Load current is shared equally, not only during steady state butalso during transient of switching. Fig.5.16 shows the current sharing during increase inload from 1.5A peak to 3A peak.


Experimental results are performed with various load currents and with various voltagelevels. Also the explained method for instantaneous current sharing holds for all ratingsof inverters as inverters with LC lters form linear plant. A method for synchronizationhas been explained and implemented in this chapter. Hardware results verify the designfor current sharing controller designed.

68

Figure 5.16: Current sharing during load transients(1.5Amp/div).

69

Chapter 6

FPGA based Control andImplementation

Signals in physical world, like voltages and currents are large in magnitude and theycannot be represented as they are, in digital platforms like micro-controllers, DSPs,FPGAs etc. FPGA provides exibility of design as its logic units can be optimally usedaccording to the user requirements. ADCs are used to convert the real world analogsignals into digital signals which are conceivable by FPGA. There are various issues likeselection of gain for sensors(voltage sensors and current sensors), base values for voltageand current, sampling sequence, selection of number format, conguration of digital pinsfor interface and others, which have to be considered while implementing the controlalgorithm designed in continuous domain into digital domain. Also the algorithm owin FPGA is needed to be analyzed before implementation. All these issues are discussedin this chapter.

6.1 Control Platforms

The controller can be implemented in following ways.

• Analog platform

• Digital platform

70

6.1.1 Analog platform

Controllers can be implemented using passive components such as resistor, capacitorand active devices such as operational ampliers. These type of controllers sense thequantities from the system as analog voltage and also takes reference as analog voltagesand produces control input to the excitation device. This type of controllers are calledas analog controllers. For dierent applications controllers has to be separately designedbecause same controller cannot be recongured for dierent applications. This willincrease the time to build the prototype.

The advantages of analog controllers are:

• Low cost if the controller is simple.

• Easy interpretation of control strategy in analog domain.

The disadvantages of analog controllers are:

• Recongurability of the control is not possible without changing the hardware.

• Number of passive components used are more.

• More sensitive to variations in temperature.

• Reliability of the system is low because no. of components used is large.

• Variations in parameter values with time largely aect the accuracy of system.

• Noise immunity is poor.

One of the recent advancements in the eld of analog control platforms are FieldProgrammable Analog Arrays (FPAA).

6.1.2 Digital platform

In recent days, the usage of digital controllers has considerably increased in the eldof Power Electronics and Drives. The controllers can be realized in digital domainusing Microcontrollers, Digital Signal Processors(DSP), Field Programmable Gate Ar-rays(FPGA), Application Specic Integrated Circuits, etc.

71

Advantages

• They are highly exible as all the control algorithms are software programs. Thustwo or more control algorithms can be stored in the same hardware and can beindividually implemented depending on the control requirement.

• It enables better monitoring of the system. Features like data logging and super-visory control can be incorporated in digital control systems, for debugging anddiagnostic purposes.

• Digital control is the best suited for modular systems, as it is easy to interpret thesystem as an integration of dierent modules. This is possible by decoupling thecontrol algorithms of the dierent modules. For example it is possible to turn OFFthe current sharing loop to see the eect of parallel operation of inverters withoutany compensation for circulating currents.

• It is possible to implement complex non-linear control algorithms like neural net-works, fuzzy logic or genetic algorithms in digital control platforms.

Disadvantages

• The major disadvantage is the delay in the control introduced due to the signalprocessing stage of the digital platform. Also the limited speed of ADCs canfurther increase the delay produced.

• A limited word length in most of the processors imposes a limit on the signalresolution.

6.2 Features of FPGA Board

Field Processed Gate Array (FPGA) is a semiconductor device made up of an array oflogic elements (LE) as their building blocks. Each logic element is made up of a numberof hardware resources like gates, ipops, decoders, counters etc. The LEs are wiredevery time to realize the required logic. This is the major advantage of FPGA over DSP.In the case of DSP, the architecture is xed and hence there are a limited number of

72

resources. However the FPGA provides resources for the user in a more abstract level.With these resources any specic hardware like DSP/microcontrollers can be conguredin an FPGA. Further unlike DSP, the FPGA allows parallel processing of data. Thenumber of LEs in an FPGA indicates the logic density of the FPGA and it depends onthe manufacturer.

In FPGA, unlike DSP, number of algorithms can run in parallel and it allows algo-rithm to run in parallel and decrease the total execution time. Hence for same algorithmFPGAs need less execution time and they can use higher sampling rates compared toDSPs, imparting more exibility in design.

Figure 6.1: FPGA Board Block Diagram

The block diagram of FPGA board used is shown in g.6.1. This digital platformconsists of cyclone FPGA, conguration device (EEPROM) and other interfacing devicessuch as Analog to Digital Converter(ADC), Digital to Analog Converter (DAC) anddigital I/Os which are dedicated I/O pins of the FPGA device. ADC and DAC arealso interfaced using dedicated I/O pins of the FPGA device. For control of powerelectronic systems, analog signals such as voltages and currents must be sensed. HenceADC is required. Sometimes there may be need to send control output in analog form,

73

so DAC is required. DAC can also be used to view some digital signals in analog formfor debugging purposes. Digital I/Os can be used for control output such as gatingpulses to power converter, and also it can be used to interface devices such as ADC,DAC, LC display, keyboard etc. Also this I/O pins can be used for providing digitalinformation, like status of RESET switch or start SWITCH to control strategy. Theseare the minimum requirements of the FPGA based digital platform for control of powerelectronic systems.

The important features of the FPGA board used are:

• Altera Cyclone EP1C12Q240C8 FPGA with 12k Logic Elements

• 16 channels of 12bit, simultaneous sampling ADCs for reading analog signals. Outof this 16 channels available, 15 channels are used for sampling purpose to measure8 currents signal, six ac voltage signals and one DC bus voltage signal as shown ing.5.1. Conversion time is 1.64µS per channel.

• 4 DAC channels of AD5447, 12-bit DAC with 2 channels per chip. DAC is primarilyused for monitoring and debugging purposes.

• Congurable Digital I/O pins that are used as gating signals for IGBTs, othercontrol and communication signals.

The FPGA board is interfaced to PC parallel port with a programming cable calledByte Blaster Cable. This cable is used by the Quartus development tool on PC tocongure the FPGA.

6.3 FPGAModules for Power Electronics Applications

The implementation of a controller for power electronic applications requires develop-ment of several basic modules which perform control and communication operations.Some of the basic modules required are listed below:

• Interfaces for ADCs and DACs

• Filters and other DSP modules like controllers and lead/lag compensators.

74

• Transformation Blocks like abc-αβ and vice-versa.

• PWM Generator

• RS232 and other Communication modules

• User Interface modules like LCD, Keypad Interfaces

• Reciprocal module.

• Sine-cosine generation module.

• Three phase free running reference generator.

• Per-unitization block.

This modules are developed using Altera GUI software(Quartus) and Verilog HDLand are tested oine before including them for nal control algorithm.

6.4 Implementation of Control System in FPGA

Figure.6.2 shows the data ow and implementation of control system for instantaneouscurrent sharing scheme for two inverters in alpha-beta domain on FPGA. Arrows repre-sent the ow of data from module to module. The number in parenthesis in each modulerepresents the number of those modules actually used there. Sampling frequency chosenis 20kHz and hence sampling period is Ts = 50µs. Hence all computations for updatingof modulation signals must have execution time less than 50µs. Synchronized referenceblock generates the free running three-phase reference of 50Hz frequency and speciedamplitude. Data acquisition block samples all analog sensor outputs at sampling fre-quency fs and converts them to digital variables.

6.4.1 Selection of Base Values

All computations within FPGA and representation of numbers are done using xedpoint representation. The 4.12 format is used for representation and details regardingthis number format are explained in appendix.A. In 4.12 format, we can represent any

75

activ

eab

c2αβ

mod

ule

abc2

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odul

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Thr

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abc2

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e (1)

gene

ratio

nm

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ge r

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grat

orm

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abc2

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Fun

dam

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lF

requ

ency

+−

+−

(2)

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com

pens

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lead

mod

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+−

activ

eda

mpi

ngab

c2αβ

mod

ule (1

)

mul

tiplie

r (1)

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M

++

gene

ratio

nm

odul

e(1

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reci

proc

alm

odul

e(1

)

+−

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mul

tiplie

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++

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Figure 6.2: Control Implementation in FPGA76

fractional number from -8 to +8 with resolution of 1/(212). All calculations are done inper unit, with proper selection of base values. As all variables must remain within therange of ±8 during steady state as well as dynamic condition to avoid overow errors.Proper base values are required to be selected to retain variables within limit. Voltagebase value is chosen as 100Volts, so that any voltage signal can go upto 800volts withoutoverow. For 300Volt dc bus system, this limit is suciently higher to avoid overoweven during dynamic conditions.

Assuming 25Amps to be maximum current that may appear in the system, thecurrent base value is chosen as 8Amps. This allows to represent current component ofupto 64Amps without any overow and this limit is suciently higher for give setup.

6.4.2 Sensor Gains

Voltage sensors have congurable gain which can be varied by adjusting the resistancevalues of its potential divider. Gain of voltage sensor is limited by the range of ADC usedin FPGA. ADC-7864 can take analog signal in the range of ±10V [25]. Hence outputof voltage sensor must be limited to 10V in either direction. The sensor gain must notbe very low for given range of input voltages, otherwise the inputs to ADC will getrestricted to a narrow range and hampering the resolution.

Sensors which are used to measure ac phase voltages are set with gain of 0.045 andhence they can sense signal upto 10/0.045 = 222Volts. Sensor for DC link voltage is setwith gain of 0.01 and it can measure dc link voltage upto 10/0.01 = 1000Volts.

Current sensors gain is 0.45 and hence it can sense current upto 10/0.45 = 22Ampswithout any overow error. This range is sucient for application.

6.4.3 Per-unitization Block

The gains of sensors are tuned, considering the current and voltage levels of system, toutilize the full range of ADC. This decreases the quantization errors in system. AlsoADCs convert the analog signals of range ±10V into digital numbers of 12bit width.Outputs of ADC are represented in 2's complement form from -2048 to 2047. HenceADCs have their own gain, while converting analog signals to digital signals. These

77

sensor and ADC gains are needed to be considered to get the information of analog signalin required per unit form. The output of ADCs are multiplied by proper multiplicationfactor to get the signal in p.u. form with specied base value for further computation.

Multiplication factor for any sensor or analog channel is given by

M.F. =(2F − 1)× 10

Base value × sensorgain × 2047(6.1)

where, F is number of bits used for representation of fractional part of variable. In 4.12,F is equal to 12.

Per-unitization block is used to convert outputs of ADCs to p.u. with selected basevalues for voltage and current.

6.5 Serial and Parallel Implementations on FPGA

All the modules mentioned in the previous sections can be implemented either in parallelor serially. The choice of implementation depends on whether the design has to beoptimized for speed or resources. Parallel implementation decreases the time requiredfor processing, but consumes more resources. Purely parallel implementation can be usedin cases where simple algorithms have to be implemented in realtime at high samplingrates like for analog to digital conversion of all sensor signal is done simultaneously. Thealgorithm is designed considering these factors and also retaining its execution time lessthan sampling period Ts(50µs).


This chapter begins with the discussion of advantages of digital platform for implemen-tation of control system. Features of FPGA kit are also discussed. The issues regardingimplementation of control system on FPGA were discussed alongwith criteria regardingselection of base values, sensor gains and multiplication factors.

78

Chapter 7

Conclusions

The electricity sector is subject to important changes, aecting all aspects of the valuechain. The liberalization of the electricity market, coupled with the unbundling of thegeneration, transmission, distribution and supply functions has led to dramatically dif-ferent dynamics driving the formerly vertically integrated power system. In addition,new distributed and renewable electric energy sources are entering the market, with ma-jor promises for future growth. Technological advances are driving their developments.Moreover, dwindling fossil fuel resources in conjunction with environmental concernsfurther accelerate the growth of renewable technologies. These new sources are dierentfrom most existing generation sources as they are much smaller, but numerous, oftenconnected to low or medium voltage lines and with often intermittent generation mostlydependent on external factors. Therefore, they pose signicant challenges to the futureoperation of the grid. This work aims at contributing to the search for solutions to thesechallenges.

7.1 The Present Work

The main focus is on the reliable operation of low voltage grids with many, small gen-eration units with variable output. As these distributed generators are nowadays in-creasingly equipped with a voltage source inverter as front-end, further focus is on theoperation of these inverters to enable them to contribute to the operation of the grid.The large control exibility that voltage-source inverters provide is fully exploited here.

79

Inverters are best suited to extract power from RES and process it according to the gridor domestic load requirements. Scheme for parallel operation of VSIs is demonstratedin the present work.

Approaches used these days to control VSIs are reviewed and used for further designenhancement. Concept of active damping is used for design of inverter control whichimproves power eciency as well as control eciency. High eciency is desirable whileharnessing energy from RES. Experimental behavior of eect of active damping is studiedand its importance in damping oscillations caused by dynamic conditions is analyzed.

Step-by-step design is explained for inverter control with explanation of two methodsviz., robust P-I controller and high bandwidth second order voltage controller. Depen-dence of design of outer-loops for parallel operation on bandwidth and gain of innerloop is discussed. Specications required to be match the design of voltage controller forparallel operation of inverters with instantaneous current sharing are described. Samevoltage control techniques can be used to use inverter for other purposes like STATCOM,UPQC, DVR etc. in power systems.

Application of parallel voltage controlled VSIs as interfacing link between grid andRES is demonstrated. DC link voltage control is included in control algorithm, whichavoids the need of extra converter to support dc link. A new method is devised onthe basis of small signal model for analysis of interaction among inverters, operating oninstantaneous average current sharing scheme. This method not only provides analyticalinsight to system stability but also gives a method for design of current sharing controller.Use of perturbation model to analyze system is demonstrated. Experimental responseof designed current sharing controller is veried with rectier load and behavior duringtransients in load is also studied. Specic controls for each VSI are devised to retain themodularity in the system. Decentralized control imparts extra reliability to micro-gridformed by dierent RES due to absence of complicated communication infrastructure.

Synchronization of inverter with operating inverter is analyzed with method to de-crease the voltage dierence between the operating inverter and incoming inverter. Thisemulates the similar situation as synchronization of inverter with weak grid in distrib-uted generation. Extra voltage is injected to incoming inverter to synchronize it with

80

operating inverter before closing the paralleling switch. Dynamics of voltage acrossparalleling switch are studied for voltage injection.

Information of interest in signals lies in the range from 0 to 1500Hz. But the delaysintroduced by sampling in this range of interest, impedes the use of switching frequencyin the range of 5kHz to 20kHz. The method for compensation of this delays is includedand the use of low switching frequency is made possible for instantaneous current sharing.

FPGA is used for the implementation of controls and its parallel processing featureis exploited for faster computations. Basic control and transformation modules areprepared in Verilog HDL for use in power electronic applications.

Observations and design is summarized as follows.

• Control exibility of inverters is exploited with various control methods.

• Active damping is demonstrated with the eects of variation of damping constant.

• Specications of voltage controller are discussed with design of inner-loop for in-stantaneous current sharing scheme.

• Analysis of outer-loop design and their stability analysis is explained.

• Current sharing and dc bus voltage control is designed.

• Inverters are synchronized through voltage injection.

• Generalized and modular controls for parallel inverters are proposed and imple-mented which gives decentralized control.

• This reduces the communication infrastructure and improves reliability of system.

7.2 Scope for Future Work

Experimental behavior of dc link voltage control is required to be studied. Eect ofislanding and connection of inverters is not studied in this thesis. The operation ofparallel inverters in conjunction with grid imposes extra problems like synchronizationand dynamic behavior during magnitude and phase jump of grid voltage. This can be

81

taken care of by making the link between grid and inverters more stier and it can beanalyzed further.

The method for tuning P-I controller based on robust stability and performancecriteria has shortcoming of less bandwidth required for this specic application. Thismethod can be explored further by parameterizing higher order controllers for acquiringhigher bandwidth retaining the robustness of the system. Also inclusion of weightingfactor to design controller on the basis on dierent weightage to dierent performanceindices is suggested.

82

Appendix A

Fixed Point Representation of RealNumbers

A.1 Selection of Number Format

The Fixed point representation has been used for performing all the computations inthe FPGA. All the sensed quantities and internal constants are converted to xed pointnumbers by the choice of a suitable number format and proper scaling. A number formatis a convention used to represent the xed point number in binary number system,splitting it to an integer portion and a decimal portion. Q[I][F] is a xed point numberrepresented in binary logic. 'I' is the total number of integer bits and 'F' is the totalnumber of fractional bits. 'I' integer bits can represent numbers within a range of −2(I−1)

to 2I−1−1/(2F ), with a resolution of 12F . Thus any decimal number 'x' within the range

of −2(I−1) to 2I−1 − 1/(2F ) can be represented in xed point binary notation as,

Q[I][F ] = x ∗ 2F (A.1)

In order to implement the designed PI controller, second order controller and other digitalsignal processing blocks, the Kp, Ki and other constant values have to be representedin the xed point format. In active damping Kc is not constant, but it represents theamount of virtual resistance inserter in series with capacitor and its unit is Omega(ohm).Hence it is converter to per-unit by diving its value with Zbase. The maximum valuewhich is required to represent in FPGA is 3.58 of second order controller. In order torepresent this quantity, 4.12 number format has been chosen, since it can be used to

83

represent any number within the range of ±8. Accordingly, the following convention isused to represent a oating point variable in 4.12 format,

7FFFh −−− > +8... ...

5FFFh −−− > +6... ...

3FFFh −−− > +4... ...

1FFFh −−− > +2... ...

0000h −−− > 0... ...

E000h −−− > −2... ...

C000h −−− > −4... ...

A000h −−− > −6... ...

8000h −−− > −8

Now any equation can be converted into per unit form with 0FFFh as 1 pu. The basevalue must be chosen in such a way that the maximum value of that variable does notexceed 8pu.

84

A.2 ADC Conversion

Input range of the ADC s (AD 7864 ) used in the FPGA kit is ±10V . This is a 12-bitADC. The following table illustrates 16-bit equivalent word for input range ±10V .

ADC input 12-bit ADC output equivalent 16-bit ADC output p.u.value

+10V 7FFh 7FFFh 8pu... ... ... ...

+7.5V 5FFh 5FFFh 6pu... ... ... ...

+5V 000h 3FFFh 4pu... ... ... ...

+2.5V 1FFh 1FFFh 2pu... ... ... ...

0V 000h 0000h 0pu... ... ... ...

−2.5V E00h E000h −2pu... ... ... ...

−5V C00h C000h −4pu... ... ... ...

−7.5V 1FFh A000h −6pu... ... ... ...

−10V 800h 8000h −8pu

So, (equivalent 16-bit ADC output) = (12-bit ADC output) ×24.

A.3 PI Controller Design

In frequency domain a PI controller block diagram is shown in Fig.A.1.

85

Figure A.1: PI Controller

The integral part of the controller can be represented as

Y1(s) =KI

sU(s) .

Now to transform it into discrete-time domain, bilinear transformation is used, i.e.,

s =2

T

(1− z−1

1 + z−1

).

So,

Y1(s)

U(s)=

KI

s

⇒ Y1(z)

U(z)= KI

T

2

(1− z−1

1 + z−1

)

⇒ (1− z−1)Y1(z) =KIT

2(1 + z−1)U(z)

⇒ y1[k]− y1[k − 1] =KIT

2[u[k] + u[k − 1]]

⇒ y1[k] = y1[k − 1] +KIT

2[u[k] + u[k − 1]]

(A.2)

The proportional part of the controller is represented as

Y2(s) = KP U(s) .

Its discrete time equivalent is given by

y2[k] = KP u[k]

where,KP is the proportional constant, KI is the integral constant, T is the Sampling time, U

is the input and Y is the output of the controller.

86

The discrete equivalent of the PI controller is written as

y[k] = KP u[k] + y1[k − 1] +KIT

2u[k] + u[k − 1] (A.3)

where, y1[k−1] is initial condition of the integrator, during kth switching interval. (A.3)is used in the FPGA to implement a PI controller.

87

Appendix B

Specications of Hardware Modules

Fig.B.1 shows corresponding hardware setup and g.B.2 shows the FPGA kit used withinterface cards.

Filter setup is shown in g.B.3.

B.1 Protection Card

Protection card is mainly designed for protection of inverter from overload, overvoltageof DC bus, undervoltage of DC bus and inverter-leg shoot through (short circuit) fault.All logic functions are implemented on this card. Overload protection for all phases ofinverter is also included. It also activates a relay to bypass charing resistors when dc busvoltage reached a set value of normal voltage. The charging resistors avoid large inrushcurrent curing switching of dc bus on sti dc source for charging it. Features

• Fault detection settings

Overvoltage of DC bus > 350 V

Undervoltage of DC bus < 100 V

Overload of each phase of inverter > 12 A (rms)

Short circuit of inverter

• DC bus charging resistor is bypassed if DC bus voltage exceeds 150V.

• Introduces dead time of 1.5µs between switching of top and bottom switches ineach leg.

88

Figure B.1: Experimental Setup for parallel inverters with LC lter

Figure B.2: Altera Cyclone-I FPGA kit with Interface card

89

Figure B.3: Three phase LC lters for two inverters.

• All feed back signals to FPGA are passed through clamp circuits which clamp thevoltage to ±10V.

• The manual reset push-button is provided to clear the faults.

• PWM signals to all gate drives can be disabled manually by switching the SPSTswitch provided with card.

Design notes

• TL084 (JFET input op-amp) is used as overload hysteresis comparator since it hasfast slew rate compared to commonly used op-Amps for proper operation of edgetrigger latch.

• HCPL 3100(propagation delay 1µs) is used as level converter for PWM signalsbecause it has very fast rise and fall times compare to op-amp, which has very lessslew rate.

• Low resistance (100Ω) is used in R-Z clampers in order to avoid high currents

90

during clamping and it does not shift anti-aliasing lter (sample-hold) corner sig-nicantly.

• Buer circuit is used at input of relay to supply current needed for relay operation.

B.2 Interface Card

Interface card has been designed for buering the inputs to ADCs. RS232 commu-nication transceiver is also included to enable communication between FPGA and aComputer or any other serial device. The I/O pins are made accessible to user throughconnectors. Two Flat Ribbon Cable Connectors(FRC) are provided for connecting themto two protection cards for two inverters. All sensor signals from protection card arebrought to the FPGA through this connector. PWM signals are also sent to protectioncard through this connector.

B.2.1 ADC Buer

The inputs to the ADCs come from voltage and current sensors. To prevent any loadingeect on sensor cards, the inputs to ADCs are buered using op-amp buers. Theoperating range of ADC inputs are ±10V . So an RZ clamping circuit is used to protectthe ADC from voltages above ±10.7V .

B.2.2 Power Supply

The FPGA board requires ±12V power supply for operation. A power supply sectionis also included in the interface card to provide a regulated ±12V supply to the FPGAboard as in g.B.5. The power supply section also provides regulated +5V supplyrequired by FPGA kit.

B.2.3 FRC Connector

Two 20-pin Flat Ribbon Cable connectors are provided which are used to directly connectthem to the protection cards of two inverters. It is used to bring the voltage and currentsensor signals to the interface card and send PWM signals to the protection card.

91

Figure B.4: ADC buer circuit

B.3 Voltage Sensor Card

Features

• Designed for 222V AC or ±1000V DC

• Optical isolation using isolation amplier HCPL-7800A

• Can be congured to measure maximum of 1kV.

• Linear operation over entire range.

• Can measure frequencies up to 25 kHz without phase error and measure frequenciesup to 85 kHz with 45 phase error. Ac voltage sensors gain is 0.045 and dc busvoltage sensor gain is 0.01.

Design Notes

• Fly back power supply operates at 10 kHz and this noise is attenuated by providinglarge ground plane in PCB.

• The range of measurement can be varied up to a maximum of 1kV by selecting theresistor values in the potential divider network.

92

Figure B.5: Power Supply portion circuit

B.4 Current Sensor Card

Electrical current sensors measure AC/DC current levels.Features

• Primary current : 22 A(rms)

• Loop Type : Closed loop

• Maximum AC Frequency : 10 kHz

• Maximum error (% ) : 0.309

• Temperature of the primary conductor (Max) : 90C

• Current to voltage conversion ratio : 0.45 Ω

• Oset voltage of output side : 5.695 mV

Design notes

93

• Card receives current inputs and provides outputs as analog voltage signals.

• Hall eect based closed loop current sensors used to avoid saturation problem.

• Op-amp LM324 used for scaling and ltering.

• Secondary to primary turns ratio 1000:5

• Linear operation over entire range

94

References

[1] Eftichios Koutroulis and Kostas Kalaitzakis, "Design of a maximum power trackingsystem for wind-energy-conversion applications," in Proc. of IEEE Transactions onIndustrial Electronics, April-2006, pp. 486-494.

[2] Josep M. Guerrero, Luis García de Vicuna, Jose Matas, Jaume Miret and MiguelCastilla, "A high-performance DSP-Controller for parallel operation of online UPSsystems," in Proc. of Applied Power Electronics Conference and Exposition, 2004.APEC '04, pp. 463-469.

[3] K. De Brabandere, B. Bolsens, J. Van Den Keybus, et al., "A voltage and frequencydroop control method for parallel inverters," in Annual IEEE Power ElectronicsSpecialists Conference, 2004, pp. 2501-2507.

[4] Josep M. Guerrero, José Matas, Luis García de Vicuña, Néstor Berbel and JorgeSosa, "Wireless-control strategy for parallel operation of distributed generation in-verters," in proc. of IEEE Transactions on Industrial Electronics, June-2005, pp.846-850.

[5] Mukul C. Chandorkar, Deepakraj M. Divan and Rambabu Adapa, "Control ofparallel connected inverters in standalone ac supply systems," in Proc of IEEETransactions on Industrial Applications, January/February-1993, pp. 136-143.

[6] S. Y. Yang, C. W. Zhang, X. Zhang, R. X. Cao, W.X. Shen, "Study on the controlstrategy for parallel operation of inverters based on adaptive droop method," inproc. of IEEE Conference on industrial electronics and applications, May-2006.

95

[7] Jiann-Fuh Chen and Ching-Lung Chu, "Combination voltage-controlled andcurrent-controlled PWM verters for UPS parallel operation," in Proc. of IEEETransactions on Power Electronics, September-1995, pp. 547-558.

[8] Zhang Chunjiang, Chen Guitao, Guo Zhongnan and Wu Weiyang, "An alternating-master-salve parallel control research for single phase paralleled inverters based onCAN bus," in Power Electronics and Motion Control Conference, 2006. IPEMC'06..

[9] Xiao Sun, Yim-Shu Lee and Dehong Xu, "Modeling, analyis, and implementation ofparallel multi-inverter systems with instantaneous average current sharing scheme,"in Proc. of IEEE Transactions on Power Electronics, May-2003, pp. 844-856.

[10] Rihui Xiong, Yunfeng Lee and Jixiang Zhao, "Modeling and analysis of stabilityfor parallel inverters operated with instantaneous maximum current control strat-egy," in Proceedings of IMACS Multiconference on "Computational Engineering inSystems Applications"(CESA), Beijing, China, October-2006, pp. 1701-1706.

[11] Junggi Lee, Jaihong Kim, Jungmin Kwon and Kwanghee Nam, "Two DOF con-troller for parallel operation of fuel cell power generator with power grid," inProc.Industry Applications Conference, 2005, pp. 585-590.

[12] Michael J. Ryan and Robert D. Lorenz, "A high performance sine wave invertercontroller with capacitor current feedback and "Back-EMF" decoupling", in Proc.of IEEE Transactions, 1995, pp. 507-513.

[13] Michael J. Ryan, William E. Brumsickle and Robert D. Lorenz, " Control topologyoptions for single-phase UPS inverters," in Proceedings of IEEE Transactions onIndustrial Applications, March/April-1997, pp. 493-501.

[14] Naser M. Abdel-Rahim, and John E. Quaicoe, "Analysis and design of a multiplefeedback loop control strategy for single-phase voltage-s ource UPS inverters", inProceedings of IEEE Transactions on Power Electronics, JULY 1996, pp. 532-541.

96

[15] Atsuo Kawamura, Toshimasa Haneyoshi and Richard G. Hoft, "Deadbeat controlledPWM inverter with parameter estimation using only voltage sensor", in Proceedingsof IEEE Transactions on Power Electronics, April 1988, pp. 117-125.

[16] Dong-Choon Lee, G-Myoung Lee and Ki-Do Lee, "DC-Bus voltage control of Three-Phase AC/DC PWM converters using feedback linearization," in Proc. of IEEETransaction on Industry Applications, May/June-2000, pp. 826-833.

[17] Pedro G. Barbosa, Luis G. B. Rolim, Vladmir V. Tavares et al., "Novel control strat-egy for grid-connected dc-ac converters with load power factor and mppt control,"in IEEE Proc. on Generation, Transmission and Distribution, Spetember-1998, pp.487-491.

[18] Sato Y. Kataoka T, "A current-type PWM rectier with active damping function,"IEEE Transactions on Industrial Applications, Vol.32, Iss-3, May/June 1966, pp.533-541.

[19] Norbert Hohenbichler and Dirk Abel, "Robust PID controller design meeting polelocation and gain/phase margin requirements for time delay systems," in Proceed-ings of Automatisierungstechnik 54, Oldenbourg, 2006, pp. 495-501.

[20] Ned Mohan, Udeland and Robbins, "Power Electronics - Converters, Application,and Design", John Wiley & Sons, 2003.

[21] Benjamin C. Kuo, "Digital Control Systems", Oxford University Press, 2nd edition,1992.

[22] D. W. Gu, P. Hr. Petkov and M. M. Konstantinov, "Robust Control Design withMatlab", Springer-Verlag, 2005.

[23] John Doyle, Bruce Francis and Allen Tannenbaum, "Feedback Control Theory",Macmillan Publishing Co., 1990.

[24] Kemin Zhou and John C. Doyle, "Essentials of Robust Control", Prentice Hall,1998.

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[25] AD7864 High Speed, Low Power, 4-channel Simultaneous Sampling, 12-Bit ADC

[26] www.altera.com/support/software/quartus

[27] www.epcos.com/web/generator/Web/Sections/ProductSearch

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