designing an alu
DESCRIPTION
Designing an ALU. Taken from various sources Primary source: Digital Design and Computer Architecture by Harris &Harris. ALU. An arithmetic logic unit ( ALU ) Performs arithmetic and logic operations A fundamental building block of the Central Processing Unit (CPU) of a computer - PowerPoint PPT PresentationTRANSCRIPT
![Page 1: Designing an ALU](https://reader033.vdocument.in/reader033/viewer/2022051419/56815a65550346895dc7b00c/html5/thumbnails/1.jpg)
Designing an ALU
Taken from various sourcesPrimary source: Digital Design and
Computer Architecture by Harris &Harris
![Page 2: Designing an ALU](https://reader033.vdocument.in/reader033/viewer/2022051419/56815a65550346895dc7b00c/html5/thumbnails/2.jpg)
ALU
• An arithmetic logic unit (ALU) – Performs arithmetic and logic
operations– A fundamental building block of
the Central Processing Unit (CPU) of a computer
– Even the simplest microprocessors contain one for purposes such as maintaining timers
– A combinational logic circuit
![Page 3: Designing an ALU](https://reader033.vdocument.in/reader033/viewer/2022051419/56815a65550346895dc7b00c/html5/thumbnails/3.jpg)
Complex ALU
![Page 4: Designing an ALU](https://reader033.vdocument.in/reader033/viewer/2022051419/56815a65550346895dc7b00c/html5/thumbnails/4.jpg)
Simple ALU
The S input is controlled by the processor based on the op code
![Page 5: Designing an ALU](https://reader033.vdocument.in/reader033/viewer/2022051419/56815a65550346895dc7b00c/html5/thumbnails/5.jpg)
5
full adder from a previous lecture
Adder
![Page 6: Designing an ALU](https://reader033.vdocument.in/reader033/viewer/2022051419/56815a65550346895dc7b00c/html5/thumbnails/6.jpg)
Adder/Subtractor
![Page 7: Designing an ALU](https://reader033.vdocument.in/reader033/viewer/2022051419/56815a65550346895dc7b00c/html5/thumbnails/7.jpg)
Textbook ALU
![Page 8: Designing an ALU](https://reader033.vdocument.in/reader033/viewer/2022051419/56815a65550346895dc7b00c/html5/thumbnails/8.jpg)
Our Target ALU, N=32
The F input is controlled by the processor based on the op code
![Page 9: Designing an ALU](https://reader033.vdocument.in/reader033/viewer/2022051419/56815a65550346895dc7b00c/html5/thumbnails/9.jpg)
Possible Implementationmodule alu (input [31:0] A, B, input [2:0] F, output reg [31:0] Y);
// implement everything using a case statement??? always @ (*) case (..) … endcase
endmodule
![Page 10: Designing an ALU](https://reader033.vdocument.in/reader033/viewer/2022051419/56815a65550346895dc7b00c/html5/thumbnails/10.jpg)
An Implementation
From Harris Text: a simple ALUA cover a cover a cover a cover a cover a cover a cover a cover
![Page 11: Designing an ALU](https://reader033.vdocument.in/reader033/viewer/2022051419/56815a65550346895dc7b00c/html5/thumbnails/11.jpg)
Test Cases
![Page 12: Designing an ALU](https://reader033.vdocument.in/reader033/viewer/2022051419/56815a65550346895dc7b00c/html5/thumbnails/12.jpg)
Test the Implementation
A simple testbenchA cover a cover a cover a cover a cover a cover a cover a cover
![Page 13: Designing an ALU](https://reader033.vdocument.in/reader033/viewer/2022051419/56815a65550346895dc7b00c/html5/thumbnails/13.jpg)
ALU Enhancements
1. Add a Zero output to the ALU. The output is TRUE when Y==0, otherwise it is FALSE.
1. Add and Overflow output to the ALU. The output is TRUE when the result of the adder overflows, otherwise it is FALSE.
![Page 14: Designing an ALU](https://reader033.vdocument.in/reader033/viewer/2022051419/56815a65550346895dc7b00c/html5/thumbnails/14.jpg)
An Implementation
From Harris Text: an enhanced ALUA cover a cover a cover a cover a cover a cover a cover a cover
![Page 15: Designing an ALU](https://reader033.vdocument.in/reader033/viewer/2022051419/56815a65550346895dc7b00c/html5/thumbnails/15.jpg)
A Better Testbench
• Improved Testbench• Data file