designing cmos wireless system-on-a-chipieee 802.11a 4-6db power backoff 10-12 db power backoff 13...
TRANSCRIPT
1
(c) D. Su Santa Clara SSCS September 2009 p.1
Designing CMOS Wireless
System-on-a-chip
David Su
Atheros Communications
Santa Clara, California
Santa Clara SSCS
(c) D. Su Santa Clara SSCS September 2009 p.2
Outline
• Introduction
• CMOS Transceiver Building Blocks
– LNA and PA
• System-on-a-chip Integration issues
– Digital Assistance and Interference
• Conclusion
2
(c) D. Su Santa Clara SSCS September 2009 p.3
SoC Trends: GSM (1995)
Stetzler et al, ISSCC 95 (AT&T)
Integrated Transceiver with
external components (e.g. filters)
(c) D. Su Santa Clara SSCS September 2009 p.4
SoC with integrated
transceiver and CPU.
SoC Trends: GSM (2006)
Bonnaud et al, ISSCC 06 (Infineon)
3
(c) D. Su Santa Clara SSCS September 2009 p.5
SoC Trends: WLAN (1996)
Prism WLAN chipset (Harris Semi) AMD App Note (www.amd.com)
Multi-Chip 802.11b Transceiver
(c) D. Su Santa Clara SSCS September 2009 p.6
SwitchDigital
Signal
Processor
Synthesizer
LOI
LOQ
LOI
LOQ
LO
LNA
RFVGAPA
ADC
ADC
DAC
DAC
Su et al ISSCC 2002 (Atheros)Mehta et al ISSCC 2005 (Atheros)Chang et al ISSCC 2007 (Atheros)
WLAN Integration Story
4
(c) D. Su Santa Clara SSCS September 2009 p.7
11a/b/g/n (2x2 MIMO) Radio SoC
SoC Trends: WLAN (2008)
Nathawad et al, ISSCC 08 (Atheros)
(c) D. Su Santa Clara SSCS September 2009 p.8
Advantages of SoC Integration
• Increased functionality
• Smaller Size / Form Factor
• Lower Power
– On-chip interface
• Lower Cost
– Single package
– Ease of manufacture• Minimum RF board tuning
• Reduced component count ���� Improved reliability
5
(c) D. Su Santa Clara SSCS September 2009 p.9
Cost of WLAN Throughput
Zargari, 2007 VLSI Symposium Short Course
(c) D. Su Santa Clara SSCS September 2009 p.10
1
10
100
1000
1996 1998 2000 2002 2004 2006 2008
Year of Product Introduction
Max PHY Data Rate (Mb/s)
802.11 (2.4GHz)
802.11b (2.4GHz)
802.11a (5GHz)
802.11g (2.4GHz)
802.11n (2.4 and 5GHz)
Evolution of 802.11 WLAN PHY Rates
6
(c) D. Su Santa Clara SSCS September 2009 p.11
Single-chip Radio Block Diagram
Transceiver Digital
Baseband
PHY
Digital
MAC
Digital
Interface
(c) D. Su Santa Clara SSCS September 2009 p.12
Transceiver Block Diagram
SwitchDigital
Signal
Processor
Synthesizer
Receiver LOI
LOQ
LOI
LOQ
LO
LNA
RFVGAPA
Transmitter
ADC
ADC
DAC
DAC
7
(c) D. Su Santa Clara SSCS September 2009 p.13
CMOS Transceiver Building Blocks
• Signal Amplification
• Frequency Translation
• Frequency Selectivity
(c) D. Su Santa Clara SSCS September 2009 p.14
CMOS RF Design
Advantages• Low-cost, high-yield
• Multi-layer interconnect makes decent
inductors
• High-level of integration supports
sophisticated digital signal processing
Challenges:• Multi-GHz: narrowband design with inductors
• No high-Q BPF: architecture + dynamic range
• Process/Temp Variation: DSP algorithms
• Reduced supply headroom: IO devices
• Noise coupling: careful design & layout
8
(c) D. Su Santa Clara SSCS September 2009 p.15
Tuned CMOS RF Gain stage
VIN
Use of Inductor
���� Narrowband tuned circuit with higher gain
gmVIN RL C L
Equivalent Model
Gain
Frequency
(c) D. Su Santa Clara SSCS September 2009 p.16
LNA Design Goal
• Low Noise Figure– Sufficient gain
• Able to accommodate large blockers– Large Dynamic Range
– Large Common-mode Rejection
– High Linearity
9
(c) D. Su Santa Clara SSCS September 2009 p.17
LNA with Cascoded Diff Pair
• Input match
• Noise Figure
BIAS
IN IN
(c) D. Su Santa Clara SSCS September 2009 p.18
Zargari et al, JSSC Dec 2004 (Atheros)
LNA with Switchable Gain
• CMRR at RF
• Switchable gain for high DR
BIAS
IN IN
gain
M1 M4
gain
gain
M2 M3
10
(c) D. Su Santa Clara SSCS September 2009 p.19
Linear PA for High Data Rate
Modern digital modulation attempts to transmit at
highest data rate within a given signal bandwidth.
� Nonlinear PA:
Information in phase only. Transmit with constant
envelope for power efficiency – GSMK, FSK
� Modestly Linear PA:
Information in phase only. Reduce signal bandwidth
with non-constant envelope signal – ππππ/4 QPSK,
OQPSK
� Linear PA:
May encode information in both amplitude and
phase. Non-constant envelope; high SNR – 64 QAM
(c) D. Su Santa Clara SSCS September 2009 p.20
PA Peak to Average Ratio
• Improved spectral efficiency (higher bits per Hz)
���� Large peak to average ratio
���� reduces power efficiency of the PA
• Example: 802.11a/g OFDM has PAR of 17dB– Class A efficiency of ~ 1%
– Infrequent signal peaks
• 16-QAM OFDM, PAR of 6dB degrades SNR by
only 0.25dB*
���� Class A Efficiency ~ 12%
• 64-QAM OFDM, PAR of 12dB is needed
���� Class A Efficiency ~ 3%
* Van Nee & Prasad, OFDM for Wireless Multimedia Communications, Artech House, 2000
11
(c) D. Su Santa Clara SSCS September 2009 p.21
Linear Design
• Design for PSAT = PAVE + PAR + …
- Low R output match
• Stability
- Cascoding
• Linearity
- Avoid VGS overdrive
- Inter-stage capacitive level-shift
(c) D. Su Santa Clara SSCS September 2009 p.22
Cascoded Power Amplifier
� Cascoding advantages
�3.3V supply voltage
�Stability
� Capacitive Level-shift
� Differential
�Off-chip balun
RFIN
RFOUT
Bias
M2
Single-ended
equivalent
M1
L1 L2
VDD
12
(c) D. Su Santa Clara SSCS September 2009 p.23
Zargari et al, JSSC Dec 2002 (Atheros)
RFINRFIN
Bias1Bias1
RFOUT
Bias2
RFOUT
Bias2
PMAX = 22 dBm POFDM = 17.8 dBm (BPSK)
Cascoded Power Amplifier
(c) D. Su Santa Clara SSCS September 2009 p.24
Measured Power vs Data Rate
6 9 12 18 24 36 48 54
12
14
16
18
OFDM Output Power (dBm)
Data Rate (Mbps)
10
Spectral mask limited EVM limited
IEEE 802.11a
4-6dB Power Backoff
10-12 dB Power Backoff
13
(c) D. Su Santa Clara SSCS September 2009 p.25
Leveraging Integration for RF PA
Transistors are cheap.
– LARGE Output Power: Nonlinear PA
– HIGH Efficiency: Nonlinear PA
– GOOD Linearity: Use linearization circuits so that the output stage does not need to be linear.
SOLUTION: Switched-mode (non-linear) output stage
+ linearization.
(c) D. Su Santa Clara SSCS September 2009 p.26
PA Linearization
� Concept:
�Use efficient nonlinear PAs for amplification
�Techniques to improve linearity
� An active research area for over half a century!
Some examples:
�Feedforward
�Predistortion
�Cartesian feedback: Rectangular I-Q
�Outphasing / Chirex / LINC: Phase-Phase
�Polar: Phase-magnitude, EER
… (many many more)
14
(c) D. Su Santa Clara SSCS September 2009 p.27
LF
RF
RF Power Amplifier
RF Output
Magnitude
Phase
Polar
� Input = PHASE and MAGNITUDE
� Amplified separately and then combined
� Ref: L. Kahn, Proc. IRE, July 1952.
(c) D. Su Santa Clara SSCS September 2009 p.28
RF
Parallel RF Power Amplifier
RF Output
Digital Magnitude
Phase
Digital Polar
n
15
(c) D. Su Santa Clara SSCS September 2009 p.29
I/Q to
Polar
I
Q
Decoder
Phase
Magnitude
6
OUT
PA1
PA2
PA64
Kavousian et al, ISSC 2007 (Stanford)
Digitally Modulated Polar Power Amplifier
(c) D. Su Santa Clara SSCS September 2009 p.30
Kavousian et al, ISSC 2007 (Stanford)
RFOUT
M1
L2
Phase
Ctrl1
Matching
Network
• Bandwidth: 20MHz
• Frequency: 1.6GHz
• EVM: -26.8dB
• Power: 13.6dBm
M2
Ctrl2
M64
Ctrl64
Digitally Modulated Polar Power Amplifier
16
(c) D. Su Santa Clara SSCS September 2009 p.31
RF PA with Envelope Feedback
Terrovitis et al, ESSCIRC Sept 2009 (Atheros)
IN OUT
PA
• Linearizes Gain
• Fixes gain variation over process and temperature
1/αααα
Gain
Control
(c) D. Su Santa Clara SSCS September 2009 p.32
Integrating RF Tx/Rx Switch in CMOS
• MOS pass transistors
as switches has too
much loss and may
not be able to support
required voltage
breakdown
Tx/Rx Switch
LNA
PA
Tx
Rx
17
(c) D. Su Santa Clara SSCS September 2009 p.33
M1 b1
M2
LNAOUT
b2
PAOUT
PAINM4
M3 b3
Tx/Rx Switch
LNAIN
Integrated RF Tx/Rx Switch
Receive chain noise figure = 5.8dB
Chang et al, ISSCC 2007 (Atheros)
ππππ matching network
Rx Mode
PA off
(c) D. Su Santa Clara SSCS September 2009 p.34
PAINM4
M3
PAOUT
b3
Tx/Rx Switch
Chang et al, ISSCC 2007 (Atheros)
Tx ModeM1
M2
b1
b2
LNAOUT
LNAIN
Transmit output power = 20dBm (< 1dB loss)
Integrated RF Tx/Rx Switch
18
(c) D. Su Santa Clara SSCS September 2009 p.35
System-on-a-Chip Integration
� Digital Assistance: Calibration Techniques
• Digital Interference: Noise Coupling
Analog/RF
DIGITAL
(c) D. Su Santa Clara SSCS September 2009 p.36
Analog Design
Digital Assisted Analog Design
Digital Designer
19
(c) D. Su Santa Clara SSCS September 2009 p.37
Digital Assistance: Calibration Issues
• Digital logic to compensate/correct for imperfections
of analog and RF circuits can enable:
– Lower power, smaller area, improved reliability of
analog/RF
• Desired properties of calibration:
– Independent of temperature, aging, frequency
– Inexpensive (in area and power) to implement
– Do not interfere with system performance
• Wireless SoC advantage:
– Calibration building blocks already exist on-chip:
transmitter and receiver, data converters, and CPU
– No package pin limitation
(c) D. Su Santa Clara SSCS September 2009 p.38
Calibration Techniques
� Test Signal
– Dedicated test signals from DAC: Tx carrier leak
– RF loop back: Receive filter bandwidth
– Thermal noise: Rx Gain
– Live Rx (signal) traffic: Rx I/Q mismatch
� Observation Signal
– Dedicated ADC
– Implicit ADC: Comparator
� Tuning Mechanism
– Dedicated DAC
– Implicit DAC: Selectable capacitors, resistors, transistors
20
(c) D. Su Santa Clara SSCS September 2009 p.39
RF loop back: Tx Carrier Leak
• Test signal: Tx DAC
• Observation signal: RF loop back to Rx ADC
• Tuning: Carrier Leak Correction at Tx DAC input
LO
PA
DAC
Digital
Baseband
TX
LNA
ADC
LO
RX+
+
Carrier Leak
Correction
(c) D. Su Santa Clara SSCS September 2009 p.40
Calibrating Low-pass gm-C Filter
Zargari et al, JSSC Dec 2004
Low-Q
Biquad
High-Q
BiquadTransresistance
Amplifier
Capacitor setting
IN OUT
Iin
gm1
-gm2
gm3gm4
Iout
Replica
Biquad
Phase
Detector
State
MachineRef Clock
21
(c) D. Su Santa Clara SSCS September 2009 p.41
System-on-a-Chip Integration
• Digital Assistance: Calibration Techniques
� Digital Interference: Noise Coupling
Analog/RF
DIGITAL
(c) D. Su Santa Clara SSCS September 2009 p.42
Digital Interference
Analog
Digital
22
(c) D. Su Santa Clara SSCS September 2009 p.43
Digital Interference: Noise Coupling
Aggressor
Victim
Accomplice
(c) D. Su Santa Clara SSCS September 2009 p.44
Noise Source
Pacify the aggressor
• Reduce noise by turning off unused digital– Clock gating
– Avoid oversized digital buffers
• Stagger digital switching– Avoid large number of digital pads switching simultaneously
– Avoid switching digital logic at the same sampling instance of sensitive analog
23
(c) D. Su Santa Clara SSCS September 2009 p.45
Noise Destination
Strengthen the victim
• Increase immunity of sensitive analog and RF circuits– Common-mode noise rejection:���� Fully differential topology
– Power Supply noise rejection:���� Good PSRR���� Dedicated on-chip voltage regulators
• Avoid package coupling by keeping sensitive nodes on chip (Example: VCO control voltage)
(c) D. Su Santa Clara SSCS September 2009 p.46
Coupling Mechanism
Deter the accomplice
• Supply noise coupling– Separate or star-connected power supplies
• Capacitive or inductive coupling to sensitive signals and bias voltages– Careful routing of signal traces to reduce parasitic capacitive/inductive coupling
– Use ground return-path shields
24
(c) D. Su Santa Clara SSCS September 2009 p.47
Coupling Mechanism (Cont’d)
• Epi vs non-epi substrate
• Substrate coupling induced VTH modulation– Low-impedance substrate connection
– Guard rings
– Physical separation
– Deep Nwell
(c) D. Su Santa Clara SSCS September 2009 p.48
Frequency Synthesizer
Terrovitis et al, ISSCC 2004 (Atheros)
DFFRef
Div
P & S
CounterDFF
8/8.5
Div
16/17 Divider
PFD CP
On-chip
Loop Filter
fvco/4I Q
LO Buffers
Xtal Osc
40MHz
/ 2
Reg1 Reg2
Retiming FFs
VCO
25
(c) D. Su Santa Clara SSCS September 2009 p.49
Conclusions
• CMOS has become the technology of choice for integrated radio systems
• Integrating a radio in mixed-Signal System-on-a-Chip is no longer a dream but a reality
• Wireless SoC can provide significant advantages in size, power, and cost
(c) D. Su Santa Clara SSCS September 2009 p.50
Continuing Challenges
• Multi-mode radios to support several wireless standards
• RF design in scaled CMOS– Reduced supply voltage: voltage, current, time
– nanometer transistors: leaky, low gm.ro
– How to reduce analog/RF area and power: less analog and more digital
• Challenge of radio designers will still be:– Power consumption / Battery life
– Range
– Data rate
– Cost
26
(c) D. Su Santa Clara SSCS September 2009 p.51
Acknowledgments
• Many of the slides are based on previous presentations from Atheros Communications and Stanford University, especially those by:
Manolis Terrovitis, Srenik Mehta, William Si, William McFarland, Lalitkumar Nathawad Richard ChangAmirpouya Kavousian