designofanalogsignalprocessingapplicationsusingcarbon...

Research ArticleDesign of Analog Signal Processing Applications Using CarbonNanotube Field Effect Transistor-Based Low-Power FoldedCascode Operational Amplifier

Varsha S. Bendre ,1 A. K. Kureshi,2 and Saurabh Waykole3

1Department of Electronics & Telecommunication, JSPM’s Rajarshi Shahu College of Engineering,Savitribai Phule Pune University, Pune 411044, India2Department of Electronics & Telecommunication, Vishwabharati Academy’s College of Engineering, Ahmadnagar, India3Department of Electronics & Telecommunication, Pimpri Chinchwad College of Engineering, Savitribai Phule Pune University,Pune 411044, India

Correspondence should be addressed to Varsha S. Bendre; [email protected]

Received 11 May 2018; Revised 30 September 2018; Accepted 18 October 2018; Published 4 December 2018

Academic Editor: Marco Rossi

Copyright © 2018 Varsha S. Bendre et al. 'is is an open access article distributed under the Creative Commons AttributionLicense, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work isproperly cited.

Carbon nanotube (CNT) is one of the embryonic technologies within recent inventions towards miniaturization of semi-conductor devices and is gaining much attention due to very high throughput and very extensive series of applications in variousanalog/mixed signal applications of today’s high-speed era. 'e carbon nanotube field effect transistors (CNFETs) have beenreconnoitred as the stimulating aspirant for the future generations of integrated circuit (IC) devices. CNFETs are being widelydeliberated as probable replacement to siliconMOSFETs also. In this paper, different analog signal processing applications such asinverting amplifier, noninverting amplifier, summer, subtractor, differentiator, integrator, half-wave and full-wave rectifiers,clipper, clamper, inverting and noninverting comparators, peak detector, and zero crossing detector are implemented using low-power folded cascode operational amplifier (op-amp) implemented using CNFET. 'e proposed CNFET-based analog signalprocessing applications are instigated at 32 nm technology node. Simulation results show that the proposed applications areproperly implemented using novel folded cascode operational amplifier (FCOA) implemented using CNFET.

1. Introduction

Over the last few decades, the electronics industries haveseen remarkable growth in integrated circuits applications.'ere is substantial increase in integration density, speed,and performance, which results in high-speed portabledevices and such demands are still raising in day-to-day life.Power dissipation and heating constraints are also in-creasing with every new technology, as emerging silicontechnologies continues to scale unfathomable into the ultra-nanometer regime. 'rough the last few decades, significantefforts are made to reduce the power budget ensuring highperformance. But, the aggressive scaling of MOS transistorsnow approached to the fact that the channel and gate oxidebecomes very thin and diffusion regions of transistors are in

such vicinity that the charge carriers can easily cross thechannel in vertical direction leading to unwanted currentsthrough it and hence further horizontal scaling is notpossible. As anticipated by the International TechnologyRoadmap for Semiconductors [1], rigorous exploration isdesirable in order to endure this process and, undeniably, toencourage novel devices and methods that will move thetechnology developments in other directions [2, 3]. Carbonnanotube field-effect transistor (CNFET) is the competitortransistor which will permit for both the scaling process tosustain and for the progress of novel devices [4]. 'e detailsof CNFET and its properties are explained in Section 2.

Operational amplifiers (op-amps) are indispensableblocks in almost all analog/mixed signal applications [5].Design and development of maximum throughput analog

HindawiJournal of NanotechnologyVolume 2018, Article ID 2301421, 15 pageshttps://doi.org/10.1155/2018/2301421

mailto:[email protected]://orcid.org/0000-0003-0290-652Xhttps://creativecommons.org/licenses/by/4.0/https://creativecommons.org/licenses/by/4.0/https://doi.org/10.1155/2018/2301421

integrated circuits is fetching progressive constraining dueto the persistent tendency towards scaling in very deepsubmicron regime. 'ere is a significant degradation in theperformance of op-amp in nanometer regime and there isa stringent requirement to reconnoitre new circuit designstrategies for new upcoming devices like CNFET for theirspeedy merchandise to prolong Moore’s law in deepnanometer regime [6]. Explanation of finest design ofCMOS-based folded cascode op-amp is extensively dis-cussed by us in [7] and will not be covered here. Brief aboutCNFET and its performance comparison with CMOS isexplained in section 2. Design of CNFET-based FCOA andthe effect of pitch and diameter on the performance pa-rameters are explained in Section 3. Section 4 explainsdifferent analog signal processing applications implementedusing CNFET-FCOA at 32 nm technology node. Concludingremarks towards the achievement of various performancemetrics using CNFET are stated in Section 5.

2. Carbon Nanotube Field Effect Transistor

CNFETs are the transistors in which number of carbonnanotubes (CNTs) acts as a physical channel between sourceand drain unlike virtual channel in case of metal oxidesemiconductor field effect transistor (MOSFET) [8]. CNTsare thin sheets of graphene. Graphene is an allotrope ofcarbon made up of tightly packed thin layer of pure carbonatoms.'is thin single-layered sheet is then rolled into tubesalong different directions to form either metallic or semi-conducting single-walled CNTs (SWCNTs).'is direction ofrotation is termed as the chirality and represented in theform of sum of two vectors (n,m), as shown in Equation (1),representing two different directions. Out of these two typesof SWCNTs, metallic nanotubes are widely used as in-terconnect and semiconducting nanotubes have captivatedprevalent attention as an alternative solution for high-performance transistors in nanometer regime [9, 10]. AnSWCNT is a conductor if n − m � 3k (k € Z); otherwise it isa semiconductor [11], where n, m are positive integers thatspecify the chirality of the tube [7–13]. 'e magnitude of thechirality depends on the diameter of the CNT and is de-termined by using Equation (2):

Ch � a��n2 + m2 + nm

√, (1)

D �a

��n2 + m2 + nm

√

π≈ 0.0783

��n2 + m2 + nm

√, (2)

where a is the carbon-to-carbon atomic distance, which is∼2.49 Å.

A distinctive construction of a CNFET device isdemonstrated in Figure 1. All regions in this device areheavily doped except the CNT channel region, which iscompletely undoped. Analogous to the MOSFET, a CNFETalso has a threshold voltage which needs to turn on thedevice. An inimitable feature of the CNFET device is theadjustability of its threshold voltage by changing the di-ameter of the CNTs. 'is is due to the fact that the CNTband gap, which is the function of the threshold voltage,

depends inversely on the diameter as shown in the fol-lowing equation [11, 14, 15]:

Vth ≈Eg

2e� 0.557a

VπDCNT≈

0.43DCNT

, (3)

where “e” is the unit electron charge and Vπ (∼3.033 eV) isthe carbon p-p bond energy in the tight bonding model. 'ispertinent property makes the CNFET very useful for voltagemode analog and digital circuits [7, 11].

2.1. Performance Comparison of CMOS and CNFET withRespect to Electrical Characteristics. CNFETs are better thanbulk complementary metal oxide semiconductor (CMOS)transistors in case of contact resistance, subthreshold slope,and current drive capability. 'e contact resistance and thesubthreshold slope of a CNFET are analogous to those ofCMOS transistors.'eCNFETcurrent is measured in currentper tube and can be increased by increasing the number oftubes, while a CMOS current drive is characteristically rep-resented in current per unit device width (e.g., µA/µm) [12].'e ON current of CNFET can be approximately given byEquation (4) and it has little dependency on the channellength in case of near-ballistic transportation:

Icnt ≈Ngcnt VDD −Vth(

1 + gcntLsρs, (4)

where Ls is the length of the doped CNT source region, ρs isthe source resistance per unit length of doped CNT, and gcntis the transconductance per CNT and is given by the fol-lowing equation:

gcnt �μcntCgc u Vgs −Vth

L�μcntCgcu Vgs − 0.43/Dcnt

L,

(5)

where μcnt and Cgc_u are the carrier mobility in CNTand gateto channel capacitance per unit length, respectively.

I-V characteristics of a typical 32nm MOSFET-likeN-CNFET and P-CNFET are shown in Figure 2(a). Accord-ing to Figure 2(b), a 32nm CNFET has proper Id-Vds char-acteristics without short channel effects, whereas the 32 nmMOSFET suffers from higher channel resistance in the trioderegion, degraded r0, and velocity saturation. Furthermore, asillustrated in Figure 2(b), besides the considerable higherION/IOFF of the CNFET, it has a quadratic Id-Vgs curve in thesaturation region while the MOSFETdevice has a linear Id-Vgscurve, mostly due to velocity saturation. Hence, it can beconcluded that the MOSFET-like CNFET can be a promisingdevice for designing some nanoscale analog circuits such asprecise comparators and high-gain amplifiers [11].

Additionally, compared to bulk CMOS, the effective gatecapacitance of one CNTper gate of CNFETs is about 4% andthe current drive capability of each CNT is about 50% incontrast to bulk n-type MOSFET [12]. 'is is due to theballistic transport of carriers along the CNT in specific di-rection. 'is results into 13 times better CV/I performanceof CNFET over that of bulk n-type MOSFET. Enhancementin performance of p-CNFET is more than that in n-CNFETas compared to PMOS and NMOS, respectively. 'is is due

2 Journal of Nanotechnology

to the similar behaviour and the current driving capability ofa p-CNFET compared to those of an n-CNFET. 'e majorproblem associated with CNFET is the significant amount ofleakage current in the off state, but it can be rectified bycontrolling the band to band tunneling and the full band gapof the CNTs which is less than for a MOSFET [13–17].

Moreover, the motion of the electrons in the nanotubesis sternly confined along the direction of tube axis, due to thequasi-1D structure of CNT. Hence, only forward andbackward scatterings are possible for the carriers in nano-tubes, and all other scatterings are prohibited. 'e experi-mentally observed mean free path (MFP) is ∼1 µm [18, 19],which implies near-ballistic carrier transport. Typical rangeof mobility is very high, up to 103∼104 cm2/V·s observedduring conductance experiments in transistors and as hasbeen proved by a diversity of studies [20, 21]. Hypothetical

study too forecasts a mobility of ∼104 cm2/V·s for semi-conducting CNTs [22]. 'e current carrying capability ofmultiwalled CNTs are confirmed to be more than 109A/cm2,about 3 orders greater than the extreme current carryingcapacity of copper and also able to sustain the same per-formance well above the room temperature [19]. In nutshell,the superior carrier transport and conduction characteristicmakes CNFETs a promising candidate for nanoelectronicsapplications [13].

With these tremendous features of CNTs and CNFETs,circuit design using CNFET is on the top choices of circuitdesigners. However, more emphasis and hence extensiveresearch is done in digital circuit implementation, andanalog circuit design is still a challenge. As on today, veryfew, only one or two, topologies of op-amps are imple-mented using CNFET. In this paper, first attempt is made, to

Substrate

Drain

Gate

Source

Dielectric(Kgate) CNTs

Csub

(a)

Wgate

Drain

Source

Gate

Patch

Lch

CNTs

(b)

Figure 1: Structure of CNFET [23].

60μ

40μ

20μ

0

Curr

ent (

lin)

–20μ

–40μ

–60μ

–500m 0Voltage X (lin) (volts)

500m

NCNFET

PCNFET

(a)

95μNCNFET

NMOS

90μ85μ80μ75μ70μ65μ60μ55μ50μ45μ40μ35μ30μ25μ20μ15μ10μ

5μ0

–5μ

I d (l

in)

0 200m 400m 600m 800m 1Voltage X (lin) (volts)

(b)

Figure 2: I-V characteristics of 32 nm CNFET and CMOS. (a) Id-Vds of NCNFET and PCNFET for various values of Vgs. (b) Id-Vds ofNCNFET and NMOS.

Journal of Nanotechnology 3

the best of our knowledge, to design CNFET-based foldedcascode op-amp (CNFET-FCOA) and successfully calculatealmost all parameters associated with an op-amp. Furtherdifferent signal processing applications are implementedusing novel folded cascode op-amp (FCOA) designed usingCNFETat 32 nm CNFET technologies. Next section explainsabout the design of CNFET-FCOA.

3. Design of Folded Cascode op-Amp UsingCarbon Nanotube Field Effect Transistor

A CNFET works on the fundamental concept of applyinggate voltage to modulate the current between drain andsource and exhibits unipolar behaviour. In back-gatedstructures, due to different junction and overlap capaci-tances, high-frequency operation is limited but the top-gateedifice of CNFETpermits high-speed operation. Also, due toinbuilt channel of nanotubes and its structure, leakagecurrent is no longer the problem with CNFET and it showsenhanced current handling competency [24–26]. CNFETendeavours remarkable carrier transport and conductioncharacteristics predominantly due to the high mobility andhigh current density [25–27]. 'e width of the CNFETtransistor (W), the diameter of CNT (Dcnt), number of CNTsin the channel (N), the spacing between two adjacentnanotubes, and pitch (S) [13, 19, 22–26] are related by thefollowing equation:

W � (N− 1)S + Dcnt. (6)

In CNFET-based implementation, number of tubes,pitch, and diameter are the parameters that are designed toachieve optimum result unlike aspect ratios in case of CMOS[2, 3, 28–30]. Figure 3(a) shows the schematic of proposedCNFET-FCOA, and Figure 3(b) shows the symbolic rep-resentation of proposed CNFET-FCOA.

In this analysis, unlike conventional op-amp, it is pre-sumed that the current from Q1 directly flows through thedrain of Q6 and thus to the load capacitance and the currentfrom Q2 goes indirectly through Q5 and the current mirrorconsisting of Q7 to Q10. Also, it is assumed that maximumamount of current flows through Q1 and hence these twopaths have slightly different transfer functions. 'e high-frequency poles and zeros are nondominant and can beignored because they are located at high frequency com-pared to unity gain frequency [7].

An approximate small-signal transfer function for thefolded-cascode op-amp in CMOS technology is given by

Av �Vout(s)

Vin(s)� gm1 . ZL(s), (7)

where gm1 is the amplifier’s transconductance gain andZL(s) is the output impedance.

'e open loop gain of op-amp is further calculated as

Av �gm1 · rout

1 + s · rout · CL, (8)

where rout is the output impedance of the op-amp and CL isthe load capacitance.

For high frequencies, the load capacitance dominates,and hence

Av �gm1

s · CL. (9)

'e input transconductance can be increased by usinglong-channel transistors and ensuring that the inputtransistor pair’s bias current is significantly larger than thecascode transistor’s bias current. 'is will also result inimprovement of bandwidth. To maximize the dc gain of thedesigned op-amp, it is considered that the current flowingthrough all the transistors connected to output node isat small levels. 'is will not only maximize the inputtransconductance but also output impedance. Maximumamount of bias current through the input differential pairresults in large transconductance of the input devices andhence in the improvement of thermal noise performance ofOpAmp [7, 31].

In this work, MOSFET-like CNFETs are used for de-signing the FCOA circuit and due to the similarities betweenthe MOSFET and MOSFET-like CNFET devices in terms ofI-V characteristics and the other inherent attributes, designprocedure of CNFET-based circuits is similar to CMOS[13, 30–37]. Furthermore, as in CNFET device μn � μp andall of the characteristics of the used CNFETs such as gatelength (L � 32 nm), CNTdiameters (DCNT � 1.49 nm), andpitch (8 nm), except the width of the CNFETs, are set to beidentical, the only parameter here that could affect the gainof the FCOA is the width of CNFETs. In addition, because ofthe direct relation between the width of a CNFET and thenumber of its nanotubes [38], the desired widths can be setby adopting proper number of CNTs for each transistor [37].

For simulation purposes, CNFET, SPICE compatibleStanford University 32 nm CNFET model is used [30]. Inthis study, top-gated undoped semiconducting MOSs likeCNFETs with 4 nm thick HfO2, high-k dielectric (k � 16),chirality (19, 0), and fixed diameter at 1.49 nm are used. 'enumber of tubes is calculated using Equation (1) for pitchequals to 8 nm, keeping the diameter constant, and isitemized in Table 1. 'e designed folded cascode op-ampconfiguration is further simulated using HSPICE to achievesatisfactory DC performance and further used to calculatevarious performance metrics such as DC gain (Av0), phasemargin (PM), unity gain bandwidth (UGB), common moderejection ratio (CMRR), power supply rejection ratio(PSRR), slew rate (SR), output swing (OS), and powerconsumption [6].

3.1. Optimum Choice for Pitch and Diameter of CNFET.'e simulations are performed for three different values ofpitch 8 nm, 12 nm, and 20 nm for CNFET-based FCOA.Table 2 shows the comparative results at different values ofpitch with respect to specifications. 'e comparative ex-amination of the important parameters of CNFET-FCOAarchitectures affirms that a noteworthy improvement inperformance is achieved in the CNFET-based FCOAs andthe gain is highest amongst three for pitch equals to 8 nm.'e similar kind of performance is not possible at such


very deep submicron levels using CMOS due to extremeshort-channel effects, lithographic limitations, processvariations, leakage current, and source-to-drain tunneling[25, 37–41]. Further CNFET technology can also be easilyclubbed with the bulk CMOS technology on a single chipand utilizes the same infrastructure [23, 30, 42].

An investigative result demonstrates that the frequencyresponse of the designed OTA improves with the increase indiameter of the nanotube as shown in Figures 4(a) to 4(c).'is is due to the fact that the transconductance goes up withthe increase in diameter of the nanotubes. 'e DC gaindecreases with the diameter because the reduction in theoutput resistance with diameter is more than the rise in itstransconductance. 'is trend is observed because CNFETcircuit performance and electrical behaviour directly dependon the CNT diameter. Diameter is the main parameter thataffects the on current proportionally in a CNFETapart frombarrier height at the S/D contact (or RS/D), chirality, andoxide thickness, but for larger diameters, current tends tosaturate due to large screening and scattering effects[14, 24, 25, 33]. Also, the power consumption of an amplifier

goes up due to the smaller band gap and higher currentdrive.

4. CNFET-FCOA-Based Analog SignalProcessing Applications

Operational amplifier was formerly aimed to execute dif-ferent operations on signals such as addition, subtraction,differentiation, integration, and comparison. In the pro-posed work, the functionality of the CNTFET-FCOA istested for all such signal processing applications to check thepractical usefulness of the proposed CNFET-FCOA at verydeep submicron node. All the signal processing circuits aredesigned and implemented at 32 nm, a nanometer regimewhere there are certain constraints with CMOS technologydue to sternness of nonideal effects.

4.1. CNFET-FCOA-Based Noninverting Amplifier. 'e op-amp circuitry, comprising voltage divider at inverting node,is called a noninverting amplifier because its voltage gain ispositive [30]. 'is means that the output voltage will followthe input voltage. 'e period of input and output voltage issame as the phase, only amplitude of output waveformsdepends on gain of the op-amp. CNFET-FCOA-basednoninverting amplifier is shown in Figure 5(a). 'e inputvoltage Vin is applied to the noninverting terminal of op-amp. Partial output, i.e., feedback, is given to the invertinginput through the feedback resistor RF, which forms voltagedivider network with Rin1. For the designed noninvertingamplifier, voltage gain is 14. 'e expression for outputvoltage is given by using Equation (10) and its waveform isshown in Figure 6(a):

Vout � Vin 1 +RF

Rin1 . (10)

VoutVin+

CL

Vb1

Vb2

VDD

Bias 1

Bias 2

Vin–

Q1 Q2

Q3 Q4Q11

Q5 Q6

Q7 Q8

Q9 Q10

(a)

VoutVin1

Vin2

(b)

Figure 3: Proposed folded cascode operational amplifier using CNFET. (a) Schematic and (b) symbol.

Table 1: Number of tubes for pitch � 8 nm.

Transistors Number of tubesM1 600M2 600M3 200M4 200M5 100M6 100M7 20M8 20M9 100M10 100M11 200


4.2. CNFET-FCOA-Based Inverting Amplifier. As the namesuggests, input and output waveforms are out of phase or arehaving 180° phase shift, i.e., whenever input voltage in-creases, output voltage decreases and vice-a-versa. 'ecircuit diagram of a CNFET-FCOA-based inverting am-plifier is shown in Figure 5(b). 'e input signal, Vin, isapplied through resistor Rin1 to the inverting terminal of theop-amp. Feedback resistor RF connects the partial output tothe noninverting input. Second input of the op-amp is con-nected to fixed potential, say ground. For the designed invertingamplifier, voltage gain is 14 and the expression for outputvoltage of the inverting amplifier is as shown by Equation (11)and the resulting waveform is shown in Figure 6(b):

Vout � −VinRF

Rin1 . (11)

4.3. CNFET-FCOA-Based Summer. As the name suggests,summer means the circuit which adds two signals [30].Figure 5(c) shows the basic inverting summer which is usedto sum two or more signal voltages and at the outputproduces amplified sum of the two input signal. For thedesigned non inverting summer, the expression for outputvoltage is given by Equation (12), and the waveform is asdisplayed in Figure 6(c):

Table 2: Comparative results at different values of pitch.

Performance parameter Design specificationSimulation results

Pitch 8 nm Pitch 12 nm Pitch 20 nmOpen loop gain (dB) 60 75.2 66.2 60.4Phase margin (°) 45° 86.6° 86.9° 87.2Unity gain bandwidth (MHz) 255 530 523 510Power dissipation (mW)

RF = 500KRin1 = 10K

VinVout

(a)

RF = 500K

+

–

Rin1 = 10KVin

Vout

(b)

Vin1

Vin2 RF = 5K

Rin1 = 5K Vout

Rin2 = 5K

(c)

Vin1

Vin2

RF = 5K

Rin1 = 5K

Vout

Rin2 = 5K

Rcomp = 5K

(d)

Vin1

RF = 5K

Cin = 10µF

VoutRin1 = 10K

CF = 20µF

(e)

Vin1VoutRin1 = 4K

CF = 15nF

(f )

D1

RF = 100K

Rin1 = 100K

Vin

Vout+

–+–

(g)

Rin1 = 100K D2

Vin

Vout

Rin2 = 100K Rin3 = 100K Rin4 = 100K

D1

Rin5 = 100K

++ – –

– +

(h)

10K

P1Vref = 0.9V

Vin1Vout

D1

++ –

–

(i)

10K

P1Vref = 0.9V

Vin1Vout

D1Cin = 10µF

++ –

–

(j)

+Vref

Rin1 = 10K

Rin2 = 10K

Vin1Vout+

–

+

–

(k)

+Vref

Rin1 = 10K

Rin2 = 10K

Vin1Vout+

+–

–

(l)

Figure 5: Continued.


Vout

RF = 10K

Vin

R1=

1M

D1+

–

+–

+

–

C1=

100p

F

(m)

Vout

Vin

C1 = 1µF

R2 = 10KR1 = 10K

+–

+

–

(n)

Figure 5: Analog signal processing applications. (a) Noninverting amplifier. (b) Inverting amplifier. (c) Summer. (d) Subtractor.(e) Differentiator. (f ) Integrator. (g) Half-wave rectifier. (h) Full-wave rectifier. (i) Clipper. (j) Clamper. (k) Noninverting comparator.(l) Inverting comparator. (m) Peak detector. (n) Zero crossing detector.

Volta

ge (l

in)

Volta

ge (l

in)

90m

100m

110m

–1m

1m

0

0Time (lin) (time)

500n 1μ 1.5μ

Vin

Vout

2μ

(a)

Vin

Vout

Volta

ge (l

in)

Volta

ge (l

in)

90m

100m

110m

–1m

1m

0

0Time (lin) (time)

500n 1μ 1.5μ 2μ

(b)

Vin1

Vin2

Vout

Volta

ge (l

in)

–1m

1m

0

Volta

ge (l

in)

–1m

1m

0

Volta

ge (l

in)

930m925m920m

0Time (lin) (time)

500n 1μ 1.5μ 2μ

(c)



Vin1

Vin2

Vout

Volta

ge (l

in)

500m0

–500m–1

1

Volta

ge (l

in)

0

–500m

500mVo

ltage

(lin

)

200m0

400m

0Time (lin) (time)

500n 1μ 1.5μ 2μ

(d)

Vin

Vout

Volta

ge (l

in)

0

1

500m

Volta

ge (l

in)

–1

1

0

0Time (lin) (time)

500n 1μ 1.5μ 2μ

(e)

Vin

Vout

0Time (lin) (time)

500n 1μ 1.5μ 2μ

Volta

ge (l

in)

0

1

500m

Volta

ge (l

in)

–1

1

0

(f )



Vin

Vout

0Time (lin) (time)

500n 1μ 1.5μ 2μ

Volta

ge (l

in)

–100m

100m

0

Volta

ge (l

in)

0

200m

100m

(g)

Vin

VoutPostive cycle

VoutNegative cycle

Volta

ge (l

in)

–1

350m300m250m200m150m100m

50m0

1

0

Volta

ge (l

in)

0Time (lin) (time)

500n 1μ 1.5μ 2μ

350m300m250m200m150m100m

50m0V

olta

ge (l

in)

(h)

0Time (lin) (time)

500n 1μ 1.5μ 2μ

Volta

ge (l

in)

–2

2

0

Volta

ge (l

in)

21.5

1500m

–500m0

(i)



Vin

Vout

0Time (lin) (time)

500n 1μ 1.5μ 2μ

Volta

ge (l

in)

–1m

1m

0

Volta

ge (l

in)

14m

13m

(j)

Vin Vref

Vout

0Time (lin) (time)

500n 1μ 1.5μ 2μ

Volta

ge (l

in)

–2

800m600m400m

2

0

Volta

ge (l

in) 1

0Time (lin) (time)

500n 1μ 1.5μ 2μ

(k)

VrefVin

Vout300m250m200m150m100m

50m0

–2

2

0

0Time (lin) (time)

500n 1μ 1.5μ 2μ

Volta

ge (l

in)

Volta

ge (l

in)

0Time (lin) (time)

500n 1μ 1.5μ 2μ

(l)

Vin

Vout

0Time (lin) (time)

500n 1μ 1.5μ 2μ

–1

1

0

Volta

ge (l

in)

–1

1

0

Volta

ge (l

in)

(m)



Vout � RFV1Rin1

+V2Rin2

. (12)

4.4.CNFET-FCOA-Based Subtractor. A differential amplifierwith unity gain can be used to provide an output voltage thatis equal to the difference of two input voltages [30]. Sucha circuit is called a subtractor and is shown in Figure 5(d).'enet output result, as shown in Figure 6(d), is the differencebetween two input voltages Vin1 and Vin2 applied at theinverting and noninverting terminals of the op-amp, re-spectively [40]. For the designed subtractor, voltage gain is 1,since all the resistors are of same value, and the output voltageof the subtractor is evaluated using the following equation:

Vout � Vin1 −Vin2. (13)

4.5. CNFET-FCOA-Based Differentiator. In differentiator,the output voltage is proportional to the rate of change of itsinput voltage. Figure 5(e) gives the circuit diagram ofa CNFET-FCOA-based differentiator. 'e circuit consists ofinput resistor Rin in series with capacitor Cin and pair of RFand CF in parallel in the feedback path. For the designeddifferentiator, output voltage is expressed by Equation (14).Figure 6(e) shows the corresponding output of differentiator:

Vout � −RF · CindVin

dt . (14)

4.6. CNFET-FCOA-Based Integrator. In case of integrator,output voltage is proportional to the integration of its inputvoltage [30]. 'e circuit for the integrator can be as same asthat of the differentiator, except that the position of theresistor and that of the capacitor is interchanged as shown inFigure 5(f ). For the designed integrator, output voltage isexpressed as shown in Equation (15). 'e correspondinginput-output waveforms are shown in Figure 6(f):

Vout � −1

RfC1

t

∞Vin dt. (15)

4.7. CNFET-FCOA-Based Half-Wave Rectifier. Half-waverectifier (HWR) is a circuit which allows only the positivecycle of input sinusoidal waveform with the help of forward-biased diode to reach at the output. Such a circuit of half-waverectifier is shown in Figure 5(g).'e op-amp output turns outto be positive only during the positive half cycle of the inputwaveform, which eventually makes the diode D1 forwardbiased and the positive half cycle waveform appears across theoutput terminal [30]. In contrast, during the negative halfcycle, the op-amp output becomes negative, turning OFFdiode D1. 'is will not allow the negative portion of input toappear across the output. 'e overall outcome is impeccablehalf-wave rectification, as epitomized in Figure 6(g).

4.8. CNFET-FCOA Full-Wave Rectifier. In contrast to half-wave rectifier, full-wave rectifier allows positive as well asnegative half cycles of input waveforms to reach at the

Volta

ge (l

in)

–1

1

0

Volta

ge (l

in)

0

1

500mVo

ltage

(lin

)

0500m

–500m

Volta

ge (l

in) 4m

2m

0

0Time (lin) (time)

500n 1μ 1.5μ 2μ

(n)

Figure 6: Input-output waveforms of different applications. (a) Noninverting amplifier. (b) Inverting amplifier. (c) Summer. (d) Subtractor.(e) Differentiator. (f ) Integrator. (g) Half-wave rectifier. (h) Full-wave rectifier. (i) Clipper. (j) Clamper. (k) Inverting comparator.(l) Noninverting comparator. (m) Peak detector. (n) Zero crossing detector.


output one after the other sequentially. Such a full-waverectifier circuit is shown in Figure 5(h), which is actually thecombination of two half-wave rectifier circuits. 'is isachieved using two different op-amps A1, A2 and diodes D1,D2. 'e op-amp A1 output turns out to be positive onlyduring the positive half cycle of the input waveform. V′becomes negative which eventually turns ON the diode D1[41]. 'e voltage at the inverting terminal of A2 appears atthe output, which is equal to the input, due to the virtualground at the two input terminals of op-amp A2. Considernow the negative cycle of the input waveform. In this case,the V′ will be positive, making diode D1 OFF and D2 ON.Due to the virtual ground at the inverting input of op-ampA1, V2 � V1 � V [43]. 'is causes output voltage to be equalto the negative of the input voltage at A1 and thus positive.'erefore, outputs during two half cycles are same and full-wave-rectified output voltage is obtained as shown inFigure 6(h).

4.9. CNFET-FCOA-Based Clipper. As the name suggests,a clipper is a circuit that can remove certain portions of theinput waveform near the positive or negative peaks, i.e., itavoids the output from going beyond a predeterminedvoltage level without adversely affecting the residual part ofthe input waveform. If such a circuit is implemented usingop-amp, a diode is used at the output of op-amp, to removeoff some portion of the input signal. CNFET-FCOA-basedpositive clipper is shown in Figure 5(i). 'is type of circuitconfiscates negative peak of the input signal. 'e value ofreference voltage Vref decides the clipping portion. 'epositive input gets grounded initially when the Vref is zero.Whenever input Vin is positive, the output will follow theinput Vin, since the op-amp output becomes positive,turning ON the diode. 'e op-amp output will go negativeduring negative half cycle of the input. In this case, the finaloutput Vo will follow the negative half cycle of the input tillthe input voltage is greater than the reference voltage only.Hence the portion of the negative half cycle will be clippedfor which input voltage becomes less than the referencevoltage. In order to adjust the clipping level, Vref needs to beadjusted as per requirement.

4.10. CNFET-FCOA-Based Clamper. By using clamper cir-cuits, the output is shifted up or down to a preferred DClevel, i.e., a predetermined DC level is added to the inputvoltage. A variable DC level CNFET-FCOA-based clampercircuit is presented in Figure 5(j). 'is is a positive clamperbecause the input waveform is clamped at +Vref [41]. In thiscase, both AC and DC input voltages need to be applied andoutput of the clamper is a net result of AC and DC inputvoltages applied to the inverting terminal, and a potenti-ometer is connected to noninverting input terminals to varyVref. Initially, ponder +Vref at the noninverting input. 'eoutput voltage (Vo) will also be positive, which turns ON thediode D1 completing the feedback loop. 'e op-amp thenworks as a voltage follower, since capacitor C1 blocks DCvoltage and Vo becomes equal to Vref. Now, consider thevoltage Vin at the inverting input. During its negative half

cycle, capacitor C1 will charge to the negative peak value ofthe voltage (VP) since diode D1 starts conducting. 'e peakvoltage (VP) across the capacitor acquired during the neg-ative half cycle is retained because diode D1 turns OFFduring the positive half cycle of Vin [40]. 'e output peakvoltage Vo becomes equal to 2VP, since this voltage VP is inseries with the positive peak voltage VP. 'us, the net outputis Vo � Vref + VP; so, the negative peak of 2VP is at Vref. 'einput and output waveforms are shown in Figure 6(j).

4.11. CNFET-FCOA-Based Comparator. As the name sug-gests, a comparator is a circuit that compares input signal atone terminal of op-amp with a known reference voltage atthe other input of op-amp. Figure 5(k) shows CNFET-FCOA-based comparator. Consider a fixed reference volt-age Vref of +1V at the inverting input and the other time-varying signal Vin is applied to the noninverting input. 'istype of comparator is called as noninverting comparator.When input voltage Vin is greater than reference Vref, outputvoltage Vo reaches to +Vsat and when Vin becomes less thanreference, Vo changes towards −Vsat. 'us, Vo varies fromone level to another level whenever input increases or de-creases with respect to Vref as shown in Figures 6(k) and 6(l).Hence, this circuit is also termed as “voltage level indicator.”Such inverting, noninverting comparators are needed tointerface analog and digital blocks in mixed signalapplications.

4.12. CNFET-FCOA-Based Peak Detector. As the namesuggests, a peak detector is a circuit which detects thepeak value of applied input signal [41, 43] as shown inFigure 5(m). 'is circuit detects the positive peak of theinput signal. CNFET-FCOA-based peak detector consists ofa series connection of a diode and a capacitor. 'e capacitorC1 gets charged to the peak value Vpp of the input voltage,whenever diode D1 becomes forward biased during everypositive half cycle of the input. On the contrary, thecharge/voltage across capacitor is retained during everynegative half cycle of the input, since the diode D1 isnonconducting and the only discharge path for C1 isthrough the output terminal Vo [41, 43]. 'us, the capacitorretains the peak value even as the waveform drops to zero.

4.13. CNFET-FCOA-Based Zero Crossing Detector. As thename suggests, a zero crossing detector or ZCD is a circuitused to detect a zero crossing condition of input sinusoidalwaveform during transition from positive to negative andvice-a-versa. 'e circuit is similar to the comparator exceptthat the reference voltage is fixed and its value is perma-nently zero. Figure 5(n) shows inverting comparator withinput as sinusoidal waveform. 'e corresponding input-output waveforms are shown in Figure 6(n).

Output of the ZCD, Vo, will be at positive saturationvoltage +Vsat for the values of input waveform greater thanzero and will be at negative saturation voltage −Vsat wheninput signal amplitude is less than zero. Every time when theoutput of op-amp changes from +Vsat to −Vsat, the capacitor


C charges to +Vsat and if the output of op-amp transits from−Vsat to +Vsat, capacitor discharges through R1 to −Vsat.Whenever the square wave crosses zero voltage, the ar-rangement of C1 and R1 generates an output comprising ofpeaks at that time interval. 'e diode is used to remove thepeaks at the zero crossings whenever input voltage crosseszero voltage in increasing direction.

'e resulting waveforms of all the above applications areshown in Figure 6.

5. Conclusions

In this work, we designed and simulated folded cascodeoperational amplifiers (FCOA) using promising CNFETtechnology at 32 nm, a very deep submicron technologynode, at 1 V power supply voltage. 'e relative explorationhas discovered that the CNFET-based FCOAs have beatenthe CMOS-based FCOAs extensively in the nanometer re-gime. 'e conventional CMOS technology is unable toproduce significant gain due to the stringent nonidealeffect in nanometer regime. Further, the stability analysishave revealed the CNTFET-based FCOA to be exceedinglystable.

'e novel CNFET-FCOA is further used to developanalog signal processing circuits such as noninverting am-plifier, inverting amplifier, summer, subtractor, differ-entiator, integrator, half-wave rectifier, full-wave rectifier,clipper, clamper, comparator, peak detector, and zerocrossing detector. All these circuits are successfully imple-mented and are found considerably competent than that ofconventional CMOS-based circuits in nanoscale regime. Ithas also been proved from simulation results that CNFET isa promising nanodevice especially for low-power analogcircuit applications at very deep submicron technologynodes.

Data Availability

Any data and information used to support the findings ofthis study will be provided upon request to the corre-sponding author.

Conflicts of Interest

'e authors declare that there are no conflicts of interestregarding the publication of this paper.

Acknowledgments

'e authors would like to thank Dr. A. M. Fulambarkar,Dr. N. B. Chopade, and Dr. Sheetal Bhandari, PimpriChinchwad College of Engineering, Pune, India, for theirsupport and encouragement. 'ey would also like to thankDr. G. C. Patil, Visvesvaraya National Institute of Tech-nology, Nagpur, India; Dr. M. B. Mali, Sinhgad College ofEngineering, Pune, India; Prof. Ketan Raut, VishwakarmaInstitute of Information Technology, Pune, India; and Dr.Shailaja Patil, JSPM’s Rajarshi Shahu College of Engineering,Pune, India, for many useful discussions and their contin-uous guidance throughout the work.

References

[1] 'e International technology Roadmap for semiconductors:semiconductor industry association,” February 2013, http://www.itrs.net/.

[2] F. Usmani and M. Hasan, “Design and parametric analysisof 32 nm opamp in CMOS and CNFET technologies foroptimum performance,” in Proceedings of the ArgentineSchool of Micro-Nanoelectronics, Technology and Applica-tions, pp. 87–92, San Carlos de Bariloche, Argentina, 2009.

[3] F. Rahman, “Performance evaluation of a 32-nm CNT-OPAMP: design, characteristic optimization and compari-son with CMOS technology,” in Proceedings of 14th In-ternational Conference on Computer and InformationTechnology (ICCIT, 2011), Dhaka, Bangladesh, December2011.

[4] M. A. Kafeel, M. Hasan, M. Shah Alam, A. Kumar, S. Prasad,and A. Islam, “Performance evaluation of CNFET basedoperational amplifier at technology node beyond 45-nm,” inProceedings of Annual IEEE India Conference, INDICON,Mumbai, India, December 2013.

[5] V. Sridevi and T. Jayanthi, “Determination of CNTFETOPAMP parameters,”National Journal on Electronics Sciencesand Systems, vol. 3, no. 2, pp. 56–62, 2012.

[6] P. A. Gowri Sankar and K. Udhaya kumar, “Design andanalysis of two stage operational amplifier based on emergingsub-32 nm technology,” in Proceedings International Con-ference on Advanced Nanomaterials and Emerging Engi-neering Technologies, pp. 587–591, Chennai, India, July 2013.

[7] V. Bendre, A. K. Kureshi, and S. Waykole, “A low power, highswing and robust folded cascode amplifier at deep submicrontechnology,” in Proceedings of 3rd International Conference onInformation and Communication Technology for CompetitiveStrategies, Udaipur, India, December 2017.

[8] S. K. Sinha and S. Chaudhury, “Comparative study of leakagepower in CNTFET over MOSFET device,” Journal of Semi-conductors, vol. 35, no. 11, article 114002, 2014.

[9] J. Deng and H.-S. P. Wong, “A circuit-compatible SPICEmodel for enhancement mode carbon nanotube field effecttransistors,” in Proceedings of International Conference Sim-ulation of Semiconductor Processes and Devices, pp. 166–169,Monterey, CA, USA, September 2006.

[10] G. Cho, F. Lombardi, and Y.-B. Kim, “Modelling a CNTFETwith undeposited CNT defects,” in Proceedings of IEEE 25thInternational Symposium on Defect and Fault Tolerance inVLSI Systems, Kyoto, Japan, October 2010.

[11] B. Young Kim, “A novel design methodology to optimize thespeed and power of the CNTFET circuits,” in Proceedings of52nd IEEE International Midwest Symposium on Circuit sandSystems, Cancun, Mexico, August 2009.

[12] Y.-B. Kim, “Integrated circuit design based on carbonnanotube field effect transistor,” Transactions on Electrical andElectronic Materials, vol. 12, no. 5, pp. 175–188, 2011.

[13] J. Deng and H. S. P. Wong, “A compact SPICE model forcarbon nanotube field effect transistors including non-idealities and its application—Part II: full device model andcircuit performance benchmarking,” IEEE TransactionsElectron Devices, vol. 54, no. 12, pp. 3195–3205, 2007.

[14] J. Guo, A. Javey, H. Dai, S. Datta, and M. Lundstrom, Pre-dicted Performance Advantages of Carbon Nanotube Tran-sistors with Doped Nanotubes as Source/Drain, CondensedMatter 0309039, 2003.

[15] A. Javey, R. Tu, D. B. Farmer, J. Guo, R. G. Gordon, and H. Dai,“High performance n-type carbon nanotube field-effect


http://www.itrs.net/http://www.itrs.net/

transistors with chemically doped contacts,” Nano Letters,vol. 5, no. 2, pp. 345–348, 2005.

[16] G. Cho, Y.-B. Kim, F. Lombardi, and M. Choi, “Performanceevaluation of CNFET-based logic gates,” in Proceedings ofIEEE Instrumentation and Measurement TechnologyConference, Singapore, May 2009.

[17] Z. Yao, C. L. Kane, and C. Dekker, “High-field electricaltransport in single-wall carbon nanotube,” Physical ReviewLetters, vol. 84, no. 13, pp. 2941–2944, 2000.

[18] M. S. Fuhrer, B. M. Kim, T. Dkop, and T. Brintlinger, “High-mobility nanotube transistor memory,” Nano Letters, vol. 2,no. 7, pp. 755–759, 2002.

[19] P. L. McEuen, M. S. Fuhrer, and H. Park, “Single-walledcarbon nanotube electronic,” IEEE Transactions on Nano-technology, vol. 1, no. 1, pp. 78–85, 2002.

[20] G. Pennington and N. Goldsman, “Semiclassical transportand phonon scattering of electrons in semiconducting carbonnanotubes,” Physical Review B, vol. 68, no. 4, 2003.

[21] B. Q.Wei, R. Vajtai, and P.M. Ajayan, “Reliability and currentcarrying capability of carbon nanotube,” Applied PhysicsLetters, vol. 79, no. 8, pp. 1172–1174, 2001.

[22] P. Dwivedi, K. Kumar, and A. Islam, “Comparative study ofsubthreshold leakage in CNFET and MOSFET @ 32-nmtechnology node,” in Proceedings of International Conferenceon Microelectronics, Computing and Communications(MicroCom), Durgapur, India, January 2016.

[23] F. A. Usmani and M. Hasan, “Carbon nanotube field effecttransistors for high performance analog applications: anoptimum design approach,” Microelectronics Journal, vol. 41,pp. 395–402, 2010.

[24] D. Yang, L. Wang, Q. Zhao, and S. Li, “Fabrication of single-walled carbon nanotubes (SWNTs) field-effect transistor(FET) biosensor,” in Proceedings of 3rd International Con-ference on Biomedical Engineering and Informatics, Dalian,China, October 2010.

[25] J. Zheng, Q. Zhang, X. He, M. Gao, X. Ma, and G. Li,“Nanocomposites of carbon nanotube (CNTs)/CuO with highsensitivity to organic volatiles at room temperature,” ProcediaEngineering, vol. 36, pp. 235–245, 2012.

[26] S. A. Loan, M. Nizamuddin, H. Shabir et al., “Carbonnanotube based operational transconductance amplifier:a simulation study,” in Transactions on Engineering Tech-nologies, G. C. Yang, S. I. Ao, X. Huang, and O. Castillo, Eds.,Springer, Dordrecht, Netherlands, 2015.

[27] M. Nizamuddin, S. A. Loan, A. R. Alamoud, and S. A. Abbassi,“Design, simulation and comparative analysis of CNT basedcascode operational transconductance amplifiers,” Nano-technology, vol. 26, no. 39, article 395201, 2015.

[28] A. Imran, M. Hasan, S. D. Pable, and M. W. Akram, “Highperformance optimized CNFET based current conveyor at 32nm technology node,” in Proceedings of International Con-ference on Computer and Communication Technology, ICCCT,Allahabad, India, September 2010.

[29] S. L. Murotiya and A. Gupta, “CNTFET based design ofcontent addressable memory cells,” in Proceedings of 4thInternational Conference on Computer and CommunicationTechnology, ICCCT, Piscataway, NJ, USA, September 2013.

[30] P. A. G. Sankar and K. Udhayakumar, “A novel carbonnanotube field effect transistor based arithmetic computingcircuit for low-power analog signal processing application,”Procedia Technology, vol. 12, no. 7, pp. 154–162, 2014.

[31] L. Stoica, V. Solomko, T. Baumheinrich et al., “Design ofa frequency signal conditioning unit applied to rotatingsystems in high temperature aero engine control,” in

Proceedings of IEEE International Symposium on Circuits andSystems, ISCAS, Lisbon, Portugal, May 2015.

[32] J. S. Ajit, Y.-B. Kim, andM. Choi, “Performance assessment ofanalog circuits with carbon nanotube FET (CNFET),” inProceedings of 20th Great Lakes Symposium on VLSI,pp. 163–166, Providence, RI, USA, May 2010.

[33] A. Balijepalli, S. Sinha, and Y. Cao, “Compact, modeling ofcarbon nanotube transistor for early stage process-designexploration,” in Proceedings of International Symposium onLow Power Electronics and Design, pp. 2–7, New York, NY,USA, August 2007.

[34] T. J. Kazmierski, D. Zhou, and B. M. Al-Hashimi, “HSPICEimplementation of a numerically efficient model of CNTtransistor,” in Proceedings Forum on Specification and DesignLanguages, pp. 1–5, Sophia Antipolis, France, September2009.

[35] M. H. Moaiyeri, R. Chavoshisani, A. Jalali, K. Navi, andO. Hashemipour, “High-performance mixed-mode universalmin-max circuits for nanotechnology,” Circuits, Systems, andSignal Processing, vol. 31, no. 2, pp. 465–488, 2012.

[36] M. H. Moaiyeri, Z. Hajmohammadi, M. Rezaei Khezeli, andJ. Ali, “Effective reduction in crosstalk effects in quaternaryintegrated circuits using mixed carbon nanotube bundle in-terconnects,” ECS Journal of Solid State Science and Tech-nology, vol. 7, no. 5, pp. M69–M76, 2018.

[37] S. Lin, Y.-B. Kim, F. Lombardi, and Y. J. Lee, “A new SRAMcell design using CNTFETs,” in Proceedings of IEEE In-ternational SoC Design Conference, pp. 168–171, Busan, SouthKorea, November 2008.

[38] K. Abdelhalim, L. MacEachern, and S. Mahmoud, “Ananowatt successive approximation ADC with offset cor-rection for implantable sensor applications,” in Proceedings ofIEEE International Symposium on Circuits and Systems,pp. 2351–2354, New Orleans, LA, USA, May 2007.

[39] R. Chavoshisani, M. H. Moaiyeri, and O. Hashemipour, “Ahigh-performance low-voltage current-mode min/max cir-cuit,” COMPEL International Journal for Computation andMathematics in Electrical and Electronic Engineering, vol. 34,no. 4, pp. 1172–1183, 2015.

[40] D. Akinwande, S. Yasuda, B. Paul, S. Fujita, G. Close, andH.-S. P. Wong, “Monolithic integration of CMOS VLSI andcarbon nanotubes for hybrid nanotechnology applications,”IEEE Transactions on Nanotechnology, vol. 7, no. 5,pp. 636–639, 2008.

[41] P. A. Gowrisankar and K. Udhayakumar, “A novel carbonnanotube field effect transistor based analog signal processingcircuits for low-power communication systems,” in EmergingTrends in Computing and Communication. Lecture Notes inElectrical Engineering, S. Sengupta, K. Das, and G. Khan, Eds.,vol. 298, Springer, New Delhi, India, 2014.

[42] D. Sethi, M. Kaur, and G. Singh, “Design and performanceanalysis of a CNFET based TCAM cell with dual-chiralityselection,” Journal of Computational Electronics, vol. 16, no. 1,2017.

[43] S. Raj, D. R. Bhaskar, V. K. Singh, and R. K. Sharma, “Basicsinusoidal oscillators and waveform generators using ICbuilding blocks,” in Sinusoidal Oscillators and WaveformGenerators Using Modern Electronic Circuit Building Blocks,Springer Nature, Cham, Switzerland, 2016.


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