Deterministic Approaches to AnalogDeterministic Approaches to AnalogPerformance Space Exploration (PSE)Performance Space Exploration (PSE)

D. Mueller, G. Stehr, D. Mueller, G. Stehr,

H. Graeb, U. SchlichtmannH. Graeb, U. Schlichtmann

Institute of Electronic Design Automation, TU Muenchen,

Munich , Germany

3

OutlineOutline

• Introduction to Performance Space Exploration (PSE)

• Sizing constraints and structural circuit analysis

• PSE by discretized Pareto Optimal Fronts (DISC)

• PSE by Polytopal Approximations (POLY)

• Application to hierarchical sizing

• Conclusions

4

MotivationMotivation

• Analog circuits in mixed-signal systems:– Signal conversion, clock generation, data acquisition, ...

• Performance Space Exploration (PSE):– For given topology and technology of an analog circuit block determine

its performance capabilities.

– Applications:

• Visualize Trade-Offs between competing performances

• Compare topologies which implement same analog functionality

• Topology selection

• Bottom-up propagation of information about implementation capabilities in a hierarchical sizing process

5

MethodsMethods

• Extensive search: – Parameter sweep: p (CMOS: W,L)

– Performances f obtained by simulation

– (high computational costs)

Feasible performance

space F

OpAmp

6

MethodsMethods

• Extensive search: – Parameter sweep: p (CMOS: W,L)

– Performances f obtained by simulation

– (high computational costs)

– Two deterministic approaches DISC/POLY (see Paper for state-of-the-art)

– What determines the Feasible Performance Space of a circuit block?

• Sizing constraints

Feasible Performance

Space F

• More efficient determination?

OpAmp

7

OutlineOutline

• Introduction to Performance Space Exploration (PSE)

• Sizing constraints and structural circuit analysis

• PSE by discretized Pareto Optimal Fronts (DISC)

• PSE by Polytopal Approximations (POLY)

• Application to hierarchical sizing

• Conclusions

8

Sizing Constraints: Formalized design knowledgeSizing Constraints: Formalized design knowledge

• Basic functional blocks: e. g. current mirror

21 LL

1

2

W

WK

min2,12,1 gsthgs VVv

min2,12,1 AWL

min2,1 LL

min2,1 WW

max12 ds,dsds Vvv

min212121 sat,th,gs,ds VVvv

0;0 21212,1 ,th,gsds Vvv

geometrical electrical

fun

ctio

nro

bu

stn

ess

i1 i2 i2 = K i1

9

Sizing Constraints: Formalized design knowledgeSizing Constraints: Formalized design knowledge

• Basic functional blocks: e. g. current mirror

21 LL

1

2

W

WK

min2,12,1 gsthgs VVv

min2,12,1 AWL

min2,1 LL

min2,1 WW

max12 ds,dsds Vvv

min212121 sat,th,gs,ds VVvv

0;0 21212,1 ,th,gsds Vvv

geometrical electrical

fun

ctio

nro

bu

stn

ess

c(p) ≥ 0

Sizing constraints

Reduced Parameter set

p

Saturation

Robustness against local threshold voltage variations (mismatch)

i1 i2 i2 = K i1

Analog minimum feature size

Reduce effect of channel length modulation

10

Automatic Constraint SetupAutomatic Constraint SetupFolded–Cascode OpAmpFolded–Cascode OpAmpMiller OpAmpMiller OpAmp

VDD

VSS

OutINn Inp

Ibias

VSS

VDD

INp INn

IbiasOut

11

Automatic Constraint SetupAutomatic Constraint SetupFolded–Cascode OpAmpFolded–Cascode OpAmpMiller OpAmpMiller OpAmp

Voltage Ref.

Current Mir. Load

Current Mirror

Level Shifter

Differential Pair

VDD

VSS

OutINn Inp

Ibias

VSS

VDD

INp INn

IbiasOut

12

Automatic Constraint SetupAutomatic Constraint SetupFolded–Cascode OpAmpFolded–Cascode OpAmpMiller OpAmpMiller OpAmp

Voltage Ref.

Current Mir. Load

Current Mirror

Level Shifter

4-T Current Mir.

Current Mir. Bank

Level Shifter Bank

Cascode Cur. Mir.Differential Pair

VDD

VSS

OutINn Inp

Ibias

VSS

VDD

INp INn

IbiasOut

13

Automatic Constraint SetupAutomatic Constraint SetupFolded–Cascode OpAmpFolded–Cascode OpAmpMiller OpAmpMiller OpAmp

Voltage Ref.

Current Mir. Load

Current Mirror

Level Shifter

4-T Current Mir.

Current Mir. Bank

Level Shifter Bank

Cascode Cur. Mir.Differential Pair Differential Stage

Cas. Cur. Mir. Bank

VDD

VSS

OutINn Inp

Ibias

VSS

VDD

INp INn

IbiasOut

14

Automatic Constraint SetupAutomatic Constraint SetupFolded–Cascode OpAmpFolded–Cascode OpAmpMiller OpAmpMiller OpAmp

Voltage Ref.

Current Mir. Load

Current Mirror

Level Shifter

4-T Current Mir.

Current Mir. Bank

Level Shifter Bank

Cascode Cur. Mir.Differential Pair Differential Stage

Cas. Cur. Mir. Bank

VDD

VSS

OutINn Inp

Ibias

VSS

VDD

INp INn

IbiasOut

8 Design Parameters p

62 Sizing Constraints c(p) ≥ 0

11 Design Parameters p

181 Sizing Constraints c(p) ≥ 0

15

OutlineOutline

• Introduction to Performance Space Exploration (PSE)

• Sizing constraints and structural circuit analysis

• PSE by discretized Pareto Optimal Fronts (DISC)

• PSE by Polytopal Approximations (POLY)

• Application to hierarchical sizing

• Conclusions

16

PSE by discretized Pareto Fronts – DISCPSE by discretized Pareto Fronts – DISC

Feasible Performance Space

Pareto Optimal Frontfor max f1, max f2

Utopia point

17

Normal Boundary Intersection – DISCNormal Boundary Intersection – DISC

1. Individual performanceoptima

18

Normal Boundary Intersection – DISCNormal Boundary Intersection – DISC

1. Individual performanceoptima

2. Convex hull, discretized

19

Normal Boundary Intersection – DISCNormal Boundary Intersection – DISC

1. Individual performanceoptima

2. Convex hull, discretized

3. Line search perpendicular to convex hull

20

Topology selection with DISCTopology selection with DISC

Folded–Cascode Folded–Cascode OpAmpOpAmp

Miller OpAmpMiller OpAmp

DC Gain > 75dB Phase Margin > 60o

DC Gain > 75dB Phase Margin > 80o

Folded–Cascode Folded–Cascode OpAmpOpAmp

Miller OpAmpMiller OpAmp

Miller OpAmpMiller OpAmp Folded–Cascode Folded–Cascode OpAmpOpAmp

21

OutlineOutline

• Introduction to Performance Space Exploration (PSE)

• Sizing constraints and structural circuit analysis

• PSE by discretized Pareto Optimal Fronts (DISC)

• PSE by Polytopal Approximations (POLY)

• Application to hierarchical sizing

• Conclusions

22

PSE by Polytopal Approximation - POLYPSE by Polytopal Approximation - POLY

Nonlinear problem

c(p) ≥ 0

P

Simulation

f = f(p)F

k(f) ≥ 0

23

PSE by Polytopal Approximation - POLYPSE by Polytopal Approximation - POLY

Polytope

Nonlinear problem

Lineardescription

c(p) ≥ 0

P

Simulation

f = f(p)F

k(f) ≥ 0

P F

C Δp ≥ c0 K Δf ≥ k0

Δf = F Δp

Linearisation at p0: Δp = p – p0

PolytopeLinear Circuit

Model

24

Results POLY Results POLY

DC Gain > 75dB Phase Margin > 60o

Folded–Cascode Folded–Cascode OpAmpOpAmp

Miller OpAmpMiller OpAmp

25

Comparison POLY-DISCComparison POLY-DISC

Miller OpAmpMiller OpAmp

Folded–Cascode Folded–Cascode OpAmpOpAmp

DC Gain > 75dB Phase Margin > 60o

26

Comparison POLY-DISCComparison POLY-DISC

Miller OpAmpMiller OpAmp

Folded–Cascode Folded–Cascode OpAmpOpAmp

DC Gain > 75dB Phase Margin > 60o

Points of Linearisation

27

Comparison POLY-DISCComparison POLY-DISC

Miller OpAmpMiller OpAmp

Folded–Cascode Folded–Cascode OpAmpOpAmp

DC Gain > 75dB Phase Margin > 60o

Points of Linearisation

DISC POLY

18 min 25 sec 3 sec

55 min 38 sec 1 min 45 sec

Computational time on cluster of 15 Pentium IV

ACCURATEACCURATE FASTFAST

28

OutlineOutline

• Introduction to Performance Space Exploration (PSE)

• Sizing constraints and structural circuit analysis

• PSE by discretized Pareto Optimal Fronts (DISC)

• PSE by Polytopal Approximations (POLY)

• Application to hierarchical sizing

• Conclusions

29

Flat Sizing ProcessFlat Sizing Process

System performances

(fc, Gc, Q)

Circuit parameters

(wMN1,lMN1,…)

Circuit

sizing

System

specification

CIR

CU

IT L

EV

EL

30

Hierarchical Sizing ProcessHierarchical Sizing Process

System performances (fc, Gc, Q)

System parameters

(gm(OTA8), CT(OTA8),…)

Circuit performances

(gm,φ(fc),…)

Circuit parameters

(wMN1,lMN1,…)

System

specification

System

sizing

Circuit

sizing

SY

ST

EM

LE

VE

LC

IRC

UIT

LE

VE

L

=Circuit

specification

↓

31

Hierarchical Sizing ProcessHierarchical Sizing Process

System

specification

System

sizing

Circuit

sizing

SY

ST

EM

LE

VE

LC

IRC

UIT

LE

VE

L Circuit

specificationPerformance Space

Exploration

Feasible system parameters

System level constraints

↑↓

WE NEEDWE NEED

Too ambitious

system sizing

Unrealistic

circuit specifications

↓

Circuit sizing can not meet

specification

TO AVOIDTO AVOID

Resizing Loop

32

Hierarchical Sizing of OTA-C FilterHierarchical Sizing of OTA-C FilterSizing without system constraints Sizing with system constraints

Filter Spec. fc = 2 MHz;

Gc ≥ 20 dB; Q ≥ 15

SY

ST

EM

LE

VE

LC

IRC

UIT

LE

VE

L

33

OTA 5 spec. gm = 205.1 μS

Cin = 32.9 fF φ(fc) = 174.0 deg

Rout = 184.4 MΩ Cout =

21.6 fF

Hierarchical Sizing of OTA-C FilterHierarchical Sizing of OTA-C Filter

fc [MHz] Gc [dB] Q

1.998 20.01 21.14

Sizing without system constraints Sizing with system constraints

OTA 5 spec. gm = 205.1 μS

Cin = 32.9 fF φ(fc) = 174.0 deg

Rout = 184.4 MΩ Cout =

21.6 fF

fc [MHz] Gc [dB] Q

2.001 20.64 16.23

OTA 5 spec. gm = 205.1 μS

Cin = 32.9 fF φ(fc) = 174.0 deg

Rout = 184.4 MΩ Cout =

21.6 fF

Filter Spec. fc = 2 MHz;

Gc ≥ 20 dB; Q ≥ 15

OTA 5 Spec. gm = 205.1 μS

Cin = 32.9 fF φ(fc) = 174.0 deg

Rout = 184.4 MΩ Cout = 21.6 fF

OTA 5 spec. gm = 205.1 μS

Cin = 32.9 fF φ(fc) = 174.0 deg

Rout = 184.4 MΩ Cout =

21.6 fF

OTA 5 Spec. gm = 299.7 μS Cin = 32.57 fF

φ(fc) = 175.3 deg Rout =

229.4 MΩ Cout = 22.9 fF

System level sizing System level sizing

SY

ST

EM

LE

VE

LC

IRC

UIT

LE

VE

L

34

OTA 5 spec. gm = 205.1 μS

Cin = 32.9 fF φ(fc) = 174.0 deg

Rout = 184.4 MΩ Cout =

21.6 fF

Hierarchical Sizing of OTA-C FilterHierarchical Sizing of OTA-C Filter

fc [MHz] Gc [dB] Q

1.998 20.01 21.14

gm

[μS ]Cin

[fF]φ(fc) [deg]

Rout

[MΩ]Cout

[fF]

204.9 30.3 174.0 184.6 21.8

fc [MHz] Gc [dB] Q

2.001 20.23 15.46

Sizing without system constraints Sizing with system constraints

OTA 5 spec. gm = 205.1 μS

Cin = 32.9 fF φ(fc) = 174.0 deg

Rout = 184.4 MΩ Cout =

21.6 fF

fc [MHz] Gc [dB] Q

2.001 20.64 16.23

fc [MHz] Gc [dB] Q

1.972 14.98 12.34

gm

[μS ]Cin

[fF]φ(fc) [deg]

Rout

[MΩ]Cout

[fF]

297.1 28.6 174.2 122.4 28.57

OTA 5 spec. gm = 205.1 μS

Cin = 32.9 fF φ(fc) = 174.0 deg

Rout = 184.4 MΩ Cout =

21.6 fF

Filter Spec. fc = 2 MHz;

Gc ≥ 20 dB; Q ≥ 15

OTA 5 Spec. gm = 205.1 μS

Cin = 32.9 fF φ(fc) = 174.0 deg

Rout = 184.4 MΩ Cout = 21.6 fF

OTA 5 spec. gm = 205.1 μS

Cin = 32.9 fF φ(fc) = 174.0 deg

Rout = 184.4 MΩ Cout =

21.6 fF

OTA 5 Spec. gm = 299.7 μS Cin = 32.57 fF

φ(fc) = 175.3 deg Rout =

229.4 MΩ Cout = 22.9 fF

System level sizing System level sizing

Circuit level sizing Circuit level sizing

SY

ST

EM

LE

VE

LC

IRC

UIT

LE

VE

L

35

OutlineOutline

• Introduction to Performance Space Exploration (PSE)

• Sizing constraints and structural circuit analysis

• PSE by discretized Pareto Optimal Fronts (DISC)

• PSE by Polytopal Approximations (POLY)

• Application to hierarchical sizing

• Conclusions

36

ConclusionsConclusions

Support designer in comparing different topologies for implementing a given analog functionality

Provide information about underlying implementations on system level avoiding resizing loops

Deterministic Performance Space Exploration Approaches

based on sizing constraints

POLYDISCACCURATE FAST