Developing fast clock source with deterministic jitter

Final review Part A

Yulia Okunev Supervisor -Yossi HipshHS-DSL Laboratory, Dept. of Electrical EngineeringTechnion Israel Institute of Technology

24.12.201412Background

In this project I designed fast clock source with deterministic jitter for high speed phenomena experiment.Jitter [1] is the deviation of a periodic signal, in this case, clock source, from its ideal period. Or in other words the period frequency displacement of the signal from its ideal location.System overview:Pulse generator is used to produce electrical input signal.This clock signal will be divided to 8 channels.Each signal passes through delays array and combined in the output.Using Scope we can measure the system output. Project Top Block diagram

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Two-way couplingSolution algorithm

4Passive delays array:We created 8 different length transmission lines which causes the signal to delay respectively to the line length.The lines will be printed on the top/bottom layer of the PCB (microstrip)

Passive clock divider/combiner:We created divider (combiner) for the clock signal using resistor divider (combiner)

Theory and calculations

56Transmission lines Parameters

8 high speed lines, impedance of 50, on top/bottom layer microstrip lines. Main signal period is 4 nsec. we will create 0.5 nsec clock from the main signal

To create between each pair of adjacent transmission lines the required is: 8cmWe chose to be smaller than the input signal period.This way the input signal contains the divided signal in one period as shown:

67Transmission lines Parameters-cont..

We can control by choosing different We can reduce/ increase the propagation time in each line by reducing/ increasing its length

We will observe the Jitter phenomena as a function on the accuracy of line length

Input signalIdeal outputJitter in output

Schematic

89Schematic-Step 1

At the first step we implemented the divider and the combiner in the same symmetrical way. A basic model of a passive power splitter\combiner:

this way there is 50 ohm matching after the signal is divided

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10Schematic-Step 1

Passive delays arrayPassive clock dividerPassive clock combinerJunction modelPassive clock dividerPassive clock combinerIs a mirror image ofJunction model11Schematic-Step 1

We planed to use 16.6ohm from VISHAY that seemed to be available in a wide resistance range.After connecting with VISHAY (and few other companies) we learned that only 50ohm resistors are available in stock.To create 16.6ohm resistor we need to use three 50ohm resistors in parallel > increases cost X3

1112Schematic-Step 2

We implemented semi symmetrical junction (to spare resistors and space on the board).It is possible only for the power divider since the signals spreads in all channels simultaneously without reflections back to the source.

this way there is 50 ohm matching after the signal is divided

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13Schematic-Step 2

Passive delays arrayPassive clock dividerPassive clock combinerJunction modelPassive clock dividerPassive clock combinerJunction model14Schematic-Step 3

In order to get an accurate results from the simulation, at this point, we had to design the implementation of the junctions on layout, and than run the simulation with the accurate transmission lines sizes.

14Simulation

1516SimulationInput signal to output signal

Input signal data:Period =4 nsecAmplitude=881.185mV

Output signal data:Amplitude=27.557mV

Attenuation between Input signal and Output signal: 30.1dBThis is sufficient for our needs

1617SimulationInput signal to output signal

We can observe a Transitional Phenomenon that occurs due to signals reflections back to the input.

After few clock cycles the output signal stabilizes on a steady DC average voltage.

We will look at the signal at its steady state as shown in the next slide.

1718SimulationOutput signal to undesired output signal

Zoom in on the output

We can define a threshold of 24mV that will separate between the positive and negative clock edge.This way we can clearly identify the pulse of our generated clock signal.

19Simulationoutput signal

The length of the lines , to create between each pair of adjacent transmission lines should be: 0.083m, 0.166m, 0.249m, 0.332m,0.415m 0.498m, 0.581m, 0.664m

Main signal period is 4 nsec

Generated clock period 0.5 nsec

Board stuck-up andComponents2021Stuck-up

We decided to use 4 layer stuck-up, even though 3 layers is enough for our needs it doesnt make a significant difference in terms of price. And the 4 layers stuck-up is more commonly used in the industry. 22Components

Resistors:Value: 50 ohm. Size: 0603Power consumption: 0.125W (maximal power in circuit: )

Connectors: BNC

Summary andSteps in PART B2324Summary

We examined the theory and obstacles of real implementation of fast clock source on PCB

We took in consideration the stuck-up we will use, the junction implementation, the number of components and their physical size on the PCB

We created an accurate and compatible to real implementation simulation

We got satisfying results

25Next steps PART B

Create an accurate drawing of the transmissions line on the board

Make a preliminary assessment of the board size

Give the files to Ella (CAD designer) for implementation on the PCB using CADENCE (CAD tool)

Building an engineering model to demonstrate sustainability

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26Thank youYulia Okunev27Reference

[1] http://www.antelopeaudio.com/

[2] http://il.farnell.com/ - Resistors from FRANELL company