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Nuclear Instruments and Methods in Physics Research A 598 (2009) 591–597

Contents lists available at ScienceDirect

Nuclear Instruments and Methods inPhysics Research A

0168-90

doi:10.1

� Corr

Aerospa

E-m

journal homepage: www.elsevier.com/locate/nima

Development of a low-noise, two-dimensional amplifier array

Tetsuichi Kishishita a,b,�, Hirokazu Ikeda a, Takuto Sakumura c,Ken-ichi Tamura a,b, Tadayuki Takahashi a,b

a Institute of Space and Astronautical Science, Japan Aerospace Exploration Agency, Sagamihara, Kanagawa 229-8510, Japanb Department of Physics, The University of Tokyo, Bunkyo, Tokyo 113-0033, Japanc RIGAKU Co., Ltd., Akishima, Tokyo 196-8666, Japan

a r t i c l e i n f o

Article history:

Received 21 April 2008

Received in revised form

12 August 2008

Accepted 24 September 2008Available online 17 October 2008

Keywords:

ASIC

VLSI

Analog front-end

Low noise

CdTe

X-ray

Gamma-ray

02/$ - see front matter & 2008 Elsevier B.V. A

016/j.nima.2008.09.043

esponding author at: Institute of Space and

ce Exploration Agency, Sagamihara, Kanagaw

ail address: kisisita@astro.isas.jaxa.jp (T. Kish

a b s t r a c t

This paper describes the recent development of a low-noise, two-dimensional analog front-end ASIC for

hybrid pixel imaging detectors. Based on the Open-IP LSI project, the ASIC is designed to meet a low-

noise requirement of better than 100e� (rms) with self-triggering capability. The ASIC is intended for

the readout of pixel sensors utilizing silicon (Si) and cadmium telluride (CdTe) as detector materials for

spectroscopic imaging observations in the X-ray and gamma-ray regions. The readout chip consists of a

4� 4 matrix of identical 270mm� 270mm pixel cells and was implemented with TSMC 0:35-mm CMOS

technology. Each pixel cell contains a charge-sensitive amplifier, pole-zero cancellation circuit, shaper,

comparator, and peak hold circuit. Preliminary testing of the ASIC achieved an 88e� (rms) equivalent

noise charge and a 25e�=pF noise slope with power consumption of 150mW per pixel.

& 2008 Elsevier B.V. All rights reserved.

1. Introduction

The development of hybrid pixel detectors for particledetection with high spatial resolution in high energy physicsexperiments has spun off a number of developments withapplications in imaging, most notably biomedical imaging, andalso imaging in X-ray astronomy. Particularly, in high-energyastrophysics, the hard X-ray imagers that can reconstruct hardX-ray images originating from astronomical point sources withhigh spatial and high energy resolution at a moderate data rateare the focus of development in studying the non-thermaluniverse.

So far, cadmium telluride (CdTe) pixel detectors, with highstopping power and good energy resolution, are one of theprincipal detector materials for the next-generation hard X-rayimager. The hard X-ray imager consists of a super-mirror hardX-ray telescope and CdTe pixel detectors on a focal plane [1].A two-dimensional readout ASIC assembled with CdTe pixeldetectors using the stud-bump technique provides a signalprocessing circuit for each pixel of the detector. To take advantageof the mirror, the readout ASIC must meet several requirements asfollows: (a) low-noise performance better than 100 electrons

ll rights reserved.

Astronautical Science, Japan

a 229-8510, Japan.

ishita).

(rms) with self-trigger capability and a timing resolution of a fewtens of microseconds, (b) pixel size of about 250mm� 250mm toassemble with CdTe pixel detectors, and (c) low power consump-tion of about 200mW per pixel to comply with a limited powerbudget. Thus, a two-dimensional readout ASIC with excellentspectroscopic performance is a key element for hard X-rayimagers.

In the past few years, we developed several prototype ASICs toestablish circuit designs and readout architectures in the Open-IPLSI project led by JAXA (see Ref. [2]). As the first step ofprototyping, we developed a 32� 32 two-dimensional analogASIC with TSMC 0:25-mm CMOS technology [3,4]. Each pixel cellcontains a charge-sensitive amplifier (CSA), three-stage shapingamplifiers and comparator circuits, with special care taken inthe layout to set the circuits in pixel cells of 200mm� 200mm. Inthe preliminary tests of the ASIC, we demonstrated a two-dimensional pixel readout scheme and obtained a mean noiselevel of 279e� (rms) with power consumption of 110mW perpixel [5].

We subsequently fabricated an eight-channel low-noise analogASIC with TSMC 0:35-mm CMOS technology [6]. The mainobjective for the ASIC is to construct a set of verified designs ofcircuit blocks to be used for two-dimensional ASICs and establisha low-noise architecture. In the performance measurements, weobtained an equivalent noise level of 130e� (rms) and an energyresolution of 2.4 keV for 60 keV gamma rays with a CdTe diodedetector [7].

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T. Kishishita et al. / Nuclear Instruments and Methods in Physics Research A 598 (2009) 591–597592

In order to improve the analog performances of the two-dimensional ASIC [5], we developed a new 4� 4 two-dimensionalanalog ASIC by utilizing the low-noise circuit architecture ofthe one-dimensional ASIC [6]. Our objective mainly placesemphasis on achieving good energy resolution from detectors inthe energy range of 10–80 keV, with a typical counting rate lessthan 100 cnt/s per pixel. The ASIC is designed to meet a low-noiserequirement of better than 100e� (rms) with a detectorcapacitance of 1 pF, self-triggering capability, and a powerconsumption of 150mW per pixel.

This paper reports the design and preliminary test results ofour low-noise, two-dimensional readout ASIC. Section 2 describesthe basic structure of the ASIC and details the circuit schematics.Although the circuit architecture in the shaper circuit is the sameas in the previously developed low-noise ASIC [6], we employeda transfer gate-type FET as a feedback component in the CSAcircuit, which is not employed in the previous ASIC, and alsoincluded a pole-zero cancellation (PZC) circuit. Section 3 presentsthe setup of the performance measurements. Section 4 gives the

Fig. 1. Photograph of the two-dimensional ASIC. The chip size is 2:95� 2:95 mm2 with

has a bonding pad for assembling with a pixel detector.

preliminary experimental results of the ASIC. Finally, Section 5gives a summary and conclusion.

2. Circuit description

2.1. Overview of the ASIC

The readout ASIC is implemented with TSMC 0:35-mm CMOStechnology and has a chip size of 2:95 mm� 2:95 mm. In the ASIC,16-channel pixel cells of 270mm� 270mm are arranged in a 4� 4matrix. Fig. 1 shows a photograph of the ASIC. Each pixel cell has abonding pad area of 40mm� 40mm for assembly with a pixeldetector. The peripheral circuits contain bias circuits and shiftregisters used for pixel selection (Fig. 2). Among the 16 channels,the outer four pixel cells are connected to bonding pads and theother 12 channels are isolated. These four channels can be usedfor evaluating spectral performance when connected to the Siand CdTe detectors. The power consumption in each pixel cell is

16-channel pixel cells of 270� 270mm2 arranged in a 4� 4 matrix. Each pixel cell

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Fig. 2. Block diagram of the ASIC. Bias voltages are supplied from the bottom module. Shift registers used for pixel selects are contained in CAPTOP and CAPLEFT modules.

Analog inputs of the outer four pixel cells are connected to bonding pads.

Table 1Overview of the ASIC

Fabrication process TSMC 0:35-mm CMOS

Chip size 2:95� 2:95 mm2

Number of channels 16

Pixel size 270� 270mm2

Power consumption in each pixel 150mW

Total power consumption 9.9 mW

Power rail �1:65 V

T. Kishishita et al. / Nuclear Instruments and Methods in Physics Research A 598 (2009) 591–597 593

150mW and the total power consumption including the periph-eral circuits is 9.9 mW for the power rails of �1:65 V. LVDS digitalsignals are used to control the ASIC (Table 1).

2.2. Analog processing

Fig. 3 shows the analog circuit in a pixel cell. The signalprocessing chain consists of a CSA, PZC circuit, shaper, comparator,and peak hold circuit. To achieve lower power consumption andplug into a limited pixel space, we modified the overallarchitecture in comparison with the previous ASIC designs [6].The key changes are as follows: (a) two shaper circuits withdifferent shaping time constants are unified to a common circuit,(b) CMOS switches are inserted in front of the buffer circuitsprovided for monitoring analog output signals (with the switchesactivated only when the monitor pixel is selected), and (c) ESDprotection circuits were not employed at CSA inputs.

Fig. 4 shows the schematic of the preamplifier circuitemployed for the CSA. The preamplifier circuit is based on a

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R1

R2

C1

C2

NOTA

Buffer

Analog

Out

Cf

POS

Comparator HITX

TPENB

CinCdif

OP1

VSS

HITY

VSS

Buffer

Vbias

VGG

TRK

TRK

POS

HOLD

VSS

VDD

RpzRf

Ch

POS

OP2

BAND-PASS FILTERD[0:3] DAC

Fig. 3. Signal processing chain for each pixel cell. Here, typical values of the capacitors and resistors are Cin ¼ 0:1 pF, Cf ¼ 0:02=0:04 pF, Cdif ¼ 1:2 pF, C1 ¼ C2 ¼ 0:2 pF,

R1 ¼ 6MO, R2 ¼ 1:5MO. Rf and Rpz are in the range of several M O adjusted with gate voltage VGG.

AOUT

VDD

VH

AIN

VL

VSS

M1

M2

M3

Fig. 4. Schematic of the preamplifier circuit.

T. Kishishita et al. / Nuclear Instruments and Methods in Physics Research A 598 (2009) 591–597594

conventional cascade configuration with an input PMOS transis-tor. We chose a PMOS transistor as an input transistor (i.e. M1) interms of 1=f noise. In order to optimize low-noise performance,we allocated a large value of 8mm to the gate width, and 18 to the‘‘M value’’ (denoting the number of transistors arranged inparallel). The gate length is 1:8mm. In order to maintain thelow-noise characteristics, we also inserted MOS capacitors M2 andM3 to stabilize the voltage between VH and VDD, and between VLand VSS.

As shown in Fig. 3, we employed a transfer gate-type FET forthe feedback component as is often used in several low-noiseASICs (see Refs. [8–13]). However, the nonlinear response of thefeedback component generates waveform distortion that resultsin undershoot or overshoot at shaper circuit output. To eliminateundershoot, we inserted a capacitor Cdif and FET Rpz to configure aPZC circuit (e.g. Refs. [14–16]).

The architecture of the shaper circuit fundamentally adheres tothat of the previously designed ASIC [6], and the shaping time

constant is set at 5ms. The output of the shaper circuit is split intothe peak hold circuit and comparator circuit. The peak hold circuitconsists of a peak-detect circuit and a hold circuit. In the peak-detect circuit, we employed different operational amplifiers toconstruct CMOS diode configurations for each polarity of the inputsignals. The peak-detect circuit is enabled by releasing the ‘‘TRK’’signal and the peak-detect circuit output can be quickly held in aMOS capacitor by a properly timed external ‘‘HOLD’’ signal inconcert with the comparator hit signals. The output of the peakhold circuit is fed into a multiplexer to be sequentially processedby an external A-to-D converter.

The hit signals are generated in the comparator block byreferring to an analog ground level. Baseline adjustment isachieved with a current DAC controlled by signals provided bycontrol registers. The output of the adjustment DAC is summedwith the shaper circuit output and fed to the reference terminal ofthe discriminator.

2.3. Transfer function

The transfer function of the CSA is given as

T1ðsÞ ¼ �Rf

1þ sCf Rf(1)

where s denotes the complex angular frequency, Rf the feedbackresistance, and Cf the feedback capacitance. The PZC networkshown in Fig. 3 modifies the transfer function as

T1ðsÞ0¼ �Q in

Rf

1þ sCf Rf�1þ sCdif Rpz

Rpz(2)

where Cdif and Rpz denote capacitance and resistance in the PZCcircuit, respectively. By setting the parameters as

Cdif Rpz ¼ Cf Rf (3)

the ‘‘pole’’ associated with the signal decay of the CSA iscompensated by ‘‘zero’’ of the PZC, and undershoot can beeliminated [17]. The above equation can be rewritten as

T1ðsÞ0¼ �Q in

Cdif

Cf. (4)

For impedance matching, we set the M values of Rf and Rpz, whichindicate the number of FET gates arranged in parallel, at 1:30.

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The transfer function of the shaper circuit shown in Fig. 3 canbe written as

T2ðsÞ ¼ �R1

s2C1C2R1R2 þ sR1C1 þ 1. (5)

By setting the parameters as C1R1 ¼ 4C2R2, the above equationcan be rewritten as

�R1

ð2sC2R2 þ 1Þ2. (6)

This circuit has a degenerated pole at s ¼ �1=2C2R2 and functionsas low-pass filter. Eventually the entire transfer function of thesignal processing chain is given by T1ðsÞ

0� T2ðsÞ, which yields

Q inCdif

Cf�

R1

ð2sC2R2 þ 1Þ2. (7)

Fig. 5. Measured analog waveform traces of the outputs of the CSA and shaper

circuit. The injected charges were 2 fC.

2.4. Control scheme

Each pixel cell contains a 10-bit configuration register. Fourbits are used for coarse baseline equalization (35 mV/bit), four bitsfor fine adjustments (5 mV/bit), one bit for masking noisy channel,and one bit to enable test pulse input. Entire bits are stored inD-type flip–flops that can be accessed by using peripheral shiftregisters, which also consist of D-type flip–flops and are aligned inX and Y coordinates for pixel selection. A simple protocol is usedto operate configuration registers along with three controllines (for data input, write clock signals and write-enable signals).The polarity of input signals and the gain of preamplifiers(Cf ¼ 0.02 or 0.04 pF) can be selected by a common setting overall the channels.

The sparse readout scheme is borrowed from the previouslydesigned two-dimensional ASIC [5]. The readout sequenceproceeds in two steps: reading the hit pattern and reading outanalog outputs from selected pixels. The outputs of the compara-tor circuit are summed over the entire chip to be fed into anexternal trigger circuit. The trigger signals are also summed overrow and column, with x-hit and y-hit signals being projected intothe peripheral circuits to be recorded in a X–Y coordinate registerfor the corresponding event. Then the hit pattern is read out, thehit pixel selected, and the A-to-D conversion cycle activatedaccording to the hit pattern.

3. Setup for performance measurements

The ASIC placed in a QFP ceramic package was held in a burn-in socket mounted on a test board. The interface with a computerwas established using a National Instruments PCI-7833R boardcontaining a reconfigurable FPGA and A-to-D converters. LabVIEWsoftware tools were used to control the readout sequence.

Fig. 6. Measured analog waveform traces of the outputs of the shaper and peak

hold circuits. The dot-dash lines indicate the SPICE simulation results. The injected

charges were 2 fC.

4. Experimental results

4.1. Waveforms of analog outputs

We have confirmed basic operation of the ASIC by injecting testpulses and checking analog signals from the monitor outputs for10 chips (i.e. total of 160 channels). Fig. 5 shows the outputs of theCSA and shaper circuit with three different decay time constants(Cf Rf ). Test pulses equivalent to input charges of 2 fC are injectedwith Cf ¼ 0:02 pF in each measurement. The PZC is successfullyoperated to suppress undershoot even if the decay time constant

is comparable with the shaping time constant of the shapercircuit.

The upper and lower panels in Fig. 6 show the outputs of theshaper and peak hold circuit, respectively. The dot-dash linesindicate the SPICE simulation results. The shaper and peak holdcircuits are operated properly for either positive or negative inputsignals. The shaping times are a bit longer than the simulation anda small overshoot is observed. The difference of the shaping timescomes from a variation in resistance values of R1 and R2 in Fig. 3.Since the high-resistance circuits for the shaper include a 20 kOpolysilicon resistor [6], the effective resistance value suffers froma semiconductor process variation and results in a longer shapingtime. As for the small undershoot, the waveform of the SPICEsimulation does not show any significant overshoot for a relativefluctuation of Cf , Cdif in Eq. (2), and VGG. One possibleinterpretation comes from interferences between the monitorline of the shaper output and the input pad of the CSA. However,our application does not require high counting rate and theseinfluences can be negligible.

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Fig. 7. Linearity curve of a typical channel. The measured data points (red:

Cf ¼ 0:02 pF, blue: Cf ¼ 0:04 pF) are shown. The lower plots indicate the residuals

between the data points and linear functions.

Fig. 8. Equivalent noise distribution.

Fig. 9. Input capacitance versus equivalent noise level. The dot line shows results

from a circuit simulation.

Fig. 10. Baseline distributions before and after adjustment.

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4.2. Linearity and dynamic range

Fig. 7 shows the linearity curves of a typical channel. Theconfiguration settings are the same for both negative and positiveinput signals. The lower panel shows the residuals between themeasured data points and linear functions. Different linearfunctions are used for calculating the residuals between positiveand negative polarities. Except for a small range of positive inputcharges, good linearity is maintained with an integral nonlinearity

of 1% in a range of �6 to +5 fC with Cf ¼ 0.02 pF, while in a rangeof �12 to +9 fC with Cf ¼ 0.04 pF.

4.3. Noise performance

Fig. 8 shows the equivalent noise distribution for inputcapacitance of 0 pF. Electronic noise is normalized by the responseto a test pulse. The injected charge was �2 fC with the feedbackcapacitor of 0.02 pF. We used 12 isolated channels per chip over atotal of five chips for the measurement. The mean noise level is88� 7:6e� (rms) with power consumption of 150mW per pixel,while the theoretically expected noise level is 48e� (rms). Thenoise performance highly improved from the previously designedASIC [6], however, there is still some room for noise improvementin the experimental setup. The current ASIC assembled in aceramic package is tested with a burn-in socket and exposed in anexogenous noise environment. The ESD protection circuit at theinput node of the CSA is removed in this design to eliminatepossible origin of noise source. Since the capacitance of the CdTe

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pixel detector is about 1 pF per pixel, the total noise level willsatisfy our noise requirement of less than 100e�.

We measured the noise slope using the outer four channelsconnected to a DIP socket mounted on the test board. Fig. 9 showsthe input capacitance versus noise level (ENC). Although the noiseslopes are nearly consistent with the simulation results, thecurves have excess noise of 380e�. That excess noise does notoriginate from parasitic noise due to an assembly issue. It turnsout that the wiring trace for the pixel to the bonding padcapacitively introduces positive feedback to the CSA input andthen, it results in circuit oscillation.

4.4. Baseline distribution

Fig. 10 shows the distribution of the output baselines. Weadjusted the baselines to analog ground level to confirm thebaseline adjustment range. Except for a few channels, the baselinedistribution after applying the baseline adjustment is 1.66 mV,which is comparable with noise fluctuation.

5. Summary

We developed a low-noise, 16-channel two-dimensionalamplifier array with TSMC 0:35-mm CMOS technology in theOpen-IP LSI project for future use in hard X-ray astronomy. Theentire chip consists of 4� 4 matrix of identical 270mm� 270mmpixel cells, each of which includes a charge-sensitive amplifier,shaper, comparator, and peak hold circuit. In the preliminary testof the ASIC, the mean equivalent noise level reached 88e� þ25e�=pF (rms) with power consumption of 150mW per pixel.Except the pixel size, the analog performances satisfy our noiserequirement of less than 100e� with a detector capacitance of1 pF, and power limits of 200mW per pixel. In the following step,we will bump the ASIC with a CdTe pixel detector and evaluate itsspectroscopic properties.

Since the circuit designs are developed in each functionblock, we can easily apply these circuit architectures to multi-channel ASICs for X-ray and gamma-ray imaging applications. This

easy-to-use expandability supported by the good performancelevels of the ASIC will lead to more applications in addition toastrophysical ones, including medical and industrial applications.

Acknowledgments

The authors would like to express their sincere gratitude forthe financial support of JAXA with regards to the SteeringCommittee of Space Engineering. T. Kishishita is supported byresearch fellowships of the Japan Society for the Promotion ofScience for Young Scientists.

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