Development of a Test Bench for the ATLAS NSW Repeater boards

Maria Myrto Prapa

Annual Meeting of the Institute of Nuclear and Particle Physics,

NCSR “Demokritos” - 15/11/2019

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Presentation Outline

• Development of the FPGA Mezzanine Card• Testbench at ELEA Lab

• Development of Firmware for the Virtex-7 Evaluation Board • Testing Results (featuring the Vivado GUI)

• What’s Next

As seen on T. Geralis speech yesterday :

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Development of the FPGA Mezzanine Card

PCB Design - Before and After Production

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Development of the FPGA Mezzanine Card

Main Features (for Serial Repeaters):• 4 MiniSAS Connectors = 16 Multi-Gigabit Differential

Pairs Routed to both FMC Connectors• 4 SMA Connectors = 2 Differential Reference Clocks

routed to their respective FMC Connector, each corresponding to a Quad

• Supports bit rates up to 5 Gbps.• Optimal Position of components (and traces/ conservative design rules) to ensure minimal length

of traces.• Simultaneous Testing of two Serial Repeaters• Strenuous self-testing passed to ensure signal

integrity for testing.

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Development of the FPGA Mezzanine Card

Main Features (for LVDS Repeaters):• 12 MiniSAS Connectors = 96 Differential Pairs

Routed to both FMC Connectors• Supports the testing of a single LVDS Repeater

Board.• Loopback of even to odd MiniSAS Connectors.

• Supports the 640 Mbps bit rate of the Repeaters.• Focus on reliability and signal integrity, especially

upon simultaneous LVDS and Serial Repeaters testing.

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Development of the FPGA Mezzanine Card:Test Bench at NCSR Demokritos

One quad in loopback mode, one quad having the serial repeater under testing.

The FMC is connected through two HPC to the Virtex-7 Evaluation Board.

The SMA connectors are connected to the Clock Synthesizer.

Not shown: Power Source for the Repeater.

vc707 evaluation board

FMC board

Clock SynthesizerSerial Repeater

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Development of Firmware for the Virtex-7 Evaluation Board

vc707 evaluation board

FMC board

Clock Synthesizer

Serial Repeaters Testing: Done using the Integrated Bit Error Ratio Tester (IBERT) and Vivado Serial IO Analyzer• GUI capable of producing eye diagrams along with powerful customization options on the Multi-Gb

Transceivers: Testing on Different Patterns, Tx Pre-Cursor/Post-Cursor, Termination Voltage etc.• Both loopback links and repeater have been tested in every supported set of settings.• Errors only due to faulty chips, inadequate boosting, cable attenuation and voltage drops.

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Development of Firmware for the Virtex-7 Evaluation Board

vc707 evaluation board

FMC board

Clock Synthesizer

LVDS Repeaters Testing: Done using the Integrated Logic Analyzer (ILA) Cores and Virtual IO (VIO) Core for User Resets/Customization.

• User Interface that supports waveforms for RX Data and RX Data Errors.

• Boards tested using a 7-bit PRBS Pattern; Can change width/inject errors.

• RX/TX are aligned and compared through FSM logic.

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What’s Next

Clock Synthesizer

• Completion of testing for the LVDS and Serial Repeaters.• Ethernet Connectivity: The Virtex-7 Evaluation Board supports

connections through Ethernet- processing testing results outside of Vivado.

• GUI: If Ethernet Connectivity is achieved, a GUI can be developed to create log files and simplify the interaction between user and firmware.

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Summary

FMC Board: Reliable, designed for Performance/Signal Integrity over extended testing periods.

Firmware: Customized to fit testing needs, makes the most out of the FPGA Capabilities and the Vivado GUI- may be further customized.

…any questions?