device and compact circuit-level modeling of graphene...

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 65, NO. 8, AUGUST 2018 2559

Device and Compact Circuit-Level Modelingof Graphene Field-Effect Transistors for

RF and Microwave ApplicationsLei Sang , Yulong Xu, Yun Wu, and Rongmin Chen

Abstract— Graphene field-effect transistors (GFETs) arepromising candidates for future nano-electronic circuitry withexcellent radio frequency (RF) and microwave performance dueto the ultra-high carrier mobility, large saturation velocity, andgood electrical conductivity of the graphene channel. In thispaper, a compact circuit-level model of GFETs is proposed forRF and microwave high-frequency applications. An improveddouble-gate monolayer short channel GFET with an agate lengthof 150 nm was first designed and fabricated by self-alignedgate processing, enabled by optimized organic, contamination-free graphene transfer, for realizing high working frequency upto 40 GHz. A compact, precise circuit-level model, includingthe linear and nonlinear operation of GFETs, is then proposedwith model parameters extracted based on the test data fromthe fabricated GFETs. The proposed model is capable of pre-cisely simulating the ambipolar status of GFETs working up tomicrowave frequency. The calculated errors of the S-parameters,the reflection coefficient, the gain, (all in decibel), and theI–V data (in decimal) are less than 3.5%, 4.1%, 3.1%, and2.4%, respectively. By defining as the symbolically defined devicemodule, the GFET model with gate dimensional scalability canbe easily embedded in the common commercial simulators forRF and microwave circuit and system level designs.

Index Terms— Graphene channel field effect transistor,equivalent circuit model, RF, microwave.

I. INTRODUCTION

PRESENTLY, wireless electronics are trending towardsfaster speed, smaller size, smarter function, and lower

cost [1], [2]. To achieve these goals, the requirements fornew materials with enhanced electrical properties and a highdegree of compatibility with standard processes has becomeparamount [3]. As an emerging two-dimensional (2-D) mate-rial, graphene has been proven to have superior materialproperties that perfectly match the needs of future wirelesselectronics [4]. Due to the special energy band structure

Manuscript received July 11, 2017; revised October 5, 2017 andDecember 17, 2017; accepted January 3, 2018. Date of publicationFebruary 12, 2018; date of current version July 3, 2018. This workwas supported by the National Natural Science Foundation of Chinaunder Grant 61401143. This paper was recommended by Associate EditorP. Maffezzoni. (Corresponding author: Lei Sang.)

L. Sang, Y. Xu, and R. Chen are with the Academy of OptoelectronicTechnology, Hefei University of Technology, Hefei 230009, China (e-mail:[email protected]).

Y. Wu is with the Science and Technology on Monolithic IntegratedCircuits and Modules Laboratory, Nanjing Electronic Device Institute,Nanjing 210016, China.

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCSI.2018.2793852

of graphene, the intrinsic carrier mobility was found to bebeyond 20000 cm2/V · s at room temperature [5], which ismuch larger than that of an electron (∼1400cm2/V · s) insilicon [6]. The saturation velocity of an electron is tested tobe as high as 6 × 107cm/s, which is ∼6× larger than that of anelectron in silicon [7]. As a result of these promising electricalmaterial properties, graphene field effect transistors (GFETs)have been developed rapidly in recent years, and successfullyimplemented in practical applications such as a frequency dou-bler [8], [9], voltage-tunable terahertz (THz) modulator [10],broadband millimeter wave absorber [11], and sub-harmonicfrequency mixer [12].

For the fabrication of GFETs, the general transfer approachrelies on polymethyl methacrylate (PMMA) as a supportinglayer. The graphene surface is first coated with PMMA, andthe metal catalyst is then etched using the appropriate etchant.Then, the graphene, supported by polymer, is transferred ontoa desired substrate, and the supporting layer is finally dissolvedwith acetone. However, the cleaning process is inadequate forcompletely removing the organic residue, as strong chemicaladsorption occurs between graphene and the organic com-pound PMMA. Exposing the graphene to the organic com-pound in this transfer and the following lithography processleaves behind contaminants on the graphene surface. Severalefforts, such as searching for a substitution in the transferprocess or annealing in special ambience have been done inattempt to remove the residue. However, these special methodsare not suitable for the fabrication of GFETs, a process whichrequires many consecutive lithography steps. All of the issuesabove limit the performance of GFETs, most significantly atmicrowave frequency.

Regarding modeling, an essential step in transistor design,precisely modeling the electrical performance of GFETs iscritical to improving the yield of GFETs-based RF andmicrowave integrated circuit design, and to reduce the cir-cuit development timeline [13], [14]. Fundamental-level anddevice-level physical models for GFETs have been proposedin [15] and [16]. Those proposed models are based onprevailing theories, including fundamental graphene chargecarrier transport and steady-state velocity-field characteristicsto describe carrier transport. However, these physical modelseither lack precision or are too complicated to be used forthe design of GFETs circuits due to their incompatibility withcommercial RF and microwave circuit simulators. Compared

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2560 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 65, NO. 8, AUGUST 2018

to physical modeling, the circuit-level modeling based on theequivalent circuit has many advantages, such as simplicity,high precision, and convenient implementation. Based onmeasured data, the equivalent circuit model can be built tosimulate the I -V and C-V characteristics of the GFETs, whichinvolves derived explicit closed-form equations to model thedrain current. However, only a few GFET circuit-level modelshave been built for applications in RF and microwave circuitdesign [7], [18].

A semi-empirical modeling approach for GFETs with gap-less large-area graphene channels has been presented in [19].The modeling approach is capable of doing the calculationsof I -V characteristics, small signal behaviors, and cut-offfrequency of GFETs. Another equivalent circuit model forGFETs, presented in [20] and [21], gave a qualitative explana-tion of GFETs operating in am-bipolar status. However, thosecircuit-level models are almost derived from conventionalmetal–oxide–semiconductor (MOS) FET models [22], whichinherit three major disadvantages in the design of practicalcircuits. First, the empirical square-root charge-voltage rela-tionship is incapable of distinguishing between electron andhole carrier status. Second, those models are validated withexperimental data only from long-channel GFETs workingat GHz frequency band. The capability of modeling mm-waveelectronics is still waiting for verification. Moreover, modelingof the characteristics of monolayer graphene, including highelectron mobility, 2-D conducting layer, and excellent thermalconductivity are not included in traditional MOSFET or GaNHEMT models.

In this paper, an improved double gate monolayer shortchannel GFET with a gate length of 150 nm was designedand fabricated by self-aligned gate processing, enabled byoptimized organic, contamination free graphene transfer. Thefabrication of the GFETs was improved to avoid the adverseeffects of organic residue on the Ohmic contact and thegrowth of the gate dielectric. Therefore, fabricated GFETs aredemonstrated working at frequency from Direct Current (DC)frequency up to 40 GHz. Then, combining the advantages ofMOSFET models and HEMT models, we present a completeequivalent circuit model for the GFETs, which solves thestated issues of previous circuit-level modeling, and expandsthe model frequency range to mm-wave band [23], [24]. Themodel implemented further in advanced design system (ADS)paves the way to do design GFETs-based microwave circuits.Parameter variation analyses of GFETs is therefore easilyachieved in ADS, enabling the designers to quickly quantifythe negative effects of non-idealities and parasitics such ascontact resistance, parasitic capacitance, and impurities.

II. GFETs SAMPLE & MODELING METHODOLOGY

Double gate GFET samples with gate length of 150 nmwere designed, fabricated and tested for the purpose of mod-eling and validation. The structure of the dual-gate graphenetransistor (Wch = 12 μm and Lch = 150nm) is presentedin Figure 1. The fabrication of the GFETs was performedon the CVD grown monolayer graphene on 300nm SiO2.To transfer graphene from the Cu substrate, an Au film wasused as the sacrificial transfer layer instead of polymers.

Fig. 1. (a) Structure parameters of the GFETs. (b) Optical image of theGFET samples.(c) SEM image of the graphene channel.

The Au film formed an Ohmic contact with the graphenetransistors, which also enabled a self-aligned gate process thatminimizes the ungated graphene region. The new processeskeep the CVD graphene free from organic contaminationsnot only during the transfer, but also in the later lithography.In order to reduce the gate resistance, trilayer-photoresist forT-gates was patterned on the gold film in the channel regionsusing e-beam lithography. A 200 nm high-resistivity Si sub-strate served as a buffer layer. The source/drain electrodes andthe top gate electrode were realized through standard lift-offprocess of Ti/Au (20nm/200nm) and Ti/Au (30nm/300nm)metal layers respectively. A 6 nm Al2O3 layer, which actedas the gate oxide, was deposited using an Atomic LayerDeposition (ALD) technique (fabrication processing detail canbe found in the Appendix).

GFET samples are tested under bias voltages of Vgs and Vds

from −1.5 V to 1.5 V with a step size of 0.1 V. Due to the zero

SANG et al.: DEVICE AND COMPACT CIRCUIT-LEVEL MODELING OF GFET FOR RF AND MICROWAVE APPLICATIONS 2561

Fig. 2. (a) Carriers in the channel are holes when Vgs has a small value.(b) When Vgs increases gradually, the absolute value of Vgs becomes smaller,and GFETs goes into ambipolar transport operation mode. (c) Carriers in thechannel are electrons when Vgs has a relatively large value. (d) Equivalentcircuit of the channel.

bandgap of monolayer graphene, GFETs works differentlyfrom that of traditional FETs. In general, the conductingcharacteristic of GFETs has three different modes as shownin Figure 2(a) to 2(c).

When applying a positive voltage to the gate, the verticalelectric field will charge the graphene channel with elec-trons. The electron charge density induced by the top gatecan be approximately calculated by the included empiricalequation (1). The factors that affect electron concentration areanalogous to those of Si-MOSFETs [25].

QV E S,e = CGn∅t ln

(1 + exp

V �GS − Vt,e

n∅t

)(1)

As shown in equation (1), CG is the top-gate capacitance perunit area and n is the sub-threshold coefficient. VGS and Vt,e

describe the top-gate-to-source voltage of the intrinsic part ofthe device and the effective threshold voltage of a gate-inducedelectron charge in the channel, respectively. ϕt represents thethermodynamic equivalent voltage. As shown in Figure 2(a),when applying a very small positive voltage to the gate witha value nearly equal to the threshold voltage, the electricfield intensity will be not large enough to eliminate the holescompletely. If the voltage becomes smaller, the holes willobtain sufficient energy to jump from the bound state ofacceptor into the valence band becoming conductive holes.Without gate voltage applied, the graphene channel acts as agood conductor. The channel and the gate form a structuresimilar to a parallel plate capacitor [26].

The operation region of the GFETs channel is controlledby the gate voltage and the type of majority carriers whichcan be either electrons or holes, or even the electrons andholes existing at the same as shown in Figure 2(b) [27].The transfer characteristic curve of the graphene transistoralways shows a V-shape in Figure 3(a) and 3(b). Draincurrent reaches the minimum value when Vgs is at the Diracpoint [15]. GFETs, in this case, changes their working statusfrom the active amplify state to the passive state with the

Fig. 3. Tested performance of GFETS sample. (a) Characteristic of draincurrent versus Vgs. (b) Characteristic of transconductance versus Vgs.

Fig. 4. Circuit-level modeling methodology and process for GFETs.

corresponding transconductance becoming zero. Theoretically,the Dirac point in pure graphene is located at a bias voltageof zero. However, it is easy for graphene to absorb smallmolecules and ions in the surrounding environment, whichresults in the shift of the Dirac point.

The proposed complete GFETs modeling process is illus-trated in Figure 4. First, I-V curves and S-parameters of GFETs


Fig. 5. The topology of the linear equivalent circuit model of the GFETs.

are tested using a semiconductor analyzer under narrow pulsecondition and a vector network analyzer, respectively. Then,the value of the circuit elements in the linear model can beobtained based on the measured S-parameters. The equiva-lent circuit model consists of two part: parasitic elementsand intrinsic elements. The parasitic elements do not changerelative to the bias condition. However, the value of intrinsicelements will change relative to the alteration of bias voltages.Suitable equations and curves are then presented to describevariation of intrinsic elements. In terms of functionality, thelinear model is the basic step while the nonlinear model isthe updated version. The linear equivalent circuit describesthe small signal performance under a fixed bias condition. Thenonlinear model represents the intrinsic effect under changingvoltages. Finally, the complete model is constructed by thelinear and nonlinear equivalent circuits. The complete model isbased on analytical formulas and parasitic equivalent elements.It reflects the large signal microwave characteristics withexternal current-voltage relationship.

III. LINEAR EQUIVALENT CIRCUIT MODEL

Based on the structural and electrical properties, the linearequivalent circuit model involving thirteen elements with con-stant values is shown in Figure 5. Considering the varyingworking status of the equivalent lumped elements, the equiv-alent circuit of GFETs is constructed by the parasitic and theintrinsic parts. The intrinsic effects are described by elementsin the shadow area. The circuit elements outside the shadowarea are used to model the parasitic effects. Compared totraditional FETs (like MOSFETs or HEMTs), the numberof circuit element of the GFETs is reduced. The majorparasitic effects are introduced by the three electrodes, whichare independent of the bias voltages. The intrinsic part ofthe GFETs is similar as that of HEMTs, which also has a2-D electron gas (2-DEG) channel.

In the linear equivalent circuit, elements Lg , Ls , and Ld

describe the inductive effects of the gate, source and drain elec-trodes, respectively. Rg , Rs , and Rd are the gate, source anddrain resistances, including the contact and access resistances.

TABLE I

THE VALUE OF EQUIVALENT CIRCUIT ELEMENTS(Vgs = −0.3 V AND 0.8V, Vds = 0.3 V)

The capacitive effect between the two electrodes is repre-sented by Cpg and Cpd . These eight equivalent elements areindependent of the bias voltage. Different from the parasiticelements, the intrinsic equivalent elements (marked in blue)represent the microwave performance of the graphene channel.The value of most intrinsic elements varies with different biasvoltages. Cgs represents the capacitive effect between the gateand source electrodes. Cgd represents the capacitive effectbetween the gate and drain electrodes. The capacitive effectbetween drain and source electrodes is represented by Cds .The relationship among the equivalent capacitances can bedescribed roughly by the following equations [28]:

Cch = Cgs + Cgd (2)

Cch = q2 2

π

q |Vs |(hv f )2 (3)

where q is the elementary charge, Vs is the potential betweenthe channel and the source electrode, h̄ is the Planck’s con-stant, ν f is the Fermi velocity. In the intrinsic part, gmVgs

is a voltage-controlled current source. The transconductancegm is defined as the source-drain current derivative of thegate voltage. It is similar to the drain conductance gds , andshows the change of drain-source current with the drainvoltage under fixed gate voltage. The initial value of theequivalent elements can be roughly calculated according to thestructure and material property of the GFETs. Then, the valuecan be precisely calculated with the help of an optimizedalgorithm using S-parameters as the optimization target [29],[30]. Different algorithms will lead to different convergencerates, but the final extracted values are almost the same [31].The extracted values of the equivalent elements are listedin Table 1. The parameter τ represents a delay in the timedomain, which will not affect the simulated result in frequencydomain. The values of parasitic elements changes in frequencyare shown in Figure 6(a) and (b). As the diagrams indicate,the parasitic elements are basically unchanged.

It can be seen from the diagrams Figure 3(a) that thechannel does not turn off completely due to the semi-metallic nature of graphene. The carrier type can be an


Fig. 6. (a) Equivalent value of the parasitic resistances vs frequency.(b) Equivalent value of the parasitic inductances and capacitances vsfrequency.

electron or hole, which would form a p-n junction to intro-duce a contact resistance to the device when the carriertype is opposite to the charge type in the metal-graphenecontact. Different electrode materials have different contractresistances [31]. Parasitic resistances (Rd , Rg , Rs) of theGFETs are much higher than that of ordinary FETs. It isreported that the contact resistance of GFETs is ∼10× largerthan that of silicon MOSFETs and HEMTs [33]. The largecontact resistance reduces the transconductance and the cur-rent characteristics of the GFETs, therefore affecting theRF characteristics. This phenomenon is also reflected wellin our equivalent circuit and the corresponding extractedvalues.

The calculated data by the linear model and the tested dataare compared from 0.2 GHz to 40 GHz under different biasconditions as shown in Figure 7 and Figure 8.

The mean difference calculated by equation (4) is used toevaluate the accuracy of the linear equivalent circuit model.The calculated errors of the amplitude are 1.6%, 3.5%, 2.2%,1.8% of S11, S12, S21, and S22 (in decibel), respectively. Theerrors of the phases are 1.1°, 3.7°, 3.2°, 1.7° of S11, S12,S21, and S22 (in decimal), respectively. It can be seen that thelinear equivalent circuit model has excellent accuracy in theprediction of the S-parameters, which paves a reliable basisfor establishing the nonlinear model.

σi j (s) = 1

N

N∑i=1

∣∣∣smi j − ss

i j

∣∣∣∣∣∣ssi j

∣∣∣ (4)

Fig. 7. Comparison between simulated (blue line) and measured (red dot)S-parameters (Vgs = −0.3V, Vds = 0.3V).

Fig. 8. Comparison between simulated (blue line) and measured (red dot)S-parameters (Vgs = 0.8V, Vds = 0.3V).

IV. NONLINEAR MODEL AND CHARACTERISTICS

PREDICTION OF THE GFETs

Although the linear equivalent circuit model is very usefulfor the understanding of the structural characteristics and to


Fig. 9. The complete circuit model of GFETs including nonlinear effectsbuilt based on the linear circuit model. (All the formulas are integrated in thesymbolically defined devices (SDD) calculating module in Advanced DesignSystem (ADS)).

predict S-parameters, it only works under a fixed bias voltage.Based on the linear model, the nonlinear model, also calledlarge signal model, for the GFETs needs to be established forthe simulation of RF and microwave performance as shown inFig. 9. In the large signal model, the total external current-voltage relationship is in variation. The parasitic elementsremain unchanged, and their values are inherited from thelinear equivalent model. The main intrinsic elements arecalculated by the formulas (from 5 to 16). Vgs and Vds areboth the variables. According to the simulated results of thelinear equivalent model, the intrinsic part are mainly composedof I-V model and nonlinear capacitors such as Cgs and Cgd .

Several empirical nonlinear models for III-V FETs havebeen proposed such as Curtice, Angelov, and Materka mod-els etc. [35]. Because the GFETs have some similarities asMOSFETs and HEMTs, the nonlinear formulas of the GFETsis built based on Angelov model. Considering the propertiesof the monolayer graphene channel, the structural complexity,and the accuracy of the nonlinear formulas, the followingmodifications are made to better describe the unique propertiesof GFETs with or without channel current saturation regime.

(1). The exponential relationship between Ids and Vds

is removed in original Angelov model, then forming theequation (5) and (6).

(2). The hyperbolic and exponential relationships betweenthe threshold voltage Vi and the knee voltage Vpko areremoved, but their linear relationship is kept.

(3). The nonlinear model of Cgd uses hyperbolic functioninstead of exponential function.

(4). The cubic modulation in the index terms ofequation (15) and (16) is changed to the linear modulation.

Ids = Idsk × f(Vds · Vgs

)(5)

f (Vds · Vgs) = (1 + tanh(ϕ)) tanh(αVds) (6)

ϕ = P1(Vgs − Vi ) + P2(Vgs − Vi )2

+ P3(Vgs − Vi )3 (7)

Vi = Vpk0 + δs · Vds (8)

where Idsk is the drain current when the transconduc-tance reaches its maximum value. α is the saturation

Fig. 10. The comparison of Ids -Vds between the calculated data and themeasured data.

TABLE II

THE EXTRACTED VALUE OF THE I-V MODEL PARAMETERS

TABLE III

THE EXTRACTED VALUE OF THE NONLINEARCAPACITANCE MODEL PARAMETERS

voltage parameter. ϕ can be expressed by a sum of thepower function in (7). P1, P2, P3 are the fitting parameters.Vpk0 is the drain voltage when the transconductance reachesits maximum value. The relationship between the Vpk0 andthe drain-source voltage is given in equation (8).

The comparison between the calculated data and the mea-sured data for the 150nm channel length GFETs is shownin Figure 10. The red dotted line is the measured data and thesolid line is the calculated data. The final extracted parametersare listed in table 2 and table 3. It can be seen from thecomparison that the GFETs nonlinear model has excellentaccuracy for the I-V predications.

Other than the I -V model, the nonlinear equivalent modelcontains three nonlinear capacitors, Cds , Cgs and Cgd . Amongthe three capacitors, the Cds is almost unchanged during thevariation of the bias conditions, so it can be set as a fixed valuein model. According to the structural and electrical propertiesof the GFETs, the nonlinear capacitor models are representedby the following equations:

Cds =∑

Cdsn(Vgef f − Vgs0)n (9)

Vgef f = 1

2[Vgs + Vgd +

√(Vgs − Vgd)2 + δ2] (10)

Cgs = Cgs0(1 + tanh(φ1))(1 + tanh(φ2)) (11)


Fig. 11. The comparison of Ids -Vds between the calculated data and themeasured data.

φ1 = F1Vgs + F11V 2gs + F111V 3

gs (12)

φ2 = F2Vds + F22V 2ds + F222V 3

ds (13)

Cgd = Cgd0(1 + exp(φ3)) · exp(φ4) (14)

φ3 = A · Vgs · Vds + B (15)

φ4 = C · Vds (16)

where Cdsn, Cgs0, and Cgd0 are the initial values of the model.Vgs and Vds are the bias voltages. The other parameters arefitting parameters. Compared to traditional FETs, the channelof GFETs cannot be turned-off completely, and the biasvoltage is very small, so the nonlinear effect doesn’t dominatethe performance. In equation (9), n represent the change typeof the Cds , and it is set to one in this paper. The extractedvalue of the equation parameters is listed in Table 3. Thecalculated data based on the nonlinear capacitance models andthe data extracted from measured S-parameters are comparedin Figure 11.

The nonlinear element equations combined with the para-sitic elements from linear equivalent circuit model finally formthe complete nonlinear model. The microwave performanceis simulated based on the nonlinear model in a practicalfrequency band. The simulated data and the measured dataare compared in Figure 12.

Regarding comparisons between measured data and simu-lated data, although the GFETs have a very high maximumoscillation frequency ( fmax ), the characteristic frequency ( ft )is much lower than the fmax due to parasitic effects. As shownin the equivalent circuit, the higher contact resistance leads

Fig. 12. The comparisons of current gain and reflection coefficient betweensimulated data and measured data.

to the smaller ratio of the current switch. Some of theGFETs with fmax of 350GHz have operating frequencies upto 10.5GHz due to the parasitic effects.

Once the equivalent circuit model is established, modelparameters be optimized again to fit the performance ofdevices with different gate size and channel material (moreexamples are shown in the Appendix). The proposed modelcan be easily embedded into the widely used commercial cir-cuit and system simulator “Advanced Design System (ADS)”.Shown in the Appendix, the GFET model is implementedin ADS by using the symbolically defined device (SDD)module and the surrounding lumped elements based on theproposed equivalent circuit topology and empirical formulas.The value of all the lumped elements are calculated based onthe proposed linear model, and the nonlinear I -V relationshipis represented by the SDD module which is an equation-basedmulti-port component defined by specifying equations thatrelate port currents and port voltage. Current flow in and outthose ports and inner C-V relationship are calculated by theproposed nonlinear empirical equations. Examples includingone circuit level design of using the GFET in a switchamplifier and one system level design of using the GFETmodel in a 16 QAM communication system are given inthe Appendix.

V. CONCLUSION

A complete equivalent circuit model containing linear andnonlinear models for GFETs is proposed in this paper based


Fig. 13. The photo images of GFETs with different gate length and width.(a) GFETs with fixed 200 nm gate length but four different gate width.(b) GFETs with fixed 150 nm gate length but four different gate width.

Fig. 14. The comparison between the tested data and the simulated dataof the GFET with 200nm gate length and 12 μm gate width by using thelinear equivalent model. (a) Comparison of the amplitude of S-parameters,(b) Comparison of the phase of the S-parameters.

on the tested data of the GFETs fabricated with an improvedgraphene transferring processing. The complete model is val-idated by comparing the simulated data with the measureddata. From the comparison, the model is capable of describingthe I -V and RF performance of the GFETs precisely up tothe mm-wave band. By analyzing each circuit element, the

Fig. 15. The comparison between the tested data and the simulated dataof the GFET with 200 nm gate length and 12 μm gate width by using thecomplete equivalent model. (a) Comparison of the I -V curve, (b) Comparisonof the reflection coefficient.

drawbacks of the GFETs structural design can be found explic-itly, and improvements can therefore be proposed accordingly.In addition, the complete model can be embedded convenientlyin a commercial simulator such as Advanced Design Systemto do microwave circuit level simulation.

APPENDIX

A. Fabrication Detail of GFETThe manufacturing process is described as below: a 30 nm

Au film was deposited first on the surface of as-grown CVDgraphene on Cu substrates as the supporting layer, so as toform pristine Au-graphene contact after the transfer process.Importantly, the cleanup of the supporting layer is omissibleas Au and graphene can form good Ohmic contact as thesource (and drain) of the GFETs in the latter self-alignedprocess, and the covered Au film can prevent graphene fromphotoresist and other organic contamination during the entirefabrication process. After the transfer process, standard litho-graphical methods are used to define the regions of the GFETs.Gold film outside the channel is wet etched away by an aque-ous KI : I2 solution, and the graphene film outside the channelis removed by oxygen plasma etching. The gold film under theT-gates is wet etched away by an aqueous KI: I2 solution. Theunetched gold film outside the T-gates forms the self-alignedsource and drain Ohmic contacts automatically. In particular,the proper etching time depends on the thickness of Au film,and can be designed to control lateral-etching in the solution-etching process, which can ensure isolation between the source(drain) and the gate electrode with a tiny space. Then, 1 nmAl is deposited onto the sample and exposed to air for 10 h


Fig. 16. The comparison between the tested data and the simulated dataof GFET with 150 nm gate length and 16 μm gate width by using linearequivalent model. (a) Comparison of the amplitude of the S-parameters.(b) Comparison of the phase of the S-parameters.

to form a self-oxidized Al2O3 buffer layer. After that, 8 nmthick Al2O3 film is deposited by ALD as the gate dielectricand 30 nm Ti/300 nm Au is deposited by e-beam evaporationas the top-gated electrodes. The device fabrication is completefollowing lift-off. With this method, the graphene in thechannel is kept away from the organic solution directly duringthe device fabrication, which is verified as being beneficial tothe performance improvement of our GFETs. Atomic forcemicroscope (AFM) is employed to check the surface of thesample for transferred PMMA. The sample has been dipped inacetone for 16 h to dissolve PMMA; however, contaminationis still observed in the surface of graphene, compared to theclean surface of a Si/SiO2 substrate. The similar problem willappear in lithography processes, and the Ohmic contact andthe growth of gate dielectrics will be seriously affected bythis organic residue. It is obvious that the graphene from Autransferred will not be troubled by this issue.

B. Modeled GFETs With Different Gate Dimension

To demonstrate the scalability of our model, more devicesare modeled below based on the same proposed equivalentcircuit model. Shown in Figure 13(a) and 13(b), we fabricateda series of GFETs with different gate length and width. Dueto the need of good electrical performance and scalabilityfor modeling purpose, the GFETs with 150 nm gate lengthand 12 μm gate width is chosen as the proprietary modelto validate the proposed modeling method. For GFETs withother geometry (gate length and gate width), models can be

Fig. 17. The comparison between the tested data and the simulated data ofGFET with 150 nm gate length and 16 μm gate width by using the completeequivalent circuit model. (a) Comparison of the I -V curve. (b) Comparisonof the reflection coefficient.

TABLE IV

THE EXTRACTED VALUE OF THE I-V MODEL PARAMETERS

OF DIFFERENT GFET DEVICES

easily obtained from the proprietary model. Taking anothertwo GFETs as examples, the first one maintains the same gatewidth but has 200 nm gate length, the other one maintainsthe same gate length but has 16 μm gate width. Based on theproprietary model of the 150 nm by 12 μm device, the modelparameters of the other two GFETs are derived and listedin Table 4 and Table 5. Figure 14 to Figure 17 show thesimulated results match with the tested data of the other twoGFETs excellently by using the derived model parameters.

C. Using GFET Model for Circuit and System Level Designs

To show how our proposed GFET model can be practicallyused in circuit and system design, we add one circuit level


Fig. 18. Example of implementing GFET model in ADS for the design ofswitch amplifier. (a) GFET device model in ADS built based on proposedmethod in the manuscript. (b) Schematic view of the switch amplifier circuittopology designed based on the proposed GFET model.

TABLE V

THE EXTRACTED VALUE OF THE EQUIVALENTELEMENTS OF DIFFERENT GFET DEVICES

example of using the GFET in a switch amplifier and onesystem level example of using the GFET model in a 16 QAMcommunication system below and in the main text. One should

Fig. 19. Simulated performance of GFET based switch amplifier. (a) Turn-onstatus gain in frequency domain. (b) Turn-off status isolation between inputand output signal in frequency domain. (c) Output voltage signal in timedomain of both turn-on and turn-off status.

notice that the use of GFET in circuits currently only focuson its linear regime such as the work from MIT [1], [2] andIBM [6] groups due to no saturation regime of GFET exceptvery a few examples [4].

Our proposed model can be easily embedded into the widelyused commercial circuit and system simulator “AdvancedDesign System (ADS)” as shown in Figure 18. Figure 18(a)shows the implemented GFET model in ADS by using thesymbolically defined device (SDD) and surrounding lumpedelements based on the proposed equivalent circuit topologyand empirical formulas. The value of all the lumped elementsare calculated based on the proposed linear model, and the


Fig. 20. Example of using GFET model in the simulation of a 16QAM mobilecommunication system. (a) System topology based on GFET. (b) Simulationresults.

nonlinear I-V relationship is represented by the SDD tool inthe black box. The SDD tool is an equation-based multi-portcomponent defined by specifying equations that relate portcurrents and port voltage. In our case, Vd , Vg and Vs aredefined to be the voltage on port 2, 1 and 4, respectively.Current flow in and out those ports and inner C-V relationshipare calculated by the proposed nonlinear empirical equationsshown in the figure inset.

Figure 18(b) is the schematic view of the switch amplifiertopology based on the GFET model. Note that the gatewidth W , number of gate fingers N and gate length L aretunable, which shows the scalability of the proposed GFETmodel. As shown in Figure 19, the electrical performance canbe easily simulated in both frequency and time domainswiththe gate width of 12 μm or 16 μm.

The GFET model could be also used as an element forthe simulation of a 16 QAM mobile communication systemin ADS. The system schematic view associate with simulatedperformance is shown in figure 20.

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Lei Sang received the Ph.D. degree in electricalengineering from the University of Electronic Sci-ence and Technology of China in 2013. He wasa Visiting Scholar with University of Illinois atUrbana-Champaign from 2011 to 2012. He is cur-rently an Associate Professor with the Hefei Univer-sity of Technology. He has been involved in flexibleelectronic device and model.

Yulong Xu received the bachelor’s degree in electri-cal engineering from the Hefei University of Tech-nology, where he is currently pursuing the master’sdegree. His research interest is microwave amplifier.

Yun Wu received the Ph.D. degree from WuhanUniversity in 2012. He is currently a Senior Engineerwith the Nanjing Electronic Device Institute, China.He has been involved in the technology of grapheneand other 2-D electronic device.

Rongmin Chen received the B.S. degree in instru-ment and meter engineering from the Hefei Univer-sity of Technology in 2017.

device and compact circuit-level modeling of graphene...

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