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DEPARTMENT OF ECE M.TECH VLSI DESIGN Page 1

DESIGN FOR TEST IN ENCOUNTER RTL COMPILER

TCL SCRIPT FILE FOR RTL COMPILER :

######################################################

# Script for Cadence RTL Compiler synthesis

# Sri. G.V.K.Sharma, M.Tech Associate Professor# Use with syn-rtl -f

########################################################

# Set the search paths to the libraries and the HDL files

# Remember that "." means your current directory

set_attribute hdl_search_path {./} ;# Search path for Verilog files

set_attribute lib_search_path {/usr/software/cadence/cdks/gsclib090_v3.3/timing} ;# Search path for library files

set_attribute library [list typical.lib] ;# Target Library

set_attribute information_level 6 ;# See a lot of warnings.

set myFiles [list accu.v] ;# All your HDL files

set basename accu ;# name of top level module

set myClk clk ;# clock name

set myPeriod_ps 10000 ;# Clock period in ps

set myInDelay_ps 250 ;# delay from clock to inputs valid

set myOutDelay_ps 250 ;# delay from clock to output valid

set runname RTL ;# name appended to output files

set DESIGN "accu"

#*********************************************************

#* below here shouldn't need to be changed... *

#*********************************************************

# Analyze and Elaborate the HDL files

read_hdl ${myFiles}

elaborate ${basename}

# Apply Constraints and generate clocks

set clock [define_clock -period ${myPeriod_ps} -name ${myClk} [clock_ports]]


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external_delay -input $myInDelay_ps -clock ${myClk} [find / -port ports_in/*]

external_delay -output $myOutDelay_ps -clock ${myClk} [find / -port ports_out/*]

#INSERT DESIGN FOR TEST COMMANDS HERE

set_attribute dft_scan_style muxed_scan / ;#( Selectig the scan style for the design it can be a muxed scanstyle orclocked lssd scan)

define_dft shift_enable -name SE -active high -create_port SE ;# (For muxed scan style, specify the pin or portwhich drives the shift_enable pin of the scan flip-flops)

define_dft test_mode -design ${DESIGN} -name TM -active high TM create ;# ( Defining the test mode forthe signals which are already coded in the RTL, or test mode will be used to enable the fixing of DFT violations, or testmode is used to configure the data direction control for a bidirectional or tri-state pad)

report dft_setup ;# (Report the status of design for test setup )

synthesize -to_generic ;# (Perform an RTL optimization to create a generic netlist to remove all the dont care cells thisshould be done in order so that the dft rule checker might not be able to check through dont care cells and would result in

extra dft violations)

check_dft_rules ;#( this command is for Identify all uncontrollable clocks, and any asynchronous set and resetpins that cannot be held to their inactive value during test mode )

report dft_registers ;# (Report the scannable status of the flip-flops in the design)

set_attribute dft_scan_output_preference auto /designs/$DESIGN ;#( Specify the scan flip-flop output pin to usefor the scan data path connection)

set_attr dft_scan_map_mode tdrc_pass /designs /$DESIGN ;#( This command is used to control the mapping offlip-flops to scan flip-flops)

check_dft_rules > dft_rules.report2 ;#(write in to an out put file the status of design rule violations)

synthesize -incremental -effort high ;#(It converts any all the non scannable flops to scannable flops with fixing oftiming violations)

define_dft scan_chain -name chain1 -create_ports -sdi tdi -sdo tdo ;#( Creates a scan chain or analyzes anexisting chain with the specified input and output scan data ports)

set_attribute dft_identify_internal_test_ clocks true ;#( the tool creates automatically separate test clocks in thesame test-clock domain if the design has a clock path that contains multiple input combinational gates inorder to avoidintroducing hold time violations in the scan path due to clock skew)

set_attr dft_min_number_of_scan_chains 2 /designs/ $DESIGN ;#( Specify the minimum number of scan chains tobe created)

set_attr dft_mix_clock_edges_in_scan_chains true /designs/ $DESIGN ;#( Specify whether to allow mixing ofrising and falling edge-triggered scan flip-flops from the same test-clock domain in the same scan chain)

report dft_setup ;#(report the present (up to now) status of design for test)

connect_scan_chains -auto_create_chains -preview ;#( preview the scan connection)


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connect_scan_chains -auto_create_chains :#( The -auto_create_chains option allows the tool to add new chains thatare not user-defined)

report dft_setup ;#(report the present (up to now) status of design for test)

# Sets transition to default values for Synopsys SDC format,

# fall/rise 400ps

dc::set_clock_transition .4 $myClk

# check that the design is OK so far

check_design -unresolved

report timinglint

# Synthesize the design to the target library

synthesize -to_mapped

# Write out the reports

report timing > ${basename}_${runname}_timing.rep

report gates > ${basename}_${runname}_cell.rep

report power > ${basename}_${runname}_power.rep

# Write out the structural Verilog and sdc files

write_hdl -mapped > ${basename}_${runname}.v

write_sdc > ${basename}_${runname}.sdc

#write out the reports of dft for ATPG tools

write_atpg -cadence > accu_RTL.atpg ;#(Pin assignment file)

write_atpg -stil > accu.stil.atpg ;#(information about timing ,signals and signal groups)

report dft_chains > accu_dft.report ;#(description of scan chains created)

quit

ENCOUNTER TEST FLOW:

1) To bring up the encounter test interface use the command etgui & or et &2) To bring up the encounter test environment in command line mode use etfc3) To bring up in the TCL environment use the command et tcl

FLOW DESCRIBED IN GUI MODE:

click on new project nameaccudesignfortest click OK #(this setup registers this project and lets youbring up this design from any directory )

select Verification Build ModelsModel (a window will popup) #(iputs to build model are netlist file andtecnolgy )

o select files/Directories accu_RTL.v #(this is the mapped netlist file containing the scan chains)o select Setup and chose the technical library typical.v


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/usr/software/cadence/cdks/gsclib090_v3.3/vlogo update projecto clickoko select Run

select on Tasks Tab #(tasks tab is the history ) Select Verification Build Models Test Mode (one window will popup)#(input will be pin definition file)

o Test Mode Name ---FULLSCAN #(this is a default mode for an ATPG SI to SO configuration)o Select input pin Assignment file ---accu_RTL.atpg click open #(this is the pin definition file generated

in encounter rtl compiler)o Select run

Select Verification Verify Test Structureso Select Test Mode Name ----FULLSCAN #(this checks for valid scan chains by tracing back from SO to

SI)o Select Run

Select Verification Build Models Fault Model (one window will popup) #(so to select a fault model toinclude different types of faults like ex dynamic faults)

o Select Fault Cell Boundary Onlyo Deselect Include Dynamic Faultso Select Run

Select ATPG Create Tests Specific Static Tests Scan Chain (one window will popup) #(the first tests youalways create are those that do simple shifting through the scan chains.This is mainly for manufacturing debugs)

o Select test mode name --- FULLSCANo create tests experiment name ---- SCAN_CHAIN_TESTo Click Run

Select ATPGCommit Tests (one window will popup) #(this process will apply the vectors generatedpermanently against the global fault)

o Select Test Mode Name ---- FULLSCANo Select Input Experiment Name ---- SCAN_CHAIN_TESTo Click Run

Select ATPG Create Tests Specific Static Tests logic (window popup) #(creation of standard STUCK-AT-FAULT model for ATPG patterns)

o Select Test Mode Name ---- FULLSCANo

create tests experiment name---SCAN_LOGIC_TESTo select Run Select ATPG Commit Tests (one window will popup) # this process will apply the vectors generated

permanently against the faults)

o Select Test Mode Name ----FULLSCANo Select Input Experiment Name ---- SCAN_LOGIC_TESTo Select Run

Select ATPGWrite Vectors (one window will popup)#(this step is usually for final manufacturing patterns,these patterns would be finally the vectors you have finalized and commited)

o Select Test Mode Name ----FULLSCANo Set output File Name---- final click Run


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Simulation of testpatterns generated using ncsim

goto the testresults directory in that one to verilog and do the following commands

mkdir worklib

gedit cds.lib (in the cds.lib file write down as DEFINE worklib ./newworklib)

gedit hdl.var(in the hdl.var write down as DEFINE WORK worklib )

ncvlog -mess typical.v accu_RTL.v final.mainsim.v

ncelab -mess -access +rwc -timescale 1ns/1ps dftlab1_FULLSCAN -delay_mode zero

ncsim dftlab1_FULLSCAN +simvision +TESTFILE2=fina l.1.verilog +TESTFILE3=final.2.verilog

then ucan see the goodcomapring vectors=58 and miscomparing vectors zero

INTRODUCING A STUCK AT FAULT IN GATE LEVEL NETLIST

Declare a net in the gate level net list accu_RTL.v as data type wor

Assign the net value =1b1

For example : wor n_17;

assign n_17=1'b1;

and save the file as accufault_RTL.v

then run the following commands

ncvlog -mess typical.v accufault_RTL.v final.mainsim.v

ncelab -mess -access +rwc -timescale 1ns/1ps dftlab1_FULLSCAN -delay_mode zero

ncsim dftlab1_FULLSCAN +simvision +TESTFILE2=fina l.1.verilog +TESTFILE3=final.2.verilog

then u can see total no of miscomparing vectors as 22

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