DICE LAB. PPT Template v3.0

Introduction to Digital System and Microprocessor Design

Lab Environment Setting

1/25

Youngtaek Oh, Inhwan Lee, Nameun Kang

DICE Lab. Creative IT Engineering

Mar 12, 2018

Step 1. Program Download

Download Xilinx ISE program and license file form course web site

You need more than 20GB to install Xilinx ISE

Please finish lab environment setting before 3/20.

Agree all statements and click the Next> button.

Step 2. Program Install

9/25

Choose ISE WebPACK within Products.

Step 2. Program Install

10/25

Downloaded license files are using for program activation after installation.

Click Load License and choose the file.

Step 2. Program Install

11/25

Step 3 . Fixing Project Navigator

Xilinx ISE 14.7 is not officially supported with Windows 10.

Xilinx ISE 14.7 will not open when you are running 64-bit mode.

You have to force ISE 14.7 always run in 32-bit mode.

If you use Windows 7, you can skip step 3.

Step 3 . Fixing Project Navigator

Open the following directory: C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64

Find and rename libPortability.dll to libPortability.dll.orig

Make a copy of libPortabilityNOSH.dll (copy and paste it to the same directory) and rename it libPortability.dll

Copy libPortabilityNOSH.dll again, but this time navigate to C:\Xilinx\14.7\ISE_DS\common\lib\nt64 and paste it there

In C:\Xilinx\14.7\ISE_DS\common\lib\nt64 Find and rename libPortability.dll to libPortability.dll.orig

Rename libPortabilityNOSH.dll to libPortability.dll

Step 3 . Fixing PlanAhead

Open C:\Xilinx\14.7\ISE_DS\PlanAhead\bin and rename rdiArgs.bat to rdiArgs.bat.orig

Download the attached zip file(planaheadfix.zip)

Extract it. You should now have a file named rdiArgs.bat

Copy the new rdiArgs.bat file to C:\Xilinx\14.7\ISE_DS\PlanAhead\bin

New Project give the project name Choose Schematic as Top-level source type.

Step 4. Simple Kit Test

12/25

Edit the Project Settings following spec sheet of the Kit.You can find specification from the manual or top surface of the chipset.

Step 4. Simple Kit Test

13/25

Add New Source in the project by right click in Hierarchy windowor Project-New Source menu.

Step 4. Simple Kit Test

14/25

Give the File name and click Next

Step 4. Simple Kit Test

15/25

Click the Finish than you can see schematic editor.

Step 4. Simple Kit Test

16/25

Add a logic using a and add terminals using b.

Step 4. Simple Kit Test

17/25

To make simulation, add New Source of Verilog Test Fixture and define the file name.

Step 4. Simple Kit Test

18/25

Choose the source as the schematic you built.

Step 3. Simple Kit Test

19/25

Add phrase in the source code as shown above and double click Simulate Behavioral Model.

Step 4. Simple Kit Test

20/25

You can see the result of your logic.

Step 4. Simple Kit Test

21/25

Click I/O Pin Planning (PlanAhead) Pre-Synthesis in Processes windowto arrange the I/O ports.

Step 4. Simple Kit Test

22/25

Arrange the Site as depicted above.

You can find the I/O address in the manual.

Step 4. Simple Kit Test

23/25

Double click Configure Target Device and click OK.

Step 4. Simple Kit Test

24/25

After connect the Kit double click the Boundary Scan.

Bypass the xcf08p and open bit file for xc3s100, then program.

Step 4. Simple Kit Test

25/25