DIFFERENTIAL AMPLIFIERS

DIFFERENTIAL AMPLIFIER

1. VERY HIGH INPUT IMPEDENCE

2. VERY HIGH BANDWIDTH

3. DIFFERENTIAL INPUT

4. DC DIFFERENTIAL INPUT ACCEPTED

5. HIGH COMMON MODE REJECTION

6. SIGNAL INTEGRITY AT THE OUTPUT

Let us start with a simple amplifier that can give us at the output a signal proportional to the difference between two signals, each with reference to a ground.

In a MOSFET under small signal conditions the output current is proportional to the signal voltage across the gate and source. As is obvious any signal applied to the source needs to be preferably applied through a buffer to reduce loading, while that at the gate could be applied directly.

It is evident from the circuit diagram that when we consider the output at transistor M2, vo2, we are looking at a cascade of CD amplifier followed by CG amplifier from vs1 to vo2 and CS amplifier from vs2 to v02. Similarly considering the output at transistor M1, vo1, we are looking at a cascade of CD amplifier followed by CG amplifier from vs2 to vo1 and CS amplifier from vs1 to v01. Assuming a total symmetrical circuit, it is sufficient to analyze the effect of any one signal input to analyze the total circuit. In analyzing the circuit we will use superposition theorem.

Let us now look at the equivalent circuit and its analysis. We represent the current source ISS by its output impedance 1/go in the equivalent circuit.

In the equivalent circuit

1s2gs1m1gs1mo1gs

L1gs1m1o

1s2gs1gs

vvgvgg1v

andRvgv

vvv

Solving for vo1/vs1 from the above three equations we get

o

1m

o

1m

L1m1s

2o

o

1m

o

1m

L1m1s

1o

g

g21

g

g

Rgv

vand

g

g21

g

g1

Rgv

v

Let us define the following:

222s

2o12

2s

1o

211s

2o11

1s

1o

Av

v;A

v

v

andAv

v;A

v

v

We can then write

2s221s212o

2s121s111o

vAvAv

andvAvAv

For a symmetric network A11 = A22 and A12 = A21.

We can now recast the equations as

2

RgAAAand

2

Rg

gg21

Rg

2AA

Awhere

2vv

AvvAv

2vv

AvvAv

Lo1211CM

L1m

om

L1m1211d

2s1sCM2s1sd2o

2s1sCM2s1sd1o

The signal (vs1 – vs2) is called the differential signal and the signal (vs1 + vs2) is called the Common Mode signal. This leads us to define a very important parameter defining a differential Amplifier, the Common Mode Rejection Ratio, CMRR. CMRR is defined as

o

1mo1m

CM

dg

g

2

gg21

A

ACMRR

Having evaluated the gains of differential and common mode gain an interesting fall out is what is popularly known as half circuit equivalent.

This has been reduced to two half circuits to evaluate differential and common mode gain. These are

Differential Common Mode

Half Circuit Half Circuit

2

RgAAAand

2

Rg

gg21

Rg

2AA

A

Lo1211CM

L1m

om

L1m1211d

The load Resistance used in a CMOS circuit could be each a PMOS transistor in saturation with a constant Gate to Source Voltage or Gate tied to Drain.

In both these cases the load resistance is the same for M1 and M2.

Let us now consider an non-symmetric load on M1 and M2 and look at the outputs vo1 and vo2. For this circuit we will have

om

om

3d

1m21

om

om

3d

1m22

om

om

3m

1m12

om

om

3m

1m11

gg21

gg

g

gA

gg21

gg1

g

gA

gg21

gg

g

gA

gg21

gg1

g

gA

This will give us the outputs vo1 and vo2 as

21222CM12111CM

21222d

12111d

2s1s2CM2s1s2d2o

2s1s1CM2s1s1d1o

AAA;AAAand2

AAA;

2

AAAwhere

2

vvAvvAv

2

vvAvvAv

Assuming that gm1 >> go, the values of Ad1, Ad2, ACM1 and ACM2 reduce to

3d

o2CM

3m

o1CM

3d

1m2d

3m

1m1d g2

gA;

g2

gA;

g2

gA;

g2

gA

Now since we are interested only in single ended output (say) vo2, we will device a useful method to use the other output to our advantage. What we would like to do is to connect the output vo1 to the gate of M4. We will then get the most commonly used single ended differential amplifier structure overleaf.

Solving for the circuit assuming gm1 , gm3 >> go, gd1, gd3 we obtain the differential and common mode gain as

1do

3m1m

3d1d3m

1doCM

3d1d

1md

gg

gg2CMRRusGiving

ggg2

ggAand

gg

gA

In our discussions so far we had considered NMOS input devices with PMOS load devices. It is equally likely that we may use PMOS input transistors and NMOS load transistors.

The relative advantages of the NMOS input differential Amplifier and PMOS input Differential Amplifier will be seen as we go down the course.

NMOS input pair:

M5

Common Mode Input Range

Lowest common mode input voltage at gate of M1(M2)v G1(min) = V SS + v GS3 + v SD1 - v SG1

for saturation, the minimum value of v SD1 = v SG1 - |V T1 |Therefore, v G1(min) = V SS + v GS3 - |V T1 |

v G1(max) = V DD - v SD5 - v SG1

|V|VI

VminVor 1TO3TOSS

SS1G

|V|I

VVmaxVor 1TOSS

5SDDD1G

Thermal Noise

21

11'P

33'N

21

111'P

2eq

LWK

LWK1

LWIK23

Tk16thv

To reduce thermal noise we choose

1

LWK

LWK

11'P

33'N

and large value of gm1.

Assume that V DD = 3V and that V SS = -3V. Using K’N = 2K’P 18 A/V2, 0.8V <VTO3 , VT1< 1.2V, find the common mode range for worst case conditions. Assume that ISS = 100A, W1/L1 = W2/L2 = 5, W3/L3 = W4/L4 = 1, and vSD5 = 0.2V.

V25.08.02.118

1003

|V|VI

VminV 1TO3TOSS

SS1G

V6.02.19x5

1002.03

|V|I

VVmaxV 1TOSS

5SDDD1G

The input common mode range is -0.25V to 0.6V.

Slew Rate:

This defines the rate at which the load capacitor charged. In other words it defines the rate dv/dt at the output. Slew rate is a measure of the output to follow the input signal. This is normally associated with large signal property. Under large signal, only one of M1 or M2 will be ON and the charging current will be I5. This gives a slew rate CL(VDD- VSS)/I5.

Parasitic elements in the Differential Amplifier:

CT = tail capacitor (common mode only)

CM = mirror capacitor = Cdg1 + Cdb1 + Cgs3 + Cgs4 + Cdb3

COUT = output capacitor » Cbd4 + Cbd2 + Cgd2 + CL

Noise Sources in Differential Amplifiers:

Noise can be normally modeled as a current source in parallel to iD. This current source represents two sources of noise, thermal noise and flicker noise. The mean square current noise source is defined as

tCoefficienNoisekerFlicKF

ggffrequencyatBandwidthfwhere

fLCf

I)KF(

3

1gTk8i

mmbs

2ox

Dm2n

The mean square noise reflected to the gate giving mean square voltage noise at the gate

f

WLKCf

)KF(

g3

1Tk8

g

iv

'oxm

2m

2n2

eq

The total output noise current, is obtained by summing each of the noise current contributions.

23eq2

1m

23m2

1eq2eq

24eq

23eq2

1m

23m2

2eq2

1eq2eq

2eq

21m

24eq

23m

23eq

23m

22eq

21m

21eq

21m

2to

v2g

gv2v

sTransistorPandNIdenticalgminAssu

vvg

gvvvwhere

vgvgvgvgvgi

The total 1/f and thermal noise contributions can be written as

'P,Nox

P,N

21

11'P

33'N

21

111'P

2eq

2

3

1

P'P

N'N

11

p2eq

KC2

KFBwhere

LWK

LWK1

LWIK23

Tk16thv

LL

BK

BK1

LWf

B2f/1v

2

3

1

P'P

N'N

11

p2eq L

L

BK

BK1

LWf

B2f/1v

To get the input noise for NMOS input stages interchange BP for BN, KN

’ for KP’ and vice versa.

Since BN = 5BP it is preferable to use PMOS input stage to reduce 1/f noise with large area for M1 and M2 and

1LL

BK

BK2

3

1

P'P

N'N

1/f Noise