differential design for high-speed applications by greg aldrich,...

Differential Design for High-Speed Applications

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Differential Design for High-Speed Applicationsby Greg Aldrich, Scott McMorrow, and Bernard Voss

Abstract

Designing Gigabit interconnect systems heavily rely on differential signaling methods. Willsignal integrity and timing constraints be satisfied on high-speed differential signals? Whatare the important factors to consider? What about mismatches between the differential lines?This paper will cover the electrical and physical design considerations that are required tomake Gigabit interconnect systems work.

Biography

Greg Aldrich, Mentor Graphics

Greg Aldrich has been a product manager for Mentor Graphics' Interconnectixproduct line since 1994. Prior to that, Mr. Aldrich spent 10 years doing high-speed computer design at Amdahl Corporation in Sunnyvale, CA. He holds aBSEE from the University of Illinois.

Scott McMorrow, SiQual

Scott has 20 years system design experience in Military Aerospace, MedicalElectronics, Semiconductor Applications, Computer System Design, and SignalIntegrity Engineering. Scott received a BSEE from Virginia Tech and is now aconsultant specializing in signal integrity.

Bernard Voss, SiQual

Bernard Voss has 17 years experience executing complex interconnect designsfor various applications. His most recent projects include achieving the highestdensity complete PII system implementation at 4 square inches as well asdesigning a 10Gigabit/second network switch. For this latest project, thousandsof high-speed interconnects were needed (many were differential pairs) withstringent signal integrity requirements. Prior to joining SiQual, Mr. Vossworked at various companies, including Cadence Design Systems, MentorGraphics, Intel, and Zentec Corporation.


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Table of Figures

Figure 1 Common & Differential Mode Circuit............................................. 6

Figure 2 Coupled Transmission Line Equations ............................................ 7

Figure 3 Weak Coupling Example (100 Ohm)............................................... 8

Figure 4 Strong Coupling Example (100 Ohm) ............................................. 9

Figure 5 Coupling Versus Trace Spacing .................................................... 10

Figure 6 What Happens If Traces are Terminated at 100 Ohms?................. 11

Figure 7 Crosstalk Effects of Adjacent Traces............................................. 12

Figure 8 Termination of Differential Pairs................................................... 13

Figure 9 Side-to-Side Stack-Up Guidelines ................................................. 14

Figure 10 Determine Optimal Differential Via Pitch ................................... 15

Figure 11 Differential Placement and Escape Routing Features................... 16

Figure 12 BGA Differential Escape Routing Features Withµvia in Pad ...... 17

Figure 13 Multi-Layer Differential Routing in Lanes .................................. 17

Figure 14 Single-layer Differential Breakout and Routing........................... 18

Figure 15 Differential Routing on Adjacent Layers ..................................... 19

Figure 16 Separating Differential Pair Conductors ...................................... 19

Figure 17 Differential Route Timing Control .............................................. 20

Figure 18 Differential Route Phase Tuning ................................................. 20

Introduction

As digital systems continue to use components with faster edge rates and clock speeds,transmission of the digital information in these systems approaches the microwaverealm. At these speeds digital signal fidelity becomes both a critical success factor anda design challenge. This paper will discuss the role of differential signaling in moderndesigns, its theory, and practical implementation.

Bi-level digital logic works primarily because a high signal-to-noise ratio can translateto exceedingly low error rates. At low speeds, the physical realization of digital logiccircuits can approach the ideal and so low error rates are the logical result. At highspeeds the parasitics, losses, and other realities of physical design make achieving thoselow error rates challenging.

Differential signaling is a technique that, when properly implemented, can improve thesignal to noise ratio and provide a measure of noise rejection, a double benefit toachieving low error rates.


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Differential and Single-Ended Signal Technology & Definitions

Single-Ended and Differential Data

Single-Ended Data

With single-ended data each data bit is passed along a single transmission line. Mostdigital data is transmitted on printed circuit boards in a single-ended fashion. In asingle-ended electrical signal, the voltage level at an input pin is compared to acommon reference to determine the Boolean logic state. There are two assumptions thatare implicit in single-ended logic:

• The common reference voltage is reliable and is “seen” by both the driver and thereceiver.

• The voltage on the input represents the Boolean logic state. Many factors caninvalidate this assumption. Common mode noise, power supply variations, linereflections, and crosstalk are just a few.

Differential Data

With differential data, each data bit is passed along two transmission lines, eithercoupled microstrip, stripline, twisted pair, parallel cable, twinax, or another two-wiremedium. Differential design is commonly used for data transmitted between printedcircuit boards and outside system enclosures.

In differential signaling there is no implicit reference as the voltage potential of adifferential signal is produced across two nets. Therefore, a common reference is notneeded between the driver and the receiver. Instead the signal and its complement aresubtracted using standard logic circuits, and the polarity of the result defines the logicstate. There are two basic advantages to this technique:

• The peak-to-peak signal voltage is actually twice the physical voltage of eithertrace.

• Any disturbing influence that is common to both conductors is rejected when thedifference is taken. This means that the corrupting effect of power supply noise issignificantly reduced.

Differential Mode

Differential mode (also known as odd mode) is when signals transition inoppositedirection, for example, drivers that transition in equal but opposite directions onneighboring coupled transmission lines a differential voltage across the two nets at thedriver, the receiver, and along the entire line.

Common Mode

Common mode (also known as even mode) is when signals transition in thesamedirection, for example, drivers that transition in the same direction on neighboringcoupled transmission lines. Thus, no voltage differential is produced across the nets, buta large voltage level is produced from one end of the net to the other. A common modecurrent is produced that is not canceled by a neighboring field.


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Side-to-Side/Broadside Routing

When forming paired signal paths using conventional planar circuit board technologies,two simple approaches can be taken:

• The two signal tracks can be routedside-to-sideon a common metal layer from thesource gate to the receiver.

• The two signal tracks can be routed one above the other, orbroadside. Thedifferential signal nets are routed on parallel inner conductor layers.

The relative advantages and disadvantages of these techniques are discussed later.

Advantage of Differential Signaling

• Noise immunity—When using differential signaling, strong coupling of themagnetic and electric field is created. This very coupling of complimentary fieldtends to cancel out noise thus increasing noise immunity.

• EMI control —Field cancellation of differential signals reduces far field emissions.The main source of emission then becomes any differential skew between pairs.Controlling skew through driver selection and routing is then key to reducing theoverall Electro-Magnetic Interference levels.

• Timing precision—Because differential switching is performed at the crossing oftwo complementary signals, no separate reference level is needed. Therefore, thistiming of differential signals is less subject to process or thermal drifts in threshold,resulting in additional available margin for timing and reduced timing uncertainty.

Application of Differential Signaling

Differential signaling is used extensively in applications such as:

• USB, 12 MB/s• Firewire (IEEE-1394), 100/200/400 MB/s• LVDS, > 400 MB/s• Ethernet, 10 MB/s, 100 MB/s, 1 GB/s• Fiber channel, 1.0625 GB/s• OC48, 2.4 GB/s• Flat panel interface• Backplanes

With the exception of backplane signaling, all of the applications are typified byexternal circuits that must transmit at reasonably high data rates.

The circuits are designed to minimize radiated noise and loss over much largerdistances than seen within a system chassis. The circuits range from data rates of 10Mb/s to 2.4 Gb/s and above, with frequencies to 1.2 GHz. All can be supported on FR4substrate material with conventional manufacturing techniques. As mentioned earlierthere are several reasons why differential signaling may be employed in advanceddesigns. Noise rejection and higher effective signal levels both add to effective signal-to-noise ratio and improve error rates.


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Timing Path Considerations

Most conventional single-ended logic has an input low to input high range of 800mv to2 volts. This means that the uncertainty in the threshold voltage can be as much as 1.2volts.

Higher precision busses, such as AGP, GTL, and Rambus use an external voltagereference to set the input threshold. This decreases the input low to input high validrange to about +/- 100mv. Better precision than this requires very precise voltagereference generation and is generally not used in typical systems.

For conventional single-ended lines, timing must be measured to the minimum andmaximum possible input thresholds. Typical values are:

• 1v/ns slew rate

• +/-200mv threshold margin (receivers with external reference voltage)• 400ps timing margin lost due to threshold shift (best case)

For differential signal, timing is measured at the differential crossing of thecomplementary pair. Typical values are:

• 1v/ns slew rate• 25mv differential receiver uncertainty

• 50ps timing margin lost, but350ps faster

Differential signaling carries its own voltage reference in the crossing of thecomplementary signals. The internal input skew and noise of the receiver’s differentialamplifier are the only things that affect this reference. This is often kept below +/-25mv, giving better timing precision thus allowing for tighter skew control. Differentialsignaling is especially well suited for source synchronous transmission, wheremaximum data rate/frequency is required. Hybrid differential clock and single endeddata busses are possible, but still compromise some skew control.


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Theory of Differential Signaling

This section reviews some basic theory of differential signaling:

• Common mode versus differential mode circuits

• Differential mode matrix

• Differential mode characteristic impedance calculations

• Differential mode termination approaches.

Figure 1 Common & Differential Mode Circuit

For any two-port circuit with a common ground, the common mode and differentialmode voltages are defined as in the equations above. The differential and commonmode impedances are computed by turning on one signal (differential or common-mode), zeroing the other signal, and finding the ratio of the voltage to the currentflowing on one of the terminals.


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Figure 2 Coupled Transmission Line Equations

The terms in the matrix equations above represent the self-capacitance (C11, C22),inductance (L11, L22), and impedance coefficients (Z11, Z22), a well as the mutualcoupling capacitance (C12, C21), inductance (L12, L21), and impedance coefficients (Z12,Z21).

The self-coupling represents the coupling of the net to the ground return path, usually aneighboring plane. The mutual coupling represents the coupling from one differentialnet to its neighbor net. In a symmetric system, both nets (with exactly the same tracewidth, height, and separation from neighboring planes) will have exactly the same selfand mutual matrix coefficients.

From these matrices, the differential and common mode impedances for symmetriccoupled transmission lines can be calculated.

Differential Mode Impedance

The differential voltage is set to 1 Volt, and the common mode voltage is set to 0 tosolve for the differential mode impedance. This implies that 2/11=V and 2/12 −=V .

For an infinitely long line with no reflection:

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Common Mode Impedance

The common mode voltage is set to 1 Volt, and the differential voltage is set to 0 tosolve for the common mode impedance. This implies that 11=V and 12=V .

For an infinitely long line with no reflection:

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1211 ZZZCommonMode +=

In the examples that follow these expressions are evaluated for the conditions of bothweak and strong coupling between the transmission lines.

Weak Coupling Example

Figure 3 Weak Coupling Example (100 Ohm)

ohmZ

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For a differential transmission line with the pair spaced far apart as shown above, themutual capacitance and inductance are negligible. The overall mutual coupling willapproach zero, and the impedance matrix will look like:

21122211

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The differential impedance is:

)(2)(2 111211 ZZZZDiff =−=

Forweak coupling only, we can conclude that the common mode impedance equalsZ11, while the differential impedance equals 2*Z11.

This assumes no coupling or extremely weak coupling between traces.

Any mutual coupling will increase the common mode and decrease the differentialimpedance.

Strong Coupling Example

Figure 4 Strong Coupling Example (100 Ohm)

= 0

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For a differential line with the pairs spaced close electrically, as shown above. Themutual coupling is increased. The effect of this coupling is to decrease the differentialmode impedance and increase the common mode impedance. As a result, theimpedance matrix will look like:

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1112

1211

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The common mode impedance is:

1211 ZZZCommonMode +=

The differential impedance is:

)(2 1211 ZZZDiff −=

If lines are terminated without accounting for coupling, the differential signal will beincorrectly terminated.

Figure 5 Coupling Versus Trace Spacing

The above table quantifies the effects for the situation where a stripline transmission line isdesigned for a 50 Ohm nominal impedance. As traces are moved closer together, the couplingincreases thus affecting both common mode and differential impedances.

spacingself

impedancemutual

impedancecommon mode

impedancedifferentialimpedance

100 mil 49.995 0.111 50.11 99.7740 mil 49.993 0.533 50.53 98.9225 mil 49.984 1.116 51.10 97.7320 mil 49.972 1.554 51.53 96.8415 mil 49.941 2.331 52.27 95.2210 mil 49.836 3.915 53.75 91.84

5 mil 49.290 7.857 57.15 82.87


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A Common Mistake

Figure 6 What Happens If Traces are Terminated at 100 Ohms?

This slide shows the increase in reflection coefficient for a termination mismatchcaused by mutual impedance on coupled transmission lines and an assumption that thedifferential impedance is twice the single-ended line impedance. At minimum linespacing, the 10 percent reflection would probably be intolerable in most high-speeddesigns.

The reality of coupling between paired transmission lines (for example, it lowersimpedance, increases reflections and noise, reduces noise margins) is often lost ondesigners who do not have access to modern simulation tools. A 10 percent reflection ishard to quantify empirically. It is too easy to assume that wave-shape distortion is dueto unknown and unknowable parasitics. Completing a robust, high-quality designmeans taking every opportunity to improve signal integrity, and proper design andtermination of coupled lines is one key opportunity.

Differential Design

Side-to-Side Pair

To design a side-to-side pair:

• Determine target differential impedance.

Ethernet = 100 ohmsFiber channel = 150 ohms

• Determine desired trace spacing.

As close as possible per manufacturing rules for maximum trace density. Usingminimum manufacturable spacing between differential lines results in bothstrong coupling and minimum route area. There is, however, another reason forchoosing this approach. Strong coupling also achieves the best crosstalk andEMI rejection.

spacingcommon mode

impedancedifferentialimpedance

100 ohmtermination error

Reflectioncoefficient

100 mil 50.11 99.77 0.2% 0.12%40 mil 50.53 98.92 1.1% 0.54%25 mil 51.10 97.73 2.3% 1.15%20 mil 51.53 96.84 3.2% 1.61%15 mil 52.27 95.22 4.8% 2.45%10 mil 53.75 91.84 8.2% 4.25%

5 mil 57.15 82.87 17.1% 9.37%


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• Determine target layer impedance for net without coupling, using nominal widthand stackup.

− It is impossible to create a differential impedance larger than two times thenominal uncoupled trace impedance.

− The nominal uncoupled trace impedance should be about 5 to 10 ohms higherthan one half of the desired differential impedance.

• Route differential pairs at the nominal trace width.

• Compute the differential impedance.

• Adjust the trace-to-trace spacing or single-ended impedance (normally by changingthe trace width or trace layer), and reroute until the proper differential impedance isachieved.

Effects of Crosstalk from Adjacent Traces

Figure 7 Crosstalk Effects of Adjacent Traces

This slide shows both strongly and weakly coupled lines simulated in the presence ofan “aggressor” route, which induces crosstalk on the differential pair.

The simulations are a composite with neighbor coupling, both odd and even modeswitching as well as a simulation with no aggressor present.

Aggressor 5mil from strongcoupled diff pair

Aggressor 5mil from weakcoupled diff pair


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Remarks:

• Coupling to the aggressor (and therefore perturbation of the signal) is stronger onthe side closest to the aggressor. The effect is also strongest on the weakly coupledpair.

• This coupling causes additional bit jitter, which can degrade noise and timingperformance.

• This coupling causes asymmetry in the voltage (and current) waveforms. Thisasymmetry causes a skew between the arrival time of the positive and negativecomponents of the differential signal. This skew is the common mode componentof the signal, which if passed into an environment without containment will radiate.

• Crosstalk from adjacent signals will cause increased EMI, noise degradation, andtiming jitter. This effect is reduced with strong differential pair coupling.

Terminating Differential Pairs

All transmission lines need to be terminated in their characteristic impedance in orderto avoid ringing, overshoot, and other unpleasant distortions. There are severalstrategies for providing the required terminations. The strategies are described below.

Figure 8 Termination of Differential Pairs

Parallel

Differential

Differential


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1. Parallel terminationParallel termination provides DC bias, and is used with opencollector and open emitter drivers. Parallel termination can have significantcommon mode current differences between the pair, and twice the parts may benecessary (pull-up or pull-down depending on driver technology).

2. Differential terminationDifferential termination balances the current between thepair. It requires push-pull drivers and uses fewer parts than parallel termination.Pure differential termination works well, but has a key disadvantage. Differentialterminations do not provide matching for common mode signals. To the extent thatthe lines are asymmetrical (to some degree in most designs) there will be skew andimpedance differences. These effects transfer energy into the common mode. Witha pure differential termination the energy will be reflected, creating waveshapeproblems.

3. Differential tapped terminationDifferential tapped termination decouples the DCpaths between the nets of the pair and also requires push-pull drivers. Differentialtapped terminations have the advantage of terminating the common mode signals,leading to the lowest noise solution. In an AC-coupled scenario (transitioning from5V PECL to 3.3V PECL) the tap can also be used to bias the inputs to the receiver.

Broadside Pairs

Broadside coupled differential pairs (also known as “over-under pairs”) provide verystrong coupling, but this benefit generally does not outweigh the technical costs. Themajor drawbacks for broadside pairs are:

• Extra layers are needed

• Layer registration issues in manufacturing

• Stackup thickness are hard to control

• Differential impedance varies with stackup dimensions

Side-to-Side Stackup Guidelines

Figure 9 Side-to-Side Stack-Up Guidelines


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• For side-to-side designs, the use of micro-strip or strip-line configurations willcontrol impedance. It will also avoid adjacent layer coupling.

• Solid ground planes with coarsely spaced ~1.27mm (0.050”) pitch vias should beused.

• On printed circuit boards with only a portion of differential content, insert partialplanes above and below the differential pair routing where possible to avoidadjacent layer coupling altogether.

• Via and through pin plane layer anti-pad diameter must be small enough to allowthe plane metal to pass between uninterrupted.

Defining Via Pitch

Figure 10 Determine Optimal Differential Via Pitch

To determine the optimal differential via pitch:

• Calculate the minimum via pitch that will allow one balanced pair to pass between.

• Offset the origin of the via matrix for the whole card to best align with pins orbreakout vias from fixed position part instances.

Ideally before determining the exact position of any part instances that will occupy thesame space as differential routing, determine optimal via pitch, and place the partinstances on a grid equal to one half of the via pitch. This will allow the part instance tosnap to a position that is symmetric to the via array and speeds placement by reducingthe number of possible positions.

Be sure to consider the size of anti-pad and hole position tolerances when determiningthe minimum differential via pitch and meeting minimum ATE test probe pitch formaximum in-circuit testability of the card.


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Routing Differential Pairs

Differential Placement and Escape Routing Features

Figure 11 Differential Placement and Escape Routing Features

Using the display grid as a visual aid of where via sites could exist, speeds placing ofall SMD packages:

• Place all SMD packages in a position that is symmetrical with the planned viaarray.

• Use a display grid equal to the via pitch during placement.

• Use the outer layers to integrate discrete part instances into the breakout solution.

The “extra” part to part and SMD pad to via pad spacing required to support a coarsepitch via array improves manufacturability as compared with designs that useminimum feature spacesk, while density is affected very little since it is distributedacross the entire card.

Terminators, pull-up pins, testpoints, etc., must share the breakout via with the activeparts if ideal point-to-point differential routing is desired.


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Case of a BGA

Figure 12 BGA Differential Escape Routing Features Withµµµµvia in Pad

This slide shows Ball Grid Array differential escape routing features usingµvia in padtechnology. By escaping outer BGA pads on the top metal layer, the space needed toescape inner pad positions on the second metal layer is realized by using a two-layerblind microvia in pad:

• Escape outer BGA lands on top and inner lands on the first inner layer.

• Minimize stubs at pull-ups, terminating resistors and test points.

• Utilize a uniform via pitch across entire card to maximize the routing “lanes.”

The diamond-shaped features shown on the slide above are square, single layer, testpoints rotated 45 degrees to fit between through vias.

Multi-Layer Differential Routing in Lanes

Figure 13 Multi-Layer Differential Routing in Lanes


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Maximum density and minimum pair-to-pair crosstalk is achieved by staying withinthe lanes:

• Position tracks within the horizontal and vertical routing “lanes” defined in viaarray.

• Route the pairs with the least horizontal or vertical components first.

Use the Manhattan distance of the guides to determine the order of routing of point-to-point connections within a given layer.

Single-layer Differential Breakout and Routing

Figure 14 Single-layer Differential Breakout and Routing

Use single-layer differential breakout and routing to:

• Reduce conductor width to allow entry and exit of BGA lands on top metal.

• Route differential source synchronous bus/clock groups point to point on a single layer orlayer pair.

The example given on this slide shows the routing of four differential pair USB signals on adesktop computer design.


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Differential Routing on Adjacent Layers

Figure 15 Differential Routing on Adjacent Layers

When routing differential pairs on adjacent layers, the crossings should be at 90degrees.

This is useful to increase density, as shown in the example above, where the clockroutes had to be routed on adjacent signal routing layers of a network switching card.

Separating Differential Pair Conductors

Figure 16 Separating Differential Pair Conductors

Balanced pairs can be separated for only short distances to increase channel routingdensity without greatly reducing the differential coupling desired.

The density of this 10Gbit network switch backplane required some splitting up ofcoupled lines due in part to a backward compliant connector pin out.

In the slide above, note the connector pin pitch supports only “three between” routingat 45 degrees between diagonal positioned pins, which necessitated the splits.


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Differential Route Timing Control

Figure 17 Differential Route Timing Control

For differential route timing control:

• Use the trace free areas that naturally develop in the initial routing solution forintroducing additional delay.

• Delay meanders must provide internal edge-to-edge spacing greater than 2X timestrace width.

Differential Route Phase Tuning

Figure 18 Differential Route Phase Tuning

To fine-tune differential routes, minimize the electrical length imbalances along theentire transmission line from source to load(s).

The final correction should be done at the receiving end of the line to minimize anydistortion caused by the signals being slightly out of phase.


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Conclusion

Differential signaling has the potential to significantly reduce timing uncertainty. Thisis especially true at high speeds where the slew rate of the signal can be a significantfraction of the bit period. Improvements in threshold control can reduce skew causedby offsets, in some cases by nearly an order of magnitude.

The downside to differential signaling is the increased routing space and complexityrequired to achieve a good result. In addition, differential signals may require up totwice the pin or pad count, a significant disadvantage in high-density designs.

Given these detractions it is tempting to find compromises. One such compromise is toroute clocks differentially and data paths single-ended. While this can result in smallimprovements in skew and jitter, it leaves the bulk of potential problem areasunaddressed.

Differential signaling is required for high-speed designs spanning multiple systems as itbrings high noise immunity, low emissions, and low skew.

Fordifferential routing , side-to-side is preferred over broadside as impedance andskew can be more easily managed with symmetry:

- in package escapes- balanced routing- planned routing lanes- meander allowance

Wide spacing to non-differential nets is needed to reduce even more crosstalk-inducedskew, jitter and EMI.

Differential analysis correctly characterizes differential impedance and it allows evaluating differentialskew margins. Design to avoid crosstalk, but perform post-layout analysis as much as possible to confirmwhat crosstalk impact there is from non-differential sources.

differential design for high-speed applications by greg aldrich,...

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