digital circuits: analysis and design, using characteristic and...

Digital Circuits: Analysis and Design, usingCharacteristic and Excitation Tables for

SR, JK, D, and T Flip Flops

Here, we describe how to i) Analyze a digital sequential circuit, from circuit diagramto state machine, and then how to ii) construct a sequential circuit, from description orstate diagram to a physical digital circuit using JK, D, and/or T flip flops and othersupporting logic components. We begin by writing out the standard characteristic tablesand excitation tables for the four flip flops: SR, JK, D, T. We use the JK, D, and T flipflops in several examples throughout, but neglect the SR flip flop due to it’s unknownstate. Clearly, unknown states are less than optimal for designing!

Characteristic Tables: Characteristic tables describe the output, Qn+1, of the FlipFlop given the specific values of the inputs, such as S and R, J and K, or D, or T .Characteristic tables are analogous to treating the Flip Flop as a function. These tablesare used in the analysis of a circuit.

S R Qn+1

0 0 Qn

0 1 01 0 11 1 ?

J K Qn+1

0 0 Qn

0 1 01 0 11 1 Qn

Qn D Qn+1

0 0 00 1 11 0 01 1 1

Qn T Qn+1

0 0 00 1 11 0 11 1 0

Qn+1 = JQn + KQn Qn+1 = D Qn+1 = T ⊕Qn

Excitation Tables: Excitation tables describe the values of the inputs (S, R, J, K,D, T), required in order to cause a particular excitiation (transition from Qn to Qn+1), ofthe Flip Flop. These are used in the design of a circuit, as they allow us to understandwhat the input to each component must be in order to support the intended function.

Qn Qn+1 S R

0 0 0 X0 1 1 01 0 0 11 1 X 0

Qn Qn+1 J K

0 0 0 X0 1 1 X1 0 X 11 1 X 0

Qn Qn+1 D

0 0 00 1 11 0 01 1 1

Qn Qn+1 T

0 0 00 1 11 0 11 1 0

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Section I: Analyzing a sequential logic circuit, from components to statediagram:

Circuit Analysis: From Circuit to State Diagram

1. Compose the next state equations in terms of the current statevariables:

The inputs to the flip flops, that is, the D’s, T’s, J’s, and K’s are com-posed as expressions of the logic gates leading to each input. The out-put signals, (the y’s), are constructed in the same way. The next-stateequations, (the Q+

1 , Q+2 , etc.), however, are constructed using the Char-

acteristic Table.

2. Compose the State Transition table.

3. Create the State Diagram from the State Table.

4. Create a timing diagram.

These will be discussed in class, so for the sake of brevity, we leave thispart as an exercise.

Example 1: Analyze the following circuit:

1. Compose the next state equations in terms of the current state variables:

So for our example here, we have:

Input x. Output y:

D = x + Q2,n

J = x ·Q1,n

2

K = Q1,n

y = J ⊕Q2,n = (x ·Q1,n) ⊕Q2,n

Q+1 = D

Q+2 = JQ2,n + KQ2,n


x Q1 Q2 D J K Sn Q+1 Q+

2 Sn+1 y

0 0 0 1 0 1 0 1 0 2 00 0 1 0 0 1 1 0 0 0 10 1 0 1 0 0 2 1 0 2 00 1 1 0 0 0 3 0 1 1 11 0 0 1 0 1 0 1 0 2 01 0 1 1 0 1 1 1 0 2 11 1 0 1 1 0 2 1 1 3 11 1 1 1 1 0 3 1 1 3 0



We suggest this as an exercise to the eager student!

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Example 2: Analyze this slightly simpler circuit:


Inputs: x. Outputs: y, z.

D = Q1,n

T = x ·Q2,n

y = Q2,n

z = Q1,n + Q2,n

Q+1 = T⊕Q1,n

Q+2 = D


x Q1 Q2 T D Sn Q+1 Q+

2 Sn+1 y z

0 0 0 0 1 0 0 1 1 1 10 0 1 0 1 1 0 1 1 0 10 1 0 0 0 2 1 0 2 1 00 1 1 0 0 3 1 0 2 0 11 0 0 1 1 0 1 1 3 1 11 0 1 0 1 1 0 1 1 0 11 1 0 1 0 2 0 0 0 1 01 1 1 0 0 3 1 0 2 0 1


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Section II: Designing a sequential circuit with Flip Flops from a StateDiagram.

As the title of this section suggests, we essentially perform the steps from the previoussection in reverse order.

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Circuit Design: From State Diagram to Sequential Circuit

1. Create the timing diagram from the State Diagram.

These will be discussed in class, so for the sake of brevity, we leave thispart as an exercise.

2. Create the State Table from the State Diagram.

3. Compose the next state equations in terms of the current statevariables:

We have the data in our State Table. We might, however need a bitof “Karnaugh Map” assitance. Here we encounter an interesting phe-nomenon: We have a choice between flip flops. We can often pick whetherwe wish to use a D, a T, or a JK flip flop. Which ever device we use, wecan easily complete our table using the Excitation Tables above.

4. Compose the Digital Circuit from the next state equations:

Example 3: Here is an example, or rather, three examples. We wish to construct acircuit which supports the following simple state machine, which corresponds to a circuitwhich cuts an input clock frequency in half. We can construct this with a single flip flop,but for the sake of illustration, we construct this in three ways: using a D flip flop, a Tflip flop, and a JK flip flop. Here goes:




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We include enough columns for all three flip flop designs below. Notice from thestate diagram that we only need transitions from S0 to S1 and S1 to S0. There areno transitions from either state S0 or S1 back to itself. There are also no inputsother than the actual clock:

Qn Q+n y D T J K

0 1 0 1 1 1 X1 0 1 0 1 X 1


Our three design choices (ie. which flip flop to use) gives us three possible sets ofequations:

For the D flip flop: Q+n = Qn y = Qn D = Qn

For the T flip flop: Q+n = Qn y = Qn T = 1

For the JK flip flop: Q+n = Qn y = Qn J = K = 1

4. Compose the three Digital Circuits from the next state equations:

Notice that in terms of constructing these circuits, the simplest in terms of numberof signals used, count and distance of wiring, is the T flip flop: the T input is simplytied to high voltage. But this makes perfect sense! A clock is essentially a neverending toggle operations, high to low to high to low ... forever.

Example 4: Here’s another example. We wish to build a device which divides a clockby three. In particular, the state machine cycles through states 0, 1, 2, 0, 1, 2, 0, 1, 2.... Theoutput is 0 except when transitioning from state 2 back to state 0, when it becomes 1 forone clock cycle. The state diagram and the derivations for three different approaches arebelow:

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Here’s where we get to choose which flip flops to use. Rather arbitrarily, one devicewill consist of two D-flip flops, the second device will consist of one T flip flop andone JK flip flop, while the third consists of two JK flip flops. We will present eachdesign in it’s own state transition table to avoid confusion.

Another important new consideration presents itself. We use two flip flops becausewe need to support three states. In order to support n states, we need to have anumber of flipflops, m, for which 2m ≥ n. In this case, we see that m = 2. We canoften choose a variety of combinations of flip flops, which is really the point of thisexample!

Yet another consideration: If we have two flip flops, we can support n = 4 states!But we only need three states, S0, S1, S2. What do we do about state S3, We can’tsimply ignore it because it shows up in our state transition table. So we essentiallyisolate it, by not allowing a transition two or from it. The only transitions allowedin S3 are back to S3.

Approach 1: Two D flip flops:

Qn,1 Qn,2 Q+n,1 Q+

n,2 y D1 D2

0 0 0 1 0 0 10 1 1 0 0 1 01 0 0 0 1 0 01 1 1 1 0 1 1

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Approach 2: One T, One JK flip flop:

Qn,1 Qn,2 Q+n,1 Q+

n,2 y T JK

0 0 0 1 0 0 0X0 1 1 0 0 1 1X1 0 0 0 1 1 X11 1 1 1 0 0 X0

Approach 3: Two JK flip flops:

Qn,1 Qn,2 Q+n,1 Q+

n,2 y J1K1 J2K2

0 0 0 1 0 0X 1X0 1 1 0 0 1X X11 0 0 0 1 X1 0X1 1 1 1 0 X0 X0


Approach 1: Approach 2: Approach 3:D1 = Qn,2 T = Qn,1 ⊕Qn,2 J1 = Qn,2 K1 = Qn,2

D2 = Qn,1 ⊕Qn,2 J = Qn,2 K = Qn,2 J2 = Qn,1 K2 = Qn,1

y = Qn,1 ·Qn,2 y = Qn,1 ·Qn,2 y = Qn,1 ·Qn,2

4. Compose the Digital Circuit from the next state equations:

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Example 5: Design a device which counts up modulo 4, or down modulo 4. Thatis, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1.... or 0, 3, 2, 1, 0, 3, 2, 1, 0, 3, 2.... This is a very common and fre-quently used circuit. It is also easily expandable to modulo 8, 16, 32, etc. You’ll see thiswhen we have completed this circuit.

The input to this circuit is u/d̄ (1 = up, 0 = down). There are two outputs, b1andb0,which form the two bits of the current number in the count.




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u/d̄ Qn,1 Qn,0 Q+n,1 Q+

n,0 b1 b0 D T

1 0 0 0 1 0 1 0 11 0 1 1 0 1 0 1 11 1 0 1 1 1 1 1 11 1 1 0 0 0 0 0 10 0 0 1 1 1 1 1 10 1 1 1 0 1 0 1 10 1 0 0 1 0 1 0 10 0 1 0 0 0 0 0 1


D = u/d̄⊕Qn,1 ⊕Qn,0 T = 1 b1 = u/d̄⊕Qn,1 ⊕Qn,0 b0 = Qn,0

4. Compose the circuit diagram from the next state equations:

Notice that when counting, the least significant bit toggles ... so the T flip flop is anatural choice.

Example 6: Recall the multiplication operation. If both x and y are n = 4, or 8, or16, or 32 bit registers, one approach to multiplication is to load an accumulator with 2nbits with all 0’s. Then one register is repeatedly added into the accumulator, then shiftedup by one bit.

In this example, we present a simplified version of a multiplication control state ma-chine. It controls the shifting and adding operations throughout a multiplication. Herewe let variable x be n bits in length; x is the register which is shifted and added into theaccumulator. We let variable y by n bits, and governs whether x is or is not added intothe accumulator, by checking the value of y[k]: if y[k] is equal to 1, then we add x. If y[k]is 0, we do not add x. Next we shift x up by 1 bit. We repeat this until we are finishedwith the entire multiplication.

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In this process, we identify two input variables: i) “multiply”. When this is equal to1, we are performing a multiplication; ii) “ybit”: when this is equal to 1, we add x intothe accumulator. When “ybit” is equal to 0, we do not perform the addition. The sig-nal “ybit” comes from the individual values y[i], each bit of variable y, in order, bit by bit.

The output signals are: i) “shift”, which causes variable x to shift up by one bit whenactive, and ii) “add”, which performs the addition of x into the accumulator when active.We identify a state to state transition using the input and output variables as:

“multiply”, “ybit” / “add”, “shift”

Our state machine has four states:

S0: Waiting to start; Done (from the last multiplication);S1: x, y, and accumulator are all initialized; Ready to go!S2: Don’t add, then shift x upS3: Add then shift x up

State transitions occur according to the state diagram and state table below. But just“in words”, S0 is where one waits for the “mult” to be asserted to begin a multiplication.Any time “mult” turns off (becomes 0), flow moves immediately back to S0. Moving fromS0 t0 S1, we presume that the registers x, y, accumulator are initialized to the values x, y,and 0, respectively. States S2 is the state supporting “the current digit in the multiplier,y, is a 0, so do NOT add x into the accumulator, then shift x up by one bit, returning tostate S1; conversely, S3 supports “the current digit in the multiplier, y, is a 1, so add xto the accumulator, then shift x up by one bit, returning to state S1.




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multiply ybit Qn,1 Qn,0 Sn Sn+1 Q+n,1 Q+

n,0 add shift D1 D0

0 X X X X 0 0 0 0 0 0 01 X 0 0 0 1 0 1 0 0 0 11 0 0 1 1 2 1 0 0 0 1 01 1 0 1 1 3 1 1 1 0 1 11 X 1 0 2 1 0 1 0 1 0 11 X 1 1 3 1 0 1 0 1 0 1


D1 = mult · (Q1 + Q0) D0 = mult · (ybit + Q1 + Q0)

add = mult · ybit ·Q1 ·Q0 shift = Q1 ·mult

4. Compose the circuit diagram from the next state equations:

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