digital circuits and design - oxford university press

Principal, SSN College of EngineeringChennai

Principal, Mepco Schlenk Engineering CollegeSivakasi

Digital Circuits and Design

S. Salivahanan

S. Arivazhagan

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© Oxford University Press. All rights reserved.

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3Oxford University Press is a department of the University of Oxford.

It furthers the University’s objective of excellence in research, scholarship, and education by publishing worldwide. Oxford is a registered trade mark of

Oxford University Press in the UK and in certain other countries.

Published in India by Oxford University Press

Ground Floor, 2/11, Ansari Road, Daryaganj, New Delhi 110002, India

© Oxford University Press 2018Previous editions published by Vikas Publishing House Pvt. Ltd

The moral rights of the author/s have been asserted.

Fifth Edition published in 2018

All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, without the

prior permission in writing of Oxford University Press, or as expressly permitted by law, by licence, or under terms agreed with the appropriate reprographics

rights organization. Enquiries concerning reproduction outside the scope of the above should be sent to the Rights Department, Oxford University Press, at the

address above.

You must not circulate this work in any other form and you must impose this same condition on any acquirer.

ISBN-13: 978-0-19-948868-1ISBN-10: 0-19-948868-1

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Printed in India by Magic International (P) Ltd., Greater Noida

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Third-party website addresses mentioned in this book are providedby Oxford University Press in good faith and for information only.

Oxford University Press disclaims any responsibility for the material contained therein.

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Preface to the Fifth Edition

Digital electronic circuits are mainly based on digital design. Today, digital circuits form the workhorses of the mobile phone, smart TV, digital camera, computer, GPS, and many other applications that demand digital electronic circuitry. Ever since the invention of transistors in 1947, there has been a growing dependency on digital electronic devices in our day-to-day life. The usage of system-based design tools from the mid-1980s has revolutionized the electronic industry worldwide. The functionality of any digital circuit can be written using a hardware description language (HDL) such as Verilog or VHDL and it can be synthesized into hardware using FPGA or CMOS technology. Every digital device in future will be smart enough to automatically communicate with other devices and also do work without human intervention. Moreover, any technological advancement in industry finds its way to engineering curriculum. This book provides an exposition of the fundamental concepts for the design of digital circuits and furnishes suitable methods and procedures for a variety of digital design applications. The enhanced usage of digital circuits in all disciplines of engineering has created an urge among students to have an in-depth knowledge about digital circuits and design.

About the BookA single textbook dealing with the basics of digital technology including the design aspects of digital circuits is the need of the day. We present this fifth edition to fulfil the requirements of the students of various B.E./B.Tech. degree courses, including Electronics and Communication Engineering, Electrical and Electronics Engineering, Information Technology, Computer Science and Engineering, and Electronics and Instrumentation Engineering offered in all Indian universities. It will also serve as textbook for students of B.Sc. and M.Sc. degree courses in Electronics, Information Technology, Computer Science, Applied Physics and Computer Software, and MCA, AMIE, Grad. IETE, and Diploma courses, and as a reference book for competitive examinations. All the topics have been illustrated with clear diagrams. A variety of examples is given to enable students to design digital circuits efficiently.

Key Features• Provides simple and clear explanation of digital electronic concepts in a lucid language.• Includes numerous examples—each solved step-by-step in chapters.• Numerous review questions and additional problems are given at the end of each chapter to help

reader apply and practice the concepts learnt.

New to this Edition• Introduces newer topics such as SDRAM, DDR RAMs, Flash memories, and GAL.• Includes more solved problems using Boolean algebra, six-variable K-map, Quine-McClusky

method, more logic function implementation using multiplexers, minimization of state diagram using merger graph, and also additional problems for analysis of sequence cells.

• Presents Verilog HDL programs in addition to VHDL programs.

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vi Preface to the Fifth Edition

Organization of the BookThis book is divided into 16 chapters. Each chapter begins with an introduction and ends with review questions and problems.

Chapter 1 provides an introduction to the number system and binary arithmetic and codes.

Chapter 2 deals with Boolean algebra, simplification using Boolean theorems, K-map method, and Quine-McCluskey method.

Chapter 3 discusses logic gates and implementation of switching functions using basic and universal gates.

Chapter 4 deals with various logic families such as TTL and CMOS logic circuits.

Chapters 5 and 6 give a brief description on combinational circuits like arithmetic and data processing.

Chapter 7 describes flip-flops and realization using flip-flops.

Chapter 8 discusses synchronous and asynchronous counters and the design of synchronous counters in detail.

Chapter 9 presents shift registers, shift counters, and ring counters and their design.

Chapter 10 elaborates upon memory devices, which include ROM, RAM, PLA, PAL, and FPGA.

Chapters 11 and 12 are devoted to the design of synchronous and asynchronous sequential circuits, respectively.

Chapter 13 explains some of the most common types of digital to analog and analog to digital converters.

Chapters 14 and 15 deal with clock generators and applications of digital circuits, respectively.

Chapter 16 describes hardware description language (HDL) for digital circuits.

An appendix provides a table of 74XX series TTL gates.

AcknowledgementsWe sincerely thank the managements of SSN College of Engineering, Chennai and Mepco Schlenk Engineering College, Sivakasi, for their constant encouragement and providing the necessary facilities for completing this project. We express our deep gratitude to Prof. M. Salihu, Former Vice-Chancellor, Madurai Kamaraj University, for writing Foreword to the first edition of this book. Many of our colleagues have reviewed the additional material and we thank them for their useful comments, which have improved the book considerably over the previous edition. Our thanks are due to Mr. R. Gopalakrishnan, Mr. K. Rajan, and Mr. A. Chakkarapani for word processing the additional script.

We specially thank Oxford University Press for their initiation to bring out this revised edition in a short span of time.

Dr Salivahanan is greatly thankful to his wife, Kalavathy and sons, Santhosh Kanna and Subadesh Kanna. Dr Arivazhagan expresses his heartfelt thanks to his wife Rosilin Glory and children Sri Madhu Mitha and Selva Yokesh.

We welcome suggestions for the improvement of the book.

S. SalivahananS. Arivazhagan

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ContentsForeword to the First Edition ivPreface to the Fifth Edition v

1. Number System and Codes 11.1 Introduction 11.2 Number System 1

1.2.1 Binary Numbers 11.2.2 Decimal–Binary Conversion 21.2.3 Octal Numbers 31.2.4 Octal–Binary Conversion 41.2.5 Hexadecimal Numbers 51.2.6 Hexadecimal–Binary Conversion 61.2.7 Hexadecimal–Octal Conversion 7

1.3 Floating Point Representation of Numbers 91.4 Arithmetic Operation 10

1.4.1 Binary Arithmetic 101.5 l’s and 2’s Complements 13

1.5.1 l’s Complement Subtraction 131.5.2 2’s Complement Subtraction 141.5.3 Signed Binary Number Representation 151.5.4 Addition in the 2’s Complement System 161.5.5 Subtraction in the 2’s Complement System 171.5.6 ArithmeticOverflow 181.5.7 ComparisonBetween1’sand2’sComplements 19

1.6 9’s Complement 191.6.1 9’s Complement Subtraction 20

1.7 10’s Complement 201.7.1 10’s Complement Subtraction 21

1.8 BinaryCodedDecimal(BCD) 221.8.1 BCDAddition 221.8.2 BCDSubtraction 23

1.9 Codes 251.9.1 Weighted Binary Codes 251.9.2 Non-weightedCodes 271.9.3 Error Detecting Codes 311.9.4 Error Correcting Codes 321.9.5 Alphanumeric Codes 33

Review Questions 36Problems 36

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2. Boolean Algebra and Minimization Techniques 402.1 Introduction 402.2 Development of Boolean Algebra 402.3 Boolean Logic Operations 40

2.3.1 Logical AND Operation 412.3.2 Logical OR Operation 412.3.3 LogicalComplementation(Inversion) 41

2.4 BasicLawsofBooleanAlgebra 412.4.1 Boolean Addition 422.4.2 Boolean Multiplication 422.4.3 Properties of Boolean Algebra 422.4.4 Principle of Duality 44

2.5 Demorgan’s Theorems 452.6 Sum of Products and Product of Sums 53

2.6.1 Minterm 542.6.2 Maxterm 562.6.3 DerivingSumofProduct(SOP)ExpressionfromaTruthTable 592.6.4 DerivingProductofSum(POS)ExpressionfromaTruthTable 59

2.7 Karnaugh Map 602.7.1 Five-variableK-map 68

2.8 Quine-McCluskeyorTabularMethodofMinimizationofLogicFunctions 74Review Questions 85Problems 86

3. Logic Gates 903.1 Introduction 903.2 Positive and Negative Logic Designation 903.3 Logic Gates 91

3.3.1 OR Gate 913.3.2 AND Gate 933.3.3 NOTGate(Inverter) 943.3.4 NAND Gate 953.3.5 NOR Gate 963.3.6 UniversalGates/UniversalBuildingBlocks 963.3.7 Exclusive-OR(Ex-OR)Gate 993.3.8 Exclusive-NOR(Ex-NOR)Gate 101

3.4 Mixed Logic 1103.4.1 Basic Mixed Logic Operators 1113.4.2 Mixed Logic Symbols/Alternate GATE Symbols 1123.4.3 Assertion Levels and Polarity Indication 113

3.5 MultilevelGatingNetworks 1153.5.1 ImplementationofMultilevelGateNetwork 1153.5.2 ConversiontoNAND-NANDandNOR-NORGateNetworks 116

3.6 MultipleOutputGateNetworks 124

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3.6.1 BCD to Excess-3 Code Conversion 124Review Questions 126

4. Logic Families 1284.1 Introduction 1284.2 DigitalIntegratedCircuits 128

4.2.1 BipolarLogicFamilies 1284.2.2 MOS Families 129

4.3 Characteristics of Digital ICs 1294.3.1 Speed of Operation 1294.3.2 PowerDissipation 1304.3.3 Fan-in 1304.3.4 Fan-out 1304.3.5 Noise Immunity or Noise Margin 1304.3.6 Operating Temperature 1314.3.7 PowerSupplyRequirements 1314.3.8 CurrentandVoltageParameters 131

4.4 Current–SourcingandCurrent-SinkingLogic 1314.5 Resistor–TransistorLogic(RTL) 1314.6 Resistor–Capacitor–TransistorLogic(RCTL) 1334.7 Diode–TransistorLogic(DTL) 1344.8 HighThresholdLogic(HTL) 1354.9 Transistor–TransistorLogic(TTLorT2L) 135

4.9.1 TTL NAND Gate 1364.9.2 Other TTL Series 1374.9.3 TTLCircuitOutputConnections 1384.9.4 TTL Parameters 1414.9.5 TTL Inverter 1474.9.6 TTL NOR Gate 1474.9.7 TTLANDandORGate 148

4.10 Emitter-coupledLogic(ECL)—Non-saturatingLogic 1494.10.1 ECL OR/NOR Gate 1514.10.2 ECL Characteristics 151

4.11 Integrated-injectionLogic(I2L) 1524.12 MOS Digital Integrated Circuits 153

4.12.1 MOSFET 1534.12.2 MOSFET Logic Circuits 1544.12.3 Characteristics of MOS Logic 157

4.13 Complementary MOS Logic 1574.13.1 CMOS Inverter 1574.13.2 CMOSNANDGate(74C00) 1584.13.3 CMOS NOR Gate 1594.13.4 CMOS Series 159

4.14 Characteristics of CMOS 160

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4.15 BiCMOS Logic Circuits 1614.16 Compatibility or Interfacing 163

4.16.1 InterfacingCMOSwithTTL 1644.16.2 TTL Driving CMOS 1644.16.3 CMOS Driving TTL 165

4.17 Comparison of Logic Gates 166Review Questions 170Problems 171

5. Arithmetic Circuits 1735.1 Introduction 1735.2 Procedure for the Design of Combinational Circuits 1735.3 Half-Adder 1735.4 Full-Adder 1755.5 K-MapSimplification 1775.6 Half-Subtractor 1785.7 Full-Subtractor 1785.8 ParallelBinaryAdder 180

5.8.1 IC7483—4-bitParallelBinaryAdder 1825.8.2 4-bitParallelBinarySubtractor 183

5.9 ControlledInverter 1835.10 4-bitParallelAdder/Subtractor 1845.11 FastAdder 185

5.11.1 4-bitCarryLookAheadAdder 1855.12 SerialAdder 1885.13 SerialSubtractionUsing2’sComplement 1895.14 4-bitSerialAdder/Subtractor 1895.15 BCD Adder 1905.16 Binary Multiplier 193

5.16.1 Multiplier Using Shift Method 1945.16.2 Parallel Multiplier 194

5.17 Binary Divider 196Review Questions 198

6. Combinational Circuits 1996.1 Introduction 1996.2 Multiplexers(DataSelectors) 199

6.2.1 Basic Four-input Multiplexer 2006.2.2 IC74151—8-to-lMultiplexer 2016.2.3 IC74150—16-to-lMultiplexer 2026.2.4 Implementation of Higher Order Multiplexers 2056.2.5 Implementation of Boolean Expression Using Multiplexers 206

6.3 ApplicationsofMultiplexer 2086.4 Demultiplexers(DataDistributors) 216

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6.4.1 l-to-4 Demultiplexer 2166.4.2 1-to-8Demultiplexer 2176.4.3 IC74154—l-to-16Demultiplexer 218

6.5 Decoders 2206.5.1 Basic Binary Decoder 2206.5.2 3-to-8Decoder 2206.5.3 4-to-16 Decoder 2226.5.4 IC74139—Dual2-to-4Decoder 2236.5.5 IC74154—4-to-16Decoder 2236.5.6 BCD-to-Decimal Decoder 2256.5.7 IC7445—BCD-to-DecimalDecoder 2266.5.8 ImplementationofHigherOrderDecodersUsing LowerOrderDecoders 2276.5.9 BCD-to-Seven-SegmentDecoder/Driver 228

6.6 LiquidCrystalDisplays 2346.7 Encoders 235

6.7.1 Octal-to-Binary Encoder 2366.7.2 Decimal-to-BCD Encoder 2376.7.3 PriorityEncoder 2386.7.4 IC74148—8-to-3PriorityEncoder 2396.7.5 IC74147—Decimal-to-BCDPriorityEncoder 240

6.8 ParityGenerators/Checkers 2436.8.1 DesignofParityCheckers 243

6.9 Parity Generation 2446.9.1 Odd-parity Generator 244

6.10 CodeConverters 2486.10.1 BCD-to-Binary Converters 2496.10.2 Binary-to-Gray Code Converters 2526.10.3 Gray Code-to-Binary Converters 254

6.11 Magnitude Comparator 2576.11.1 4-bit Magnitude Comparator 2596.11.2 IC7485—4-bitMagnitudeComparator 2606.11.3CascadingofIC7485s 262

6.12 Applications of Comparators 262Review Questions 262Problems 263

7. Flip-Flops 2677.1 Introduction 2677.2 Latches 268

7.2.1 Set–Reset(S-R)Latch 2697.2.2 NOR-based S-R Latch 2697.2.3 NAND-based S-R Latch 2717.2.4 StateDiagramandCharacteristicEquationofS-RLatch 272

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7.3 Flip–Flops 2737.3.1 Types of Flip-Flops 273

7.4 S-R Flip-Flop 2737.5 D Flip-Flop 276

7.5.1 StateDiagramandCharacteristicEquationofDFlip-Flop 2777.6 J-KFlip-Flop 278

7.6.1 StateDiagramandCharacteristicEquationofJ-KFlip-Flop 2807.7 TFlip-Flop 281

7.7.1 StateDiagramandCharacteristicEquationofTFlip-Flop 2827.8 Triggeringof 283

7.8.1 LevelTriggeringinFlip-Flops 2847.8.2 EdgeTriggeringinFlip-Flops 2847.8.3 Edge-triggeredDFlip-Flop 2857.8.4 Edge-triggeredJ-KFlip-Flop 286

7.9 AsynchronousInputsinFlip-Flops 2877.10 Master–SlaveFlip-Flops 288

7.10.1 TheRace-aroundCondition 2887.10.2 Master-SlaveJ-KFlip-Flop 289

7.11 Realisation of One Flip-Flop Using Other Flip-Flops 2907.11.1 Realisation of Delay Flip-Flop Using S-R Flip-Flop 2917.11.2 Realisation of J-K Flip-Flop Using S-R Flip-Flop 2927.11.3 Realisation of Trigger Flip-Flop Using S-R Flip-Flop 2957.11.4 Realisation of Delay Flip-Flop Using J-K Flip-Flop 2967.11.5 RealisationofJ-KFlip-FlopUsingDFlip-Flop 298

7.12 Applications of Flip-Flops 2997.12.1 Parallel Data Storage 3007.12.2 Shift Registers 3017.12.3 FrequencyDivision 3017.12.4 Counters 302


8. Counters 3078.1 Introduction 3078.2 Asynchronous(RippleorSerial)Counter 3078.3 RippleCounterwithDecodedOutputs 3098.4 RippleCounterswithModulus<2n 3128.5 CounterICs 313

8.5.1 IC7493—4-bitBinaryRippleCounter 3138.5.2 IC7490—DecadeCounter 315

8.6 AsynchronousDownCounter 3168.7 Up-DownCounter 3178.8 PropagationDelayinRippleCounter 3198.9 Synchronous(Parallel)Counter 319

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8.10 SynchronousCounterwithRippleCarry 3218.11 SynchronousDownCounter 3228.12 SynchronousUp/DownCounter 3238.13 Synchronous/AsynchronousCounter 3238.14 Presettable(Programmable)Counters 3248.15 DesignofSynchronousCounters 324

8.15.1 DesignofMOD-3Counter 3258.15.2 DesignofMOD-6Counter 3278.15.3 DesignofBCDorDecade(MOD-10)Counter 3298.15.4 DesignofMOD-6UnitDistanceCodeCounter 3348.15.5 DesignofMOD-8Up-DownCounter 3388.15.6 DesignofSynchronousCounterUsingSR,JK,TandDFlip-Flops 343

8.16 CounterImplementationandApplications 3508.16.1 FrequencyCounter 3508.16.2 MeasurementofPeriod 3518.16.3 DigitalClock 352


9. Registers 3589.1 Introduction 358

9.1.1 4-bitShiftRegister 3589.2 Shift Registers 359

9.2.1 Serial-in-Serial-out Shift Register 3609.2.2 IC7491—8-bitSerial-in-Serial-outShiftRegister 3639.2.3 Serial-in-Parallel-out Shift Register 3639.2.4 IC74164—8-bitSerial-in-Parallel-outShiftRegister 3649.2.5 Parallel-in-Serial-out Shift Register 3679.2.6 IC74165—8-bitSerial/Parallel-inandSerial-outShiftRegister 3689.2.7 Parallel-in-Parallel-out Register 3699.2.8 IC74195—4-bitSerial/Parallel-inand Serial/Parallel-out Shift Register 369

9.3 Universal Shift Registers 3719.3.1 IC74194—4-bitBidirectionalShiftRegister 372

9.4 Shift Register Counters 3739.4.1 Ring Counter 3749.4.2 Design of 4-bit Self-correcting Ring Counter 3759.4.3 Ring Counter Using IC 74164 Serial Shift Register 379

9.5 ShiftCounter/JohnsonCounter 3809.5.1 Designof4-bitSelf-correctingShiftCounter 381

9.6 SequenceGenerator 3859.6.1 Designof5-bitSequenceGenerator 3869.6.2 Designof6-bitSequenceGenerator 3879.6.3 Designof7-bitSequenceGenerator 389

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9.6.4 SequenceGeneratorUsingMultiplexerandCounter 3929.6.5 SequenceGeneratorUsingCounter 393


10. Memory and Programmable Logic Devices 39810.1 Introduction 39810.2 ClassificationofMemories 399

10.2.1 Registers,MainMemoryandSecondaryMemory 39910.2.2 SequentialAccessMemoryandRandomAccessMemory 39910.2.3 Static and Dynamic Memory 39910.2.4 VolatileandNon-volatileMemory 39910.2.5 Magnetic and Semiconductor Memory 400

10.3 Basic Memory Structure 40010.4 ReadOnlyMemory(ROM) 401

10.4.1 Architecture of ROM 40110.4.2 Types of ROM 40310.4.3 Programming Mechanisms 40410.4.4 OrganizationofaSimpleROM 40510.4.5 ROM ICs 40510.4.6 ROM Access Time 40910.4.7 Applications of ROM 40910.4.8 CombinationalLogicDesignUsingROM 41010.4.9 ProgrammableROM(PROM) 41410.4.10 PROM Programming 41610.4.11 ErasableProgrammableROM(EPROM) 41810.4.12 Programming of EPROM 41910.4.13 ElectricallyErasableProgrammableROM(EEPROM) 421

10.5 RandomAccessMemory(RAM) 42210.5.1 Types of RAM 42210.5.2 Static RAM 42310.5.3 Static RAM ICs 42510.5.4 DynamicRAM(DRAM) 42810.5.5 PseudoStaticRAM(PSRAM) 432

10.5.7 DDR SDRAM 43510.5.8 AdvantagesofRAM 437

10.6 Flash Memory 43710.6.1 FlashMemoryCell 43810.6.2 NOR Flash 43910.6.3 Flash Memory Interfacing 44010.6.4 NAND Flash 44110.6.5 ComparisonBetweenNANDandNORFlash 44210.6.6 Flash Memory as a Replacement for Hard Drives 442

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10.5.6 SynchronousDRAM(SDRAM) 433


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10.7 Memory Decoding 44310.7.1 Address Assignment 443

10.8 MemoryExpansion 44610.9 ProgrammableLogicDevices(PLD) 448

10.9.1 ProgrammableLogicArray(PLA) 45010.9.2 Implementation of Combinational and

SequentialLogicUsingPLA 45410.9.3 Application of PLAs 45910.9.4 ProgrammableArrayLogic(PAL) 45910.9.5 GenericArrayLogic(GAL) 46210.9.6 FieldProgrammableGateArray(FPGA) 464


11. Synchronous Sequential Circuits 47311.1 Introduction 47311.2 GeneralSequentialCircuitModel 47311.3 ClassificationofSequentialCircuits 47411.4 DesignofSynchronousSequentialCircuits 476

11.4.1 Design of Serial Binary Adder 47711.4.2 StateReductionandAssignment 48011.4.3 DesignofSequenceDetectors 48411.4.4 DesignofOdd/EvenParityGenerator 489

11.5 SynchronousSequentialCircuitDesignUsingAlgorithmicStateMachine(ASM) 49311.5.1 AlgorithmicStateMachine(ASMs) 49411.5.2 ASM Charts 49511.5.3 Examples of ASM Charts 49711.5.4 RelationshipBetweenStateDiagramsandASMCharts 49911.5.5 Procedure for Design Using ASM Charts 50111.5.6 DesignofSequenceDetectorUsingASMChart 50111.5.7 Design of Parity-Bit Generator Using ASM Chart 504

11.6 AnalysisofSynchronousSequentialCircuits 509Review Questions 520

12. Asynchronous Sequential Circuits 52112.1 Introduction 52112.2 DesignofFundamentalModeAsynchronousSequentialCircuits 521

12.2.1(a) RealizationUsingDFlip-Flops 52712.2.1(b) RealizationUsingJKFlip-Flops 529

12.3 DesignofPulseModeAsynchronousSequentialCircuits 53412.4 IncompletelySpecifiedStateMachines 55012.5 Problems in Asynchronous Circuits 551

12.5.1 Cycles 55112.5.2 Races 552

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12.5.3 Hazards 55312.6 DesignofHazardFreeSwitchingCircuits 555

12.6.1 StaticHazardsElimination 55512.6.2 DynamicHazardsElimination 55712.6.3 EssentialHazardsElimination 557

Review Questions 558

13. D/A and A/D Converters 56013.1 Introduction 56013.2 Analog and Digital Data Conversions 56013.3 SpecificationsofD/AConverter 56113.4 BasicD/AConversionTechniques 564

13.4.1 Weighted Resistor Type D/A Converter 56513.4.2 R-2R Ladder Type D/A Converter 56913.4.3 VoltageModeR-2RLadder 57213.4.4 Inverted or Current-Mode R-2R Ladder D/A Converter 572

13.5 MultiplyingD/AConverters(MDACs) 57413.6 Sampling Process 57513.7 A/D Converters 57713.8 SpecificationsofA/DConverter 57813.9 ClassificationofA/DConverters 581

13.9.1 SimultaneousType(FlashType)A/DConverter 58213.9.2 CounterTypeA/DConverter 58613.9.3 ContinuousType(ServoTracking)A/DConverter 58713.9.4 SuccessiveApproximationTypeA/DConverter 58913.9.5 Single Slope Type A/D Converter 59213.9.6 Dual Slope Type A/D Converter 59413.9.7 Analog-to-DigitalConverterUsingVoltage-to-TimeConversion 595


14. Clock Generators 59914.1 Introduction 59914.2 Astable Multivibrator 599

14.2.1 Astable Multivibrator Using BJT 59914.2.2 General Description of IC 555 Timer 60214.2.3 Astable Multivibrator Using IC 555 Timer 60414.2.4 Astable Multivibrator Using NAND / NOT Gates 60514.2.5 Astable Multivibrator Using NAND / NOT Gates

withRReturnedtoGround 60614.3 Monostable Multivibrator 607

14.3.1 Monostable Multivibrator Using BJT 60714.3.2 Monostable Multivibrator Using IC 555 Timer 61014.3.3 Monostable Multivibrator Using IC 74121 612

14.4 Bistable Multivibrator Using BJT 613

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14.5 Schmitt Trigger 61514.5.1 Schmitt Trigger Using BJT 61614.5.2 Schmitt Trigger Using IC 555 Timer 61914.5.3 Schmitt Trigger Using IC 74132 620

14.6 CrystalClockGenerators 621Review Questions 621

15. Applications of Digital Circuits 62315.1 Introduction 62315.2 FrequencyCounter 623

15.2.1 5-digitFrequencyCounter 62415.3 Time Meter 625

15.3.1 4-digit Time Meter 62615.4 Bar Graph Display System 62715.5 Multiplexed Display System 627

15.5.1 4-Digit Multiplexed Display System 62915.5.2 Advantages of Multiplexed Display System 63115.5.3 IC74925—4-DigitCounterwithMultiplexed

7-segment Display Decoder/Driver 63115.6 Dot Matrix Display System 63215.7 DigitalVoltmeter 632

15.7.1 3-digitDigitalVoltmeter 63615.7.2 MeritsofDVM 63715.7.3 DemeritsofDVM 638

15.8 DigitalMultimeter(DMM) 63815.8.1 MeasurementofVoltage 63815.8.2 MeasurementofCurrent 63815.8.3 MeasurementofResistance 639


16. HDL for Digital Circuits 64016.1 Introduction to HDL 64016.2 VeryHighSpeedHardwareDescriptionLanguage(VHDL) 640

16.2.1 DataFlowDescription 64016.2.2 Structural Description 64216.2.3 Simulators 64416.2.4 Other Types 64616.2.5 OtherOperators 648

16.3 BehavioralDescription 64816.4 VHDLLibraries 65416.5 VHDLProgramsforCombinationalCircuits 655

16.5.1 VHDLProgramsforLogicGates 65516.5.2 Adders and Subtractors 65716.5.3 Multiplexer and Demultiplexer 659

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16.5.4 Encoder and Decoder 66016.5.5 4-bitParityChecker 66116.5.6 4-bit Magnitude Comparator 66116.5.7 Code Converters 662

16.6 VHDLProgramsforSequentialLogicCircuits 66316.6.1 RealizationofFlip-Flops 66316.6.2 RealizationofShiftRegisters 66616.6.3 Counters 668

16.7 VHDLProgramforArithmeticLogicUnit 67216.8 VerilogHDL 674

16.8.1 Methodology 67416.8.2 Modules 67416.8.3 DataTypes 67516.8.4 Integer,Real,andTimeRegisterDataTypes 67616.8.5 VariableDeclaration 67616.8.6 LevelsofAbstraction 67716.8.7 VerilogOperatorTypes 677

16.9 VerilogHDLProgramsforCombinationalLogicCircuits 67816.9.1 VerilogHDLProgramsforLogicGates 67816.9.2 AddersandSubtractors 68016.9.3 MultiplexerandDemultiplexer 68116.9.4 EncoderandDecoder 68216.9.5 4-bitParityChecker 68216.9.6 4-bitMagnitudeComparator 68216.9.7 CodeConverters 683

16.10 VerilogHDLforSequentialLogicCircuits 68316.10.1 RealizationofFlip-Flops 68316.10.2 RealizationofShiftRegisters 68616.10.3 Counters 687

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16.11 Verilog Program for Arithmetic Logic Unit 690Review Questions 691

Appendices 694Index 711About the Authors 717


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5.3 Half-adderThe simplest combinational circuit which performs the arithmetic addition of two binary digits is called a half-adder. As shown in Fig. 5.1(a), the half-adder has two inputs and two outputs. The two inputs are the two 1-bit numbers A and B, and the two outputs are the sum (S ) of A and B and the carry bit denoted by C. From the truth table of the half-adder shown in Table 5.1, one can understand that the Sum output is 1 when either of the inputs (A or B ) is 1, and the Carry output is 1 when both the inputs (A and B ) are 1.

In a sequential circuit, the output at any time depends on the present input values as well as the past output values. The basic building blocks of an arithmetic unit such as half-adder and full-adder are combinational circuits.

5.2 Procedure for th e Design of Combinational CircuitsAny combinational circuit can be designed by following the design procedure given below:

5.1 IntroductionDigital computers and calculators consist of arithmetic and logic circuits, which contain logic gates and flip-flops that add, subtract, multiply and divide binary numbers. The basic building blocks of the arithmetic unit in a digital computer are adders. These circuits perform operations at speeds less than 1ms.

A digital system consists of two types of circuits, namely(i) Combinational logic circuit,

(ii) Sequential logic circuit.

In a combinational circuit, the output at any time depends only on the input values at that time.

1. From the word description of the problem, identify the inputs and outputs and draw a blockdiagram.

2. Draw a truth table such that it completely describes the operation of the circuit for dif ferentcombinations of inputs.

3. Write down the switching expression(s) for the output(s).

4. Simplify the switching expression using either algebraic or K-map method.

5. Implement the simplified expression using logic gates.

Arithmetic Circuits 5Ch

ap

te

r

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174 Digital Circuits and Design

Table 5.1 Truth table of half-adder

Inputs Outputs

AugendA

AddendB

SumS

CarryC

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

(c) Using NAND gates

Inputs Outputs SumA

A Halfadder Sum (S) B

B Carry (C) Carry

(a) Logic symbol

A

A AB SumB

S = AB + AB

Carry, C = AB

(b ) Logic diagram

Fig. 5.1 Half-adder

From Table 5.1, the logic expression for the Sum output can be written as a Sum of Product expression by summing up the input combinations for which the sum is equal to 1.

In the truth table, the sum output is 1 when AB = 01 and AB = 10. Therefore, the expression for sum is

S = __

A B + A __

B

Now, this expression can be simplified as

S = A ≈ BSimilarly, the logic expression for Carry output can be expressed as a Sum of Product expression

by summing up the input combinations for which the carry is equal to 1. In the truth table, the carry is 1 when AB = 11. Therefore,

C = AB

This expression for C cannot be simplified. The sum output corresponds to a logic Ex-OR function while the carry output corresponds to an AND function. So, the half-adder circuit can be implemented using Ex-OR and AND gates as shown in Fig. 5.1(b). Fig. 5.1(c) gives the realisation of the half-adder using minimum number of NAND gates. The implementation of the half-adder circuit using basic gates AND, OR and NOT is shown in Fig. 5.2.


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175Arithmetic Circuits

A B

A BS = AB + AB

A B

C = AB

Fig. 5.2 Half-adder using basic AND, OR and NOT gates

5.4 Full-adderA half-adder has only two inputs and there is no provision to add a carry coming from the lower order bits when multibit addition is performed. For this purpose, a full-adder is designed. A full-adder is a combinational circuit that performs the arithmetic sum of three input bits and produces a sum output and a carry.

Inputs OutputsCin S

A Full-adder

B Cout

(a) Logic symbol

Inputs OutputsCin A2 2 Sum

HA2

A A1 1 B2 C2

HA1 CoutB B1 C1

(b) Symbol using 2 half-adders

A B CinBCin

ACin Carry

AB Cout = AB + BCin + CinA

Sum

S = A B Cin (c) Logic diagra m

Fig. 5.3 Full-adder

Arithmetic Circuits 175

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The logic symbol of the full adder is shown in Fig.5.3(a). It consists of three inputs and two outputs. The two input variables denoted by A (Augend bit) and B (Addend bit) represent the two significant bits to be added. The third input, Cin, represents the carry from the previous lower significant position. The outputs are designated by the symbols S (for sum) and Cout (for carry). The truth table for the full-adder circuit is shown in Table 5.2. The binary variable S gives the value of the LSB of the sum, and the binary variable Cout, gives the output carry. A full-adder can be formed using two half-adder circuits and an OR gate as shown in Fig. 5.3 (b).

Table 5.2 Truth table of full-adder

Inputs Outputs

Augend bit Addend bit Carry input Sum Carry outputA B Cin S Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

As shown in Table 5.2, there are eight possible input combinations for the three inputs and for each case the S and Cout values are listed. From the truth table, the logic expression for S can be written by summing up the input combinations for which the sum output is 1 as:

S = __

A __

B Cin + __

A B __

C in + A __

B __

C in + ABCin

Simplifying the above expression, we get

S = __

A ( __

B Cin + B __

C in) + A( __

B __

C in + BCin)

= __

A (B ≈ Cin) + A( ______B ≈ Cin )

Let B ≈ Cin = X

Now, S = __

A X + A __

X = A ≈ XReplacing X by B ≈ Cin in the above expression, we have

S = A ≈ B ≈ Cin

Similarly, the logic expression for Cout can be written by summing up the input combinations for which Cout is 1, as given below:

Cout = __

A BCin + A __

B Cin + AB __

C in + ABCin

= BCin(A + __

A ) + A __

B Cin + AB __

C in

= BCin + A __

B Cin + AB __

C in


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Now, the ABCin term is added twice for simplification.

Cout = BCin + A __

B Cin + AB __

C in + ABCin + ABCin

= BCin + ACin(B + __

B ) + AB(Cin + __

C in)

= BCin + ACin + AB

From the simplified expressions of S and Cout, the full-adder circuit can be implemented using one 3-input Ex-OR gate, three 2-input AND gates and one 3-input OR gate as shown in Fig. 5.3(c).

5.5 K-map SimplificationK-map method can also be used for simplifying the logic expressions for S and Cout. The K-maps forthe outputs S and Cout are given in Fig. 5.4.

ABAB

Cin 00 01 11 10Cin 00 01 11 10

0 0 1 0 1 0 0 0 1 0

1 1 0 1 0 1 0 1 1 1

(a) K-map for sum (b) K-map for Cout

Fig. 5.4 Karnaugh maps

From the K-maps, the simplified expressions for S and Cout can be written as follows:____ __ __ ____

S = A B Cin + A B C in + A B C in + ABCin

Cout = AB + BCin + CinA

Using the above expressions, the full-adder can be implemented using basic gates as shown in Fig. 5.5.

A B CinA B Cin

A B Cin

A B Cin S = A B C

A B Cin

AB

BCinCout = AB + BCin + CinA

CinA

Fig. 5.5 Full-adder using basic gates


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From the above equations, the half-subtractor can be implemented using an Ex-OR gate, a NOT gate and an AND gate as shown in Fig. 5.6(b).

5.7 Full-subtractorA full-subtractor is a combinational circuit that performs subtraction involving three bits, namely minuend bit, subtrahend bit and the borrow from the previous stage. The logic symbol for full-subtractor is shown in Fig. 5.7(a).

5.6 Half-subtractorThe half-subtractor is a combinational circuit which is used to perform subtraction of two bits. It has two inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and Bout (borrow out). The logic symbol for a half-subtractor is shown in Fig. 5.6(a). The truth table for half-subtractor is shown in Table 5.3. From the truth table, it is clear that the difference output is 0 if X = Y and 1 if X π Y; the borrow output Bout is 1 whenever X < Y. If X is less than Y, then subtraction is done byborrowing 1 from the next higher order bit.

X (X Y) DX D

YHS

Y Bout (X Y) Bout

(a) Logic symbol (b) Logic diagram

Fig. 5.6 Half-subtractor

Table 5.3 Truth table of half-subtractor

Inputs Outputs

MinuendX

SubtrahendY

DifferenceD

BorrowBout

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

From Table 5.3, as discussed earlier, the Boolean expressions for difference (D) and Borrow out (Bout) can be written as follows:

D = __

X Y + X __

Y = X ≈ Y

Bout = __

X Y

It has three inputs, X (minuend), Y (subtrahend) and Bin (borrow from previous stage), and two outputs D (difference) and Bout (borrow out). The truth table for the full-subtractor is given in Table 5.4. The full-subtractor can be implemented using two half-subtractors and an OR gate as shown in Fig. 5.7(b).


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X D

Y FS

Bin Bout

(a) Logic symbol

BinX2 D2

HS2

X X1 D1 Y2 Bout 2

HS1

Y Y1 Bout 1Bout

(b) Using half-subtractors

Fig. 5.7 Full-subtractor

Table 5.4 Truth table of full-subtractor

Inputs Outputs

Minuend bitX

Subtrahend bitY

Borrow inBin

DifferenceD

Borrow out

out

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

From Table 5.4, the Sum of Product expression for the difference (D ) output can be written as:

D = __

X __

Y Bin + __

X Y ___

Bin + X ____

YBin + XYBin

Simplifying the above expression,

D = ( __

X __

Y + XY)Bin + ( __

X Y + X __

Y ) ___Bin

= ( _____

X ≈ Y )Bin + (X ≈ Y) ___Bin

D = X ≈ Y ≈ Bin

Similarly, the sum of product expression for Bout can be written from the truth table as:

Bout = __

X __

Y Bin + __

X Y ___

Bin + __

X YBin + XYBin

The equation for Bout can be simplified using Karnaugh map as shown in Fig. 5.8.


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XYBin 00 01 11 10

0 0 1 0 0

1 1 1 1 0

Fig. 5.8 K-map for Bout

__ X Bin + YBin

X

Y DBin

Bout

Now, Bout = __

X Y +

Using the above simplified expressions, the full-subtractor can be realised as shown in Fig. 5.9.

Fig. 5.9 Realisation of full-subtractor

One can notice that the equation for D is the same as the sum output for a full-adder, and the borrow output Bout resembles the carry output for full-adder except that one of the inputs is complemented. From these similarities, it is possible to convert a full-adder into a full-subtractor by merely complementing that input prior to its application to the input of gates which form the borrow output.

5.8 Parallel Binary AdderIn most logic circuits, addition of more than 1-bit is carried out. For example, modern comput-ers and calculators use numbers ranging from 8 to 64-bits. The addition of multibit numbers can be accomplished using several full-adders. The 4-bit adder using full-adder circuits is capable of adding two 4-bit numbers resulting in a 4-bit sum and a carry output as shown in Fig. 5.10. Since all the bits of the augend and addend are fed into the adder circuits simultaneously and the additions in each position are taking place at the same time, this circuit is known as parallel adder.


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The addition operation is illustrated in the following example: Let the 4-bit words to be added be

represented by A3 A2 A1 A0 = 111 and B3 B2 B1 B0 = 0011.

Significant place 4 3 2 1Input carry 1 1 1 0Augend word A: 1 1 1 1Addend word B: 0 0 1 1

1 0 0 1 0 Sum

Output carry

Addend and augend inputs

S3 S2 S1 S0

A3 B3 A2 B2 A1 B1 A0 B0

CinC4 C3 C3 C2 C C C

2 1 1 C00

Cout

23 22 21 20

Fig. 5.10 4-bit binary parallel adder

In a 4-bit parallel binary adder circuit, the input to each full-adder will be Ai, Bi and Ci, and the outputs will be Si and Ci + 1, where ‘i ’ varies from 0 to 3. Also, the carry output of the lower order stage is connected to the carry input of the next higher order stage. Hence, this type of adder is called ripple-carry adder.

In the least significant stage, A0, B0 and C0 (which is 0) are added resulting in Sum S0 and Carry C1. This carry C1 becomes the carry input to the second stage. Similarly, in the second stage, A1, B1 and C1 are added resulting in S1 and C2; in the third stage, A2, B2 and C2 are added resulting in S2 and C3; in the fourth stage, A3, B3 and C3 are added resulting in S3 and C4 which is the output carry. Thus, the circuit results in a sum (S3 S2 S1 S0) and a carry output (Cout).

Though the parallel binary adder is said to generate its output immediately after the inputs are applied, its speed of operation is limited by the carry propagation delay through all stages. In each full-adder, the carry input has to be generated from the previous full-adder which has an inherent propagation delay. The propagation delay (tp) of a full-adder is the time difference between the instant at which the inputs (Ai, Bi and Ci) are applied and the instant at which its outputs (Si and Ci + 1) are generated. Therefore, in a 4-bit binary adder, the output in LSB stage is generated only after tp seconds. Similarly, the output in the second stage will be generated only after tp seconds from the time the outputs of the first stage are generated, i.e., after 2tp seconds from the time the inputs are applied; the third stage will generate outputs only after 3tp seconds and the fourth stage will generate outputs only after 4tp seconds. Thus, in a 4-bit binary adder, where each full adder has a propagation delay of 50ns, the output in the fourth stage will be generated only after 4tp = 4 × 50 ns = 200 ns. The magnitude of such delay is prohibitive for high-speed computers. However, there are several methods to reduce this delay.


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One of the methods of speeding up this process is look-ahead carry addition which eliminates the ripple-carry delay. This method is based on the carry generate and the carry propagate functions of the full-adder.

This scheme utilises logic gates to look at the lower order bits of the augend and addend if a higher-order carry is to be generated. This requires extra circuitry for getting high speed adders. This is not a significant consideration with the present day availability of integrated circuits.

5.8.1 IC 7483—4-bit Parallel Binary AdderThe IC 7483 is a commonly available TTL 4-bit parallel binary adder chip. It contains four interconnected full-adders and a look-ahead carry circuitry for its operation. The logic symbol of IC 7483 is shown in Fig. 5.11(a). It has two 4-bit inputs, X3 X2 X1 X0 and Y3 Y2 Y1 Y0, and, a carry input Cin in the LSB stage. The outputs are a 4-bit sum S3 S2 S1 S0 and a carry output Cout from the most significant bit stage.

Y3 Y2 Y1 Y0 X3X2 X1 X0

7483 Cin

C S S3 2 S1 S

out 0

(a) Logic symbol of IC 7483—4-bit parallel binary adder

Y7 Y6 Y5 Y4X7 X6 X5 X4

Y3 Y2 Y1 Y0 X3 X2 X1 X0

Cout 7483 (2) CinCout 7483 (1) Cin

CoutS7 S6 S5 S4 S3 S2 S1 S0

(b) Cascading of two 7483 ICs

Fig. 5.11

Two or more parallel adder blocks can be connected in cascade to perform the addition operation on larger binary numbers. Fig. 5.11(b) shows the cascading connection of two 7483 adders. The four least significant bits of the numbers are added in the first adder. The carry output of this adder is given as the carry input to the second adder, which adds four most significant bits of the numbers. The output carry of the second adder is the final carry output.


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5.9 Controlled Inverter

5.8.2 4-bit Parallel Binary SubtractorJust as a parallel binary adder can be implemented by cascading several full-adders, a parallel binary subtractor can also be implemented by cascading several full-subtractors. A 4-bit parallel binary subtractor that subtracts a 4-bit number Y3 Y2 Y1 Y0 from another 4-bit number X3 X2 X1 X0 is shown in Fig. 5.12. It has 4 difference outputs (D3 D2 D1 D0) and a borrow output (Bout). Note that the Bin of the LSB full-subtractor is connected to 0 and Bout of ith full-subtractor is connected to Bin of (i + 1)th full-subtractor.

X3 Y3 X2 Y2 X1 Y1 X0 Y0

B3 B2B1

FS FS FS FS Bin

B3 B B B2 1 0

B D3D0out D2

D1

Fig. 5.12 4-bit parallel binary subtractor

CY

X

The subtraction of two binary numbers may be accomplished by taking the 2’s complement of the subtrahend and adding to the minuend. By this procedure, the subtraction becomes an addition operation. The 2’s complement of the subtrahend can be obtained by adding a 1 to the 1’s complement of the subtrahend. From the Ex-OR gate truth table, we know that when one of the inputs is LOW the output is the true value of the other input and when one of the inputs is HIGH the output is the complement of the other input. Therefore, the complement of a binary digit can be obtained using an Ex-OR gate as shown in Fig. 5.13.

Fig. 5.13 Ex-OR gate functioning as an inverter

In Fig. 5.13, X is the input, C is the control input and Y is the output. From the figure, it is clear that if C = 0, then Y = X, i.e., input X is available at Y in uncomplemented form; if C = 1, then Y =

__ X ,

i.e., input X is available at Y in complemented form. Thus, if C = 1, the Ex-OR gate can function asan inverter. Similarly, a group of Ex-OR gates can be used to invert a group of bits. Fig. 5.14 showsthe complementing process of a 4-bit binary number (Y3 Y2 Y1 Y0) using a controlled inverter.

When the control input is low, the output will be the input, i.e. Y3 Y2 Y1 Y0. When the control input is high, the output will be the complement of the input

__ Y 3

__ Y 2

__ Y 1

__ Y 0.


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Y3 Y2 Y1 Y0

Controlinput (C)

X3 Y3X2 Y2 X1 Y1 X0 Y0

ADD/SUB

FA FA FA FA Cin

C3S3 C2

S2 C1 S1 C0 S0

S S S3 2 1 S0Cout

Fig. 5.14 Controlled inverter

5.10 4-bit Parallel Adder/SubtractorThe 4-bit parallel binary adder/subtractor circuit shown in Fig. 5.15 performs the _____operations of both addition and subtraction. It has two 4-bit inputs X3 X2 X1 X0 and Y3 Y2 Y1 Y0. The ADD /SUB control line, connected with Cin of the least significant bit of the full-adder, is used to perform the operations of addition and subtraction. The Ex-OR gates are used as controlled inverters.

Fig. 5.15 4-bit parallel adder/subtractor

To perform subtraction, the _____

ADD /SUB control input is kept high. Now, the controlled inverter produces the 1’s complement of the addend ( Y 1 Y 0). Since 1 is given to Cin of the least significant

bit of the adder, it is added to the complemented addend producing 2’s complement of the addend before addition. Now, the data X3 X2 X1 X0 will be added to the 2’s complement of Y3 Y2 Y1 Y0 to produce the Sum, i.e., the difference between the addend and the augend, and Cout, i.e., the borrow output of 4-bit subtractor. Also, it has S3 S2 S1 S0 as sum output and Cout as carry output. When

__ Y 3

__ Y 2

__ __


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_____ ADD / SUB input is LOW, the controlled inverter allows the addend (Y3 Y2 Y1 Y0) without any change

to the input of the full-adder, and the carry input Cin of least significant bit of full-adder, becomes zero. Now, the augend (X3 X2 X1 X0) and addend (Y3 Y2 Y1 Y0) are added with Cin = 0. Hence, the circuit functions as a 4-bit adder resulting in sum S3 S2 S1 S0 and carry Cout.

Example 5.1 Construct a 4-bit parallel binary adder/subtractor using IC 7483.

Solution IC7483 is a 4-bit parallel binary adder. A 4-bit parallel binary adder/subtractor can beimplemented using IC7483, controlled inverter IC7486 and a control line

_____ ADD /SUB as shown in

Fig. E5.1.

B3 B2 B1 B0 ADD/SUBA3 A A A2 1 0

1 2 4 5 9 10 12 13

74863 6 8 11

1 3 8 10 16 4 7 11

Cout Cin14 IC 7483 13

15 2 6 9

S S2 S3 1 S0

Fig. E5.1 4-bit parallel binary adder/subtractor using IC 7483

5.11 Fast AdderIn the parallel binary adder discussed in section 5.7, the carry generated by the ith adder is fed as carry input to the (i + 1)th adder. In this adder, the output (Cout S3 S2 S1 S0) is available only after the carryis propagated through each of the adders i.e., from LSB to MSB adder through intermediate adders. Hence, the addition process can be considered to be complete only after the above carry propagation delay through adders, which is proportional to number of stages in it. One of the methods of making this process faster is look ahead carry addition, which eliminates the ripple carry delay. This method is based on the carry generating and the carry propagating functions of the full adder.

5.11.1 4-bit Carry Look Ahead AdderThe carry look ahead adder is based on the principle of looking at the lower order bits of the augend and addend if a high order carry is generated. This adder reduces the carry delay by reducing the number of gates through which a carry signal must propagate. To explain its operation, consider the truth table of full adder, shown in Table 5.5.


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Table 5.5 Truth table of Full adder, emphasizing the conditions at which carry generation occurs

Row A B Cin S Cout

0 0 0 0 0 0

1 0 0 1 1 0

2 0 1 0 1 0

3 0 1 1 0 1

4 1 0 0 1 0

5 1 0 1 0 1

6 1 1 0 0 1

7 1 1 1 1 1

Æ No carry generationi.e. Cout = 0

Æ Carry propagationi.e. Cout = Cin

Æ Carry generationi.e. Cout = 1

In rows 0 and 1, the carry output (Cout) is always ‘zero’ and independent of carry input

___Gi = Ai Bi Cin + A

___Bi Cini

= Ai Bi (Cin + Cin )

Gi = Ai Bi

Similarly the carry propagation condition (Pi) occurs when either Ai = 1 and Bi = 0 or vice versa as shown in Truth Table 5.5. Now Pi is given by

__ __Pi = Ai Bi + Ai Bi = Ai ≈ Bi

Consider the addition of two 4-bit binary numbers A (A3 A2 A1 A0) and B (B3 B2 B1 B0). The unity

(Cin), while in rows 6 and 7, the Cout is always ‘one’ and independent of Cin. These are known as carry generate combinations. In rows 2, 3, 4 and 5 the carry output is equal to the carry input i.e. Cout = 1 only when Cin = 1. These are carry propagate combinations. Let Gi represent the unity carry (i.e. Cout = 1) generate condition and Pi represent the carry propagate condition of the ith stage ofa parallel adder.

From the Truth Table 5.5 Gi is obtained by summing up the combinations corresponding to 6 th

and 7th rows as follows:

carry output of the ith stage can be expressed in terms of Gi, Pi and Ci – 1 which is the unity carryoutput of the (i – 1)th stage as follows:

Ci (Cout) = Gi + Pi Ci – 1

where Ci – 1 for LSB stage is Cin which is assumed to be zero. In a 4-bit binary adder, four stages of addition are required to add A0 B0, A1 B1, A2 B2 and A3 B3. Therefore, for i = 0, 1, 2 and 3, the Ci’s are given by

C0 = G0 + P1 Cin ............................................. where G0 = A0 B0; P0 = A0 ≈ B0 and Cin = 0

C1 = G1 + P1 C0

= G1 + P1(G0 + P0 Cin)

= G1 + P1 G0 + P1 P0 Cin .................................. where G1 = A1 B1 and P1 = A1 ≈ B1

C2 = G2 + P2 C1

= G2 + P2 (G1 + P1 G0 + P1 P0 Cin)

= G2 + P2 G1 + P2 P1 G0 + P1 P0 Cin ...where G2 = A2 B2 and P2 = A2 ≈ B2

C3 = G3 + P3 C2


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= G3 + P3 (G2 + P2 G1 + P2 P1 P0 Cin)

= G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0 + P3 P2 P1 P0 Cin ...... where G3 = A3 B3 and

P3 = A3 ≈ B3

The sum of A and B is given by

S = C3 S3 S2 S1 S0

where Si = Ai ≈ Bi ≈ Ci – 1 for i = 0, 1, 2, 3

i.e., S0 = A0 ≈ B0 ≈ Cin

S1 = A1 ≈ B1 ≈ C0

S2 = A2 ≈ B2 ≈ C1

S3 = A3 ≈ B3 ≈ C2

Using the above equation, a 4-bit carry look ahead adder can be realized as shown in Fig. 5.16. From the diagram, one can easily understand that the addition of two 4 bit numbers can be done by a carry look ahead adder in a four gate propagation time. Also, it is important to note that the addition of n-bit binary numbers takes the same four gate propagation delay.

P3

G3 P3 G2 P3 P2 G1 P3P2P1G0 P3P2P1P0Cin

A3

G3

B3

P2

A2

G2

B2

P1

A1

G1

B1

P0

A0

G0

B0

C3

G2 P2 G1 P2 P1 G0 P2P1P0Cin

S3

P3

G1 P1 G0 P1 P0 Cin

S2

P2

P0G0

S1

P1

S0

P0

Cin

Fig. 5.16 Logic diagram of 4-bit carry look ahead adder


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5.12 Serial AdderThough the parallel adder performs the addition of two binary numbers at a relatively faster rate, the disadvantage of the parallel addition is that it requires a large amount of logic circuitry. This increases in direct proportion with the number of bits in the numbers being added. On the other hand, in serial addition, the addition operation is carried out bit-by-bit. Therefore, the serial adder requires simpler circuitry than a parallel adder but results in a low speed of operation.

A Reg A3 A2 A1A0 A S SumS3 S2 S1 S0

Full- RegB Reg B3 B2 B1 B0 B adder

Cin Cout Cout

QD

CLK CLR

Initialclear pulse

Fig. 5.17 4-bit serial adder

The diagram of a 4-bit serial adder is shown in Fig. 5.17. The two shift registers A and B are used to store the numbers to be added serially. A single full-adder is used to add one pair of bits at a time along with the carry. The D flip-flop, i.e. carry flip-flop, is used to store the carry output of the full-adder so that it can be added to the next significant position of the numbers in the registers. The contents of the shift registers shift from left to right and their outputs starting from A0 and B0 are fed into a single full-adder along with the output of the carry flip-flop upon application of each clock pulse.

The sum output of the full-adder is fed to the Most Significant Bit (S3) of the sum register. For each succeeding clock pulse, the contents of both the shift registers are shifted once to the right, and new sum bit and new carry bit are transferred to sum register and carry flip-flop respectively. This process continues until all the pairs of bits are added.

The following example explains the operation of a serial adder. Let the augend (A3 A2 A1 A0) be 0111 and the addend (B3 B2 B1 B0) be 0010, stored in shift registers A and B respectively. Also, the carry flip-flop has been initially cleared to the 0 state, so that Cin = 0.

First clock pulse Before the first clock pulse occurs, as the inputs to the Full-adder are A0 = 1, B0 = 0 and Cin = 0. The full-adder outputs will be S = 1 and Cout = 0. When the first clock pulse occurs, the value in the A and B registers shift from left to right by one bit. In addition, the sum (S ) is transferred to S3 of sum register, and the Cout is transferred to the carry flip-flop, whose output becomes 0, which is the carry input of the full-adder.

Second clock pulse Now, A0 = 1, B0 and Cin = 0, at the full-adder input. Therefore, S = 0 and Cout = 1 When the second clock pulse occurs, A, B and sum registers again shift right; S = 0 is transferred to S3, and Cout = 1 is transferred to the carry flip-flop.


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Third clock pulse The values of A0 and B0 are now 1 and 0 respectively, and Cin is 1. These values produce S = 0 and Cout = 1 at the full-adder outputs. On the occurrence of the third clock pulse, the A, B and sum registers shift right, sum = 0 goes to S3, and Cout = 1 goes to the carry flip-flop.

Fourth clock pulse Both A0 and B0 are now zero, and Cin = 1. Therefore, the full-adder produces S = 1 and Cin = 0. The fourth clock pulse transfers S = 1 to S3 and initiates all the other transfers. At the end of this fourth clock pulse, the sum value (1001) will be available in the sum register, and Cout is 0.

5.13 Serial Subtraction Using 2’s ComplementA serial subtractor can be obtained by converting the serial adder of Fig. 5.17 using the 2’s comple-ment system. For subtraction, the subtrahend is stored in the B register and must be 2’s-complement-ed before it is added to the minuend stored in the A register. One simple way to accomplish this is to complement the B register and to make the initial Cin = 1 instead __of 0 prior to the first clock pulse.This can be easily accomplished by feeding the inverted output B0 into the full-adder instead of B0 and initially setting the carry flip-flop to 1 instead of clearing it. The remaining circuitry is the same as serial adder.

Fig. 5.18 4-bit serial subtractor using full-adder

5.14 4-bit Serial Adder/SubtractorA 4-bit serial adder/subtractor can be constructed in a manner similar to its parallel counterpart as shown in Fig. 5.19.

The circuit for 4-bit serial subtractor using full-adder is shown in Fig. 5.18.

A Reg A3 A2 A1A0 A S D3 D2 D1 D0

B Reg B3 B2 B1 B0 B FADifference

CinCout Reg.

Initialpresetpulse

Q PR D

CLK CLK

In the circuit shown in Fig. 5.19, when _____

ADD /SUB = 0, the uncomplemented B3 B2 B1 B0 will be applied to the full-adder. The carry flip-flop is initially cleared by applying a low pulse at

____ CLR

input and the circuit thus functions as a 4-bit serial adder. When _____

ADD /SUB = 1, the complemented output of B register (

__ B 3

__ B 2

__ B 1

__ B 0) will be applied to the full-adder. The carry flip-flop is initially set

to 1 so as to get the 2’s complement of the subtrahend by applying a low pulse at ___

PR input and thus the circuit functions as a 4-bit serial subtractor. The comparison of serial adder with parallel adder is shown in Table 5.5.


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Table 5.5 Serial adder Vs parallel adder

Serial adder Parallel adder

Serial adder is less fast Parallel adder is generally faster

It requires fewer components It requires more components compared to serial adder

Addition is performed bit by bit All the bits are added simultaneously

starting from the LSB

5.15 BCD AdderA BCD adder is a circuit that adds two BCD digits in parallel and produces a sum digit which is also in BCD. A BCD adder must include the correction logic in its internal construction. A block diagram for the BCD adder is shown in Fig. 5.20. This adder has two 4-bit BCD inputs X3 X2 X1 X0

Y3 Y2 Y1 Y0 and a carry input (Cin). It also has a 4-bit sum output (S3 S2 S1 S0 ) and a carry output(Cout). Here, the sum output is also in BCD form.

Cin

X3Augend X2digit

X1Cout

X0Decimaladder 3

Y3 2 Sum

Y2digit

Addend 1

digit Y1 0

Y0

Fig. 5.20 Block diagram of a BCD adder

Fig. 5.19 4-bit serial adder/subtractor

A Reg A3 A2 A1 A0 A S S3 S2 S1S0

B Reg B3 B2 B1 B0FA

B Sum/DifferenceCin

Cout Reg.ADD/SUBInitialPR pulse

Q PR D

CLK CLKCLR

InitialCLRpulse


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A BCD adder circuit must be able to do the following:1. Add two 4-bit BCD numbers using straight binary addition.2. If the four-bit sum is equal to or less than 9, the sum is in proper BCD form and no

correction is needed.3. If the four-bit sum is greater than 9 or if a carry is generated from the sum, the sum is not

in the BCD form. Then, the digit 6 (0110) should be added to the sum to produce the BCDresults. The carry may be produced due to this addition and it is added to the next decimalposition.

Table 5.6 shows the results of BCD addition with corrections indicated.

Table 5.6 Results of BCD addition with corrections indicated

Decimaldigit

Uncorrected BCD Sum Corrected BCD Sum

C3 S3 S2 S1 S0 Cout S3 S2 S1 S0

0 0 0 0 0 0 0 0 01 0 0 0 1 0 0 0 12 0 0 1 0 0 0 1 03 0 0 1 1 0 0 1 1 No4 0 1 0 0 0 1 0 0 correction5 0 1 0 1 0 1 0 1 required6 0 1 1 0 0 1 1 07 0 1 1 1 0 1 1 18 1 0 0 0 1 0 0 09 1 0 0 1 1 0 0 1

10 1 0 1 0 1 0 0 0 011 1 0 1 1 1 0 0 0 112 1 1 0 0 1 0 0 1 013 1 1 0 1 1 0 0 1 114 1 1 1 0 1 0 1 0 0 Correction15 1 1 1 1 1 0 1 0 1 required16 1 0 0 0 0 1 0 1 1 017 1 0 0 0 1 1 0 1 1 118 1 0 0 1 0 1 1 0 0 0

19 1 0 0 1 1 1 1 0 0 1

S3S2

S1S000 01 11 10

00 12

01 13

11 15 11

10 14 10Cn = S3S2 + S3S1 + C3

Fig. 5.21 K-map simplification


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From the Table 5.6, it is clear that correction is required. When the sum output (S3 S2 S1 S0) is greater than 9, i.e., when C3 = 1 (OR) S3 = 1 (AND) [S2 = 1 (OR) S1 = 1], add 0110 to get the BCD result. Note that when C3 = 1, the result is 16 and above; when S3 = 1 (AND) S2 = 1, the result is 12 and above; when S3 = 1 (AND) S1 = 1, the result is 10 and above; when S3 = 1 (AND) [S2 = 1 (OR) S1 = 1], the result is 14 and above. Therefore, the condition for correction can be written as an expression as follows:

Cn = C3 + S3(S2 + S1)

Alternatively, the above condition for correction can also be obtained by K-map method as shown in Fig. 5.21.

As discussed above, a BCD adder must be capable of adding two 4-bit BCD numbers, and the result has to be corrected to BCD, if the above condition is satisfied, by adding 0110. The circuit diagram for BCD adder using full-adders is shown in Fig. 5.22.

X3 Y3 X2 Y2 X1 Y1X0 Y0

C3 C2 C1

(I stage) FA FA FA FA Cin

C3 S3 C2S2 C1 S1 C0 S0

2

13

HA FA HA (II stage)

Cout 3 2 1 0

Fig. 5.22 BCD adder using full-adders

The operation of BCD adder shown in Fig. 5.22 is explained as follows: the first stage of full-adders adds two 4-bit BCD numbers, and its sum (S3 S2 S1 S0) and carry (C3) are checked to


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ascertain whether the result exceeds 9 by AND-OR gate combinations. If the output of OR gate (3) is equal to 1, then correction is required and this is accomplished by adding 0110 in the second stage of adders as shown in Fig. 5.22. Now, the BCD result is S3 S2 S1 S0 with carry output (Cout).

The BCD adder can also be implemented using two 7483 ICs as shown in Fig. 5.23. Here, X3 X2 X1 X0 and Y3 Y2 Y1 Y0 are the BCD inputs. The outputs of adder 1 (S3 S2 S1 S0 and Cout) are checked to ascertain whether the output is greater than 9 by AND-OR gate combinations. If correction is required, then a 0110 is added with the output of adder 1. Now, the adder 2 output forms the BCD result (S3 S2 S1 S0) with carry output (Cout).

Cout 0123

X3 X X2 1 X Y3 Y20 Y1Y0

Cout 7483 (Adder 1)

S3 S2

Cin

S1S0

2

3 1

X3 Y3 X2 Y2 X1 Y1 X0 Y0

7483 (Adder 2) Cin

3 2 1 0

Fig. 5.23 BCD adder using 7483 ICs

5.16 Binary MultiplierMultiplication operation can be carried out by (i) Multipliers using partial product addition and shifting and (ii) Parallel multipliers.


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5.16.1 Multiplier using Shift MethodTo understand the multiplication process using shift method, consider the multiplication of two 4-bit binary numbers 1010 and 1011, as an example.

Fig. 5.24 4-bit binary multiplier using shift method

5.16.2 Parallel MultiplierThe 4-bit multiplier using shift method requires 4 cycles of addition and shifting operations, but it requires only a single 4-bit parallel adder. The speed of multiplication process can be increased considerably in parallel multiplier at the extra cost of increased hardware. The circuit diagram for a 4-bit parallel multiplier is shown in Fig. 5.25.

1 0 1 0

1 0 1 1

1 0 1 0

1 0 1 0

0 0 0 0

1 0 1 0

1 1 0 1 1 1 0

×

Multiplicand

Multiplier

Partial product 1

Partial product 2

Partial product 3

Partial product 4

ÆÆÆÆÆÆ

From the above multiplication process, one can easily understand that if the multiplier bit is 1, then the multiplicand is simply copied as a partial product; if the multiplier bit is 0, then the partial product is 0. Whenever a partial product is obtained, it is shifted one bit to the left of the previous partial product. This process is continued until all the multiplier bits are checked, and then the partial products are added. This multiplication process, i.e. multiplication by partial product addition and shifting, can be implemented using the block diagram shown in Fig. 5.24.

In the diagram shown in Fig. 5.24, the 4-bit multiplier is stored in register Y(Y3 Y2 Y1 Y0); the 4-bit multiplicand is stored in register M(M3 M2 M1 M0), and the X register (X4 X3 X2 X1 X0) is initiallycleared to 00000. Here, to perform multiplication, the least significant bit of the multiplier bit (Y0)is checked whether it is 0 or 1. If Y0 = 1, the number in the multiplicand register (M) is added withthe least significant 4-bits of X register (X3 X2 X1 X0; X4 is to store carry in addition process) and thecombined X and Y register is shifted to the right by 1 bit. If Y0 = 0, the combined X and Y registeris shifted to the right by 1 bit without performing any addition. This process has to be repeated fourtimes to perform 4-bit multiplication. Now, the multiplication result (R7 R6 R5 R4 R3 R2 R1 R0) will beavailable in X and Y registers (X3 X2 X1 X0 Y3 Y2 Y1 Y0).

X reg. X4 X3 X2 X1 X0 Y3 Y2 Y1 Y0 (Multiplier reg.)

4-bit paralleladder

Multiplicand M3 M2 M1 M0reg.


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Y0

X3X2 X1

X0

Y1X3 X2 X1 X0

A3 B3 A2B2 A1 B1 A0 B0

Cout (C3) 7483 - 1 Cin

S3 S2 S1 S0

Y2X3 X2 X1

X0

A7 B7 A6 B6 A5 B5 A4B4

Cout (C7) 7483 - 2 Cin

S7 S6 S5 S4

Y3X3 X2 X1 X0

A11B A10B10 A B9 A

11 9 8 B8

C (C )out 11 7483 - 3 Cin

S11 S10 S9 S8

P7P6 P5

P4 P3P2 P1 P0

Fig. 5.25 4-bit parallel multiplier

It requires three 4-bit parallel binary adders and 16 numbers of 2-input AND gates. Here, each group of 4 AND gates is used to obtain partial products while 4-bit parallel adders are used to add the partial products. Since the generation of partial products and their additions are performed in parallel in the group of AND gates and 4-bit adders respectively, the multiplication result


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(P7 P6 P5 P4 P3 P2 P1 P0) will be available at the output immediately after the propagation delay in the multiplier circuit.

The operation of the parallel multiplier can be understood in a better manner from the symbolic form of binary multiplication process shown in Fig. 5.26.

X3 X2 X1 X0 Multiplicand

Multiplier

Partial product 1 Added in

Partial product 2 IC7483-1

Partial sum 1 Added in

Partial product 3 IC7483-2

Partial sum 2 Added inPartial product 4 IC7483-3

Partial sum 3

Y3 Y2 Y1 Y0

X3Y0 X2Y0 X1Y0 X0Y0

X1Y1 X0Y1X3Y1 X2Y1

C2 C1 C0

C3 S3 S2 S1 S0X3Y2 X2Y2 X1Y2 X0Y2

C6 C5 C4

C7 S7 S6 S5 S4X3Y3 X2Y3 X1Y3 X0Y3

C10 C9 C8

C11 S11 S10 S9 S8

P7 P6 P5 P4 P3 P2 P1 P0 Final result

X reg. X3 X2 X1 X0 Y Y Y3 2 1 Y0 Dividend reg.

4-bitadder/subtractor

Divisor D3 D2 D1 D0reg.

Fig. 5.26 Symbolic form of binary multiplication process

5.17 Binary DividerDivision is the most difficult and time-consuming operation for a general purpose computer. A block diagram of a binary divider unit using restoring technique for division is shown in Fig. 5.27.

Fig. 5.27 Block diagram of a 4-bit binary divider

Here, the dividend is stored in the dividend register Y(Y3 Y2 Y1 Y0), the divisor is stored in the divisor register D(D3 D2 D1 D0) and initially the X register (X3 X2 X1 X0) is cleared.


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The procedure for division operation using the circuit shown in Fig. 5.27 is explained as follows:

1. Shift the combined content of X and Y registers to the left by one bit.

2. Perform trial subtraction by subtracting the content of D register from the content of Xregister.

3. If there is no borrow in the previous subtraction, put 1 in the LSB of Y register, else restorethe original content of X register by adding the contents of D register with the contents ofX register.

4. Repeat steps 1 to 3 for n times, where n is the number of bits in the dividend. For a 4-bitdivision, n = 4.

Now, the quotient will be available in the Y register and the remainder will be in the X register. The above procedure can be understood in a better manner with the following example.

Consider the division of 1011(11) by 0011(3). The dividend and divisor are stored in Y and D registers respectively, and the X register is initially cleared to 0. Therefore,

Y3 Y2 Y1 Y0 = 1011

X3 X2 X1 X0 = 0000

D3 D2 D1 D0 = 0011

Here, both divisor and dividend are 4-bit numbers. Therefore, steps 1–3 have to be repeated four times.

I cycle

Step 1 Shift the combined contents of X and Y to the left by one bit. Therefore,

XY = 0001 0110

Step 2 Subtract dividend 0011 from register X resulting in

X = 1110 with borrow = 1

Step 3 Since borrow = 1, restore the original content in X register by adding dividend 0011 with the content of X register 1110. Now,

XY = 0001 0110

II cycle


XY = 0010 1100

Step 2 Subtract dividend 0011 from X register resulting in


Step 3 Since borrow = 1, restore the original content in X register by adding dividend 0011 with the content of X register 1111. Now,

XY = 0010 1100

III cycle


XY = 0101 1000

Step 2 Subtract dividend 0011 from register X which results in



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Step 3 Since borrow = 0, put 1 in the LSB of Y register (Y0). Therefore,

XY = 0010 1001

IV cycle


XY = 0101 0010

Step 2 Subtract dividend 0011 from X register resulting in


Step 3 Since borrow = 0, put 1 in the LSB of Y register (Y0). Therefore,

XY = 0010 0011

Now, the quotient 0011(3) is available in the Y register and the remainder 0010(2) is available in the X register.

Review Questions1. What is the need of arithmetic circuits?2. What is a half-adder? Write its truth table.3. Design a half-adder using only NOR gates.4. Describe the working of a half-adder.5. What is a full-adder?6. Draw the full-adder circuit using NAND gates only. Explain the functioning of the circuit and show that

the output is that of a full-adder.7. Design a full-adder circuit using only NOR gates. What relation has it to the half-adder circuit?8. Design a full-subtractor using only NAND gates.9. Design a full-subtractor using only basic gates.

10. Design a half-subtractor using only NAND gates.11. Design a half-subtractor using only basic gates.12. Design a half-subtractor using only NOR gates.13. Design a full-subtractor using only NOR gates.14. What is the difference between a full-adder and a full-subtractor?15. Design the logic diagram of a circuit for addition/subtraction. Use a control variable w and a circuit that

functions as a full-adder when w = 0, as a full-subtractor when w = 1.16. Show how a full-adder can be converted to a full-subtractor with the addition of an inverter circuit.17. What are the advantages of complement arithmetic?

18. Design a parallel binary multiplier that multiplies a 4-bit number B = B3 B2 B1 B0 by a 3-bit number

A = A2 A1 A0 to form the product C = C6 C5 C4 C3 C2 C1 C0.[Hint: This can be done with 12 gates and two 4-bit parallel adders. The AND gates are used to formthe products of pairs of bits. The partial products formed by the AND gates are added with the paralleladder.]

REVIEW QUESTIONS


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