digital design chap 5
DESCRIPTION
digital design for diploma studentsTRANSCRIPT
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DIGITAL ELECTRONICS
DEE 204
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DIGITAL ELECTRONICS
• Memory organisationPrinciples of storage, RAM, ROM, PROM,
EPROM.Dynamic theory, logic diagram of a single
bit within a RAM and its operation.Coincident address selection.Block diagram of a single bit within a RAM
and its operation.
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MEMORY ORGANISATION
Principles of storage, RAM, ROM, PROM, EPROM
Storage or memory: - A portion of a system for storing binary data
in large quantities- Consist of arrays of elements generally
either latches or capacitors- Made up of registers where each register
holds one storage location or address
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MEMORY ORGANISATIONPrinciples of storage, RAM, ROM, PROM, EPROMUnits of Binary Data: Bits, Bytes, Nibbles, WordsBits – smallest unit of binary dataByte – 8-bit unit dataNibble – 4-bit unit that could be split from a byteWord – complete unit of information consisting one
or more bytes
* For historical reasons, assembly language defines a word as exactly two bytes. In assembly language, a 32 bit entity is called a double-word and 64 bits is defined as a quad-word.
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MEMORY ORGANISATIONPrinciples of storage, RAM, ROM, PROM,
EPROMBasic Semiconductor Memory Array- Each storage element can retain either 0 or 1
and is called a cell- Memories are made of array of cells where
each block represents one storage cell with location determined by its row and column
- Identified by the number of words times the word size e.g. 16k X 8 memory can store 16,384 words of eight bits each
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MEMORY ORGANISATIONPrinciples of storage,
RAM, ROM, PROM, EPROM
Basic Semiconductor Memory Array
- shown is a 8 X 8 array
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MEMORY ORGANISATIONPrinciples of storage,
RAM, ROM, PROM, EPROM
Basic Semiconductor Memory Array
- shown is a 16 X 4 array
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MEMORY ORGANISATIONPrinciples of storage,
RAM, ROM, PROM, EPROM
Basic Semiconductor Memory Array
- shown is a 64 X 1 array
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MEMORY ORGANISATIONPrinciples of storage,
RAM, ROM, PROM, EPROM
Memory Address and Capacity
- Location of a unit of data is called address specified by the row and column
- Shown is the address row 5 column 4
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MEMORY ORGANISATION
Principles of storage, RAM, ROM, PROM, EPROM
Memory Address and Capacity
- Shown is the address row 3
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MEMORY ORGANISATION
Principles of storage, RAM, ROM, PROM, EPROM
Memory Address and Capacity
- Address as in 3-dimensional array is shown for address row 5, column 8
123
4567
81 2 3 4 5 6 7 8
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MEMORY ORGANISATION
Principles of storage, RAM, ROM, PROM, EPROM
Memory Address and Capacity
Capacity – the total number of data units that can be stored e.g. for figure shown the capacity is 64 bytes
123
4567
81 2 3 4 5 6 7 8
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MEMORY ORGANISATION
Principles of storage, RAM, ROM, PROM, EPROM
Basic Memory Operations: write and read
Write – puts data in a specified address in the memory
Read – copies data out of the specified address in the memory
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MEMORY ORGANISATION
Principles of storage, RAM, ROM, PROM, EPROM
Basic Memory Operations: write operation
7
6
5
4
3
2
1
0
0 0 0 0 1 1 1 1
1 1 1 1 1 1 1 1
1 0 0 0 1 1 0 1
0 0 0 0 0 1 1 0
1 1 1 1 1 1 0 0
1 0 0 0 0 0 0 1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
1
1
1 0 1
1
0 0 1
2
01 1 0 1
3
1. The address is placed on the address bus.
2. Data is placed on the data bus.
3. A write command is issued.
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MEMORY ORGANISATION
Principles of storage, RAM, ROM, PROM, EPROM
Basic Memory Operations: read operation
7
6
5
4
3
2
1
0
0 0 0 0 1 1 1 1
1 1 1 1 1 1 1 1
1 0 0 0 1 1 0 1
0 0 0 0 0 1 1 0
1 1 0 0 0 0 0 1
1 0 0 0 0 0 0 1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
1
1
0 1 1
1
0 0 0
3
11 0 0 1
2
1. The address is placed on the address bus.
2. A read command is issued.
3. A copy of the data is placed in the data bus and shifted into the data register.
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MEMORY ORGANISATION
Principles of storage, RAM, ROM, PROM, EPROM
Basic Memory Operations- Communication between
a memory and its environment is achieved through data lines, address selection lines, and control lines specifying transfer direction
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MEMORY ORGANISATION
Principles of storage, RAM, ROM, PROM, EPROM
Random Access Memory (RAM)- A type of memory in which all addresses are
accessible in an equal amount of time - Have both read and write capability- Write operation replaces previously stored
data with new data unit- Read operation does not erase data unit in
the given address
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MEMORY ORGANISATION
Principles of storage, RAM, ROM, PROM, EPROM
Random Access Memory (RAM)
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MEMORY ORGANISATIONPrinciples of storage, RAM, ROM,
PROM, EPROMRandom Access Memory (RAM):
Static RAM (SRAM)
- uses semiconductor latch memory cells organized into an array of rows and columns
- faster than DRAM but is more complex, takes up more space, and is more expensive
- available in many configurations – a typical large SRAM is organized as 512 k X 8 bits
Row Select 1
Row Select 2
Row Select n
Row Select 0
Memory cell
Data Input/OutputBuffers and Control
Data I/OBit 0
Data I/OBit 1
Data I/OBit 2
Data I/OBit 3
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MEMORY ORGANISATION
Principles of storage, RAM, ROM, PROM, EPROM
Random Access Memory (RAM): Asynchronous SRAM
The basic organization of an asynchronous SRAM is shown: G2
G1
Address lines
Address lines
I/O0
I/O7
Output data
CS
OEWE
Rowdecoder
Memory array
Column I/O
Column decoder
256 rows x128 columns x
8 bits
Input data control
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MEMORY ORGANISATIONPrinciples of storage, RAM, ROM, PROM, EPROMRandom Access Memory (RAM): Asynchronous SRAMRead cycle sequence:• A valid address is put on the address bus• Chip select is LOW• Output enable is LOW• Data is placed on the data busWrite cycle sequence:• A valid address is put on the address bus• Chip select is LOW• Write enable is LOW• Data is placed on the data bus
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MEMORY ORGANISATION
Principles of storage, RAM, ROM, PROM, EPROM
Static RAM: write operation timing waveform
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MEMORY ORGANISATIONPrinciples of storage, RAM, ROM, PROM, EPROMStatic RAM: write operation timing waveform
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MEMORY ORGANISATION
Principles of storage, RAM, ROM, PROM, EPROM
Static RAM: read operation timing waveforms
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MEMORY ORGANISATIONPrinciples of storage, RAM, ROM, PROM, EPROM Static RAM: read operation timing waveforms
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MEMORY ORGANISATIONPrinciples of storage, RAM, ROM,
PROM, EPROMRandom Access Memory (RAM):
Dynamic RAM
- store data bits as a charge on a capacitor.
- are simple and cost effective, but require refresh circuitry to prevent losing data
- the address lines are multiplexed to reduce the number of address lines
A DRAM cell is made up of a transistor and a capacitor
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MEMORY ORGANISATIONPrinciples of storage, RAM, ROM, PROM, EPROMRandom Access Memory (RAM): Dynamic RAM
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MEMORY ORGANISATIONPrinciples of storage, RAM, ROM, PROM, EPROMRandom Access Memory (RAM): Dynamic RAM
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MEMORY ORGANISATION
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MEMORY ORGANISATION
Principles of storage, RAM, ROM, PROM, EPROMRead Only Memory (ROM)- Contains permanent or semi-permanent stored
data- Can be read from the memory; either not
changed at all or changed using special equipments
- Stores data repeatedly used in system applications
- Non-volatile memories which retain stored data when power off
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MEMORY ORGANISATIONPrinciples of storage, RAM, ROM,
PROM, EPROMRead Only Memory (ROM)
- ROM symbol is shown with typical inputs and outputs. the triangles on the outputs indicate it is a tri-stated device
- to read a value from the ROM, an address is placed on the address bus, the chip is enabled, and a short time later (called the access time), data appears on the data bus
ROM 256́ 4
0
&EN
7
A0
255
D
D
D
D
Address input lines
A0
A1
A2
A3
A4
A5
A6
A7
E0
E1
O0
O1
O2
O3
Data output lines
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MEMORY ORGANISATIONPrinciples of storage, RAM, ROM, PROM, EPROMRead Only Memory (ROM): timing waveforms
Address input lines
Data outputs
Address transition
Data output transition
ta
Chip select
Valid data on output lines
Valid address on input lines
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MEMORY ORGANISATION
Principles of storage, RAM, ROM, PROM, EPROM
Programmable ROM (PROM)- Are similar to mask ROMs, only it is custom
programmed by user- Uses fusing process to store bits memory
link is burned open or left intact- Fusing process is irreversible (not to be
changed once programmed)
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MEMORY ORGANISATIONPrinciples of storage, RAM, ROM,
PROM, EPROMErasable Programmable ROM (EPROM)- can be programmed if an existing
program in the memory array is erased first
- an erasable PROM and can be erased by exposure to UV light through a window, to program it, a high voltage is applied to VPP and OE is brought LOW
- another type of erasable PROM is the EEPROM, which can be erased and programmed with electrical pulses
EPROM2048 ́ 8
&EN
0
10
02047A
D
D
D
D
D
D
D
D
O0
O1
O2
O3
O4
O5
O6
O7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
CE/PGM
OE
VPP
UV EPROM package
EPROM logic symbol
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MEMORY ORGANISATIONPrinciples of storage, RAM, ROM,
PROM, EPROMDynamic theory- Stores the data as charge on the
capacitor- When COLUMN (Sense) and ROW
(Control) line goes HIGH, MOSFET conducts and charges capacitor
- When COLUMN and ROW line goes LOW, MOSFET opens and capacitor retain its charge, stores 1 bit
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MEMORY ORGANISATION
Principles of storage, RAM, ROM, PROM, EPROM
Logic diagram of a single bit (cell) within a RAM
-Shown is the logic diagram of a single bit
(cell) within a RAM
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MEMORY ORGANISATION
Dynamic theory, logic diagram of a single bit (cell) within a RAM and its operation
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MEMORY ORGANISATION
Dynamic theory, logic diagram of a single bit (cell) within a RAM and its operation
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MEMORY ORGANISATION
Coincident address selection
- Two k/2 input decoders used
- One performs the row selection and the other performs column selection in two-dimensional matrix configuration
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MEMORY ORGANISATION
Dynamic theory, logic diagram of a single bit within a RAM and its operation
Coincident address selection: address multiplexing
- A technique to reduce number of address lines
- The basic timing waveform of the multiplexing operation will be shown
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MEMORY ORGANISATION
Dynamic theory, logic diagram of a single bit within a RAM and its operation
Coincident address selection: address multiplexing timing waveform
Row address is latched when RAS is LOW
Column address is latched when CAS is LOW
Addresses
RAS
CAS
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MEMORY ORGANISATIONBlock diagram of a single bit within a RAM and
its operationAddress multiplexing: - The ten address lines are multiplexed at the
beginning of a memory cycle by the row address select (RAS) and the column address select (CAS) into two separate 10-bit address
- The 10-bit row address is latched into the row address latch, the 10-bit column address is latched into the column address latch
- Row address and column address is decoded in the memory array, one address is selected
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MEMORY ORGANISATION
Block diagram of a single bit within a RAM and its operation
Figure shown is a simplified block diagram of DRAM using a generic 1M X 1 bit DRAM
1 2
Dataselector
Rowdecoder
Memory array
1024 rows´1024 columns
12
Columndecoder
Input/Output buffersand
Sense amplifier
12
Columnaddress
latch
Rowaddresslatch
Refresh counter
Refreshcontrol
andtiming
A0/A1 0A1/A11
A2/A1 2A3/A1 3A4/A1 4A5/A1 5A6/A1 6A7/A1 7A8/A1 8A9/A1 9
CAS
RAS
Addresslines
DOUTDIN
R/W E
1024
1024
1024
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MEMORY ORGANISATIONBlock diagram of a single bit within a RAM and
its operationAddress multiplexing: (as discussed previously)Read and write cycle: (as discussed previously)Fast Page Mode:
- allows successive read or write operations from a series of columns address that are all on the same row
Refresh Cycles- required every 8ms to 12ms since DRAM is based on
capacitor charge storage for each bit in the memory array, which leaks with temperature and time
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MEMORY ORGANISATIONBlock diagram of a single bit within a RAM and
its operationFast Page Mode:- The timing waveform of a fast page mode for a read
operation is shown
Rowaddress
Column 1address
Column 2address
Column 3address
Column naddress
Validdata
Validdata
Validdata
Validdata
Addresses
RAS
CAS
R/W
DOUT
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MEMORY ORGANISATIONBlock diagram of a single bit within a RAM and
its operation
Fast Page Mode:- A ‘page’ is a section of memory available at a
single row address consisting all columns in the row
- It allows fast successive read or write operations at each column address in a selected row
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MEMORY ORGANISATIONBlock diagram of a single bit within a RAM and
its operationFast Page Mode:
latchedbeen has data dafter valionly HIGH is CAS
disabled isoutput data HIGH is CASwhen -
row selected in thecolumn another selects CASeach -
LOW is RAS as long
as selected remains and selected is address row single a-
LOW and HIGHbetween toggle willCAS meanwhile-
LOW remains andLOW being RAS with loaded is adress row-
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MEMORY ORGANISATIONBlock diagram of a single bit within a RAM and
its operationRefresh cycles: - Read operation automatically refreshes all
addresses in a selected row- Frequency of read cycle is unpredictable, thus
special refresh cycles are required in DRAM systems
- Categorized into1. Burst refresh2. Distributed refresh
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MEMORY ORGANISATIONBlock diagram of a single bit within a RAM and its
operationRefresh cycles:Burst refresh - All rows refreshed consecutively each refresh period- Normal read and write operations are suspended during
burst refreshDistributed refresh- Each row is refreshed at intervals interspersed between
normal read and write cycles- E.g. for a 1024 row memory , an 8ms refresh period
requires each row to be refreshed every 8ms/1024=7.8µs
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MEMORY ORGANISATIONBlock diagram of a single bit within a RAM and
its operationRefresh cycles: Refresh operations
decoder row intoselector databy switched is address -
refreshed be toaddress row generates -
counterrefresh internalan activates -
LOW going RAS beforeLOW going CAS -
:refresh RAS before CAS
addresses row provide toused iscounter external -
HIGH remains CAS -
refreshed be torow
theof address thelatches andLOW n to transitioRAS -
:refreshonly -RAS
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MEMORY ORGANISATIONBlock diagram of a single bit within a RAM and
its operationRefresh cycles: - A refresh cycle of a DRAM is shown