Chapter 14

Sequential logic, Latches and Sequential logic, Latches and FlipFlip--FlopsFlops

Ch14L5-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2

Lesson 5

T- Flip Flop

Ch14L5-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 3

T- Flip-Flop – ve edge triggered• Output Q and Q

Q

Q

K = 1

J = 1

Q

Q1

1

T-FF T

T

-ve Edge triggered circuit

↓

Ch14L5-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 4

T- Flip Flop

1. It has edge trigger clock input so that the output state changes only on a clock edge

2. The NANDs S input of level clocked SR latch is given input = 1 and R input also given input = 1.

3. Second input of both NANDs is common 4. Clock input has an additional circuitry to make

the transition of Q by toggling at an instance corresponding to an edge at the T- input

Ch14L5-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 5

T- Flip Flop� Three input cross coupled NANDs � Third input of lower NAND connects the Q

output� Third input of upper NAND connects the Q

output.� There is no unstable condition in T-FF

state table

Ch14L5-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 6

T input Symbolic representation

• At T input down side arrow corresponds –ve edge instance (0 to 1 transition only)

Ch14L5-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 7

Timing Diagram

• Refer Text

Ch14L5-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 8

T = 1 to 0 transition (Q Toggles)• Output Q resets to 0 and Qn becomes = 1

in case Q was 1 earlier Qn was 0 and after at T the -ve edge occurs because J = 1 and K = 1

• Output Q sets to 1 and Qn becomes = 0 in case Q was 0 earlier Qn was 1 and after at T the -ve edge occurs because J = 1 and K = 1

• Q toggles (complements the nth state after the nth clock transition)

• Qn+1 ← Qn

Ch14L5-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 9

-ve edge triggered T and J = 1, K = 1

Inputs Output State

T Qn J Qn K Qn+1 Qn+1

X means either 1 or 0 input, Qn+1 means next state after nth clock input

1 0 1 1 1 Qn Qn No change

0 1 1 0 1 Qn Qn No change

↑ X 1 X 1 Qn Qn No change

↓ X 1 X 1 Qn Qn Toggles

Summary

Ch14L5-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 11

We learnt that in T- edge triggered FF:

• Because J = 1 and K =1, the output of flip-flop toggles (changes to opposite state) on edge at T-input.

End of Lesson 5 on T- Flip Flop

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