digital design with sm charts -...

Dr. K S Gurumurthy, UVCE, Blore 19/04/2005

DIGITAL DESIGN WITH SM CHARTS

By:

Dr K S Gurumurthy, UVCE, Bangalore

e-Notes for the lectures VTU EDUSAT Programme


DIGITAL DESIGN WITH SM CHARTS The utility of these graphs to define state machines for controlling adders, multipliers and dividers has been shown in earlier chapters. As an alternative to state graphs, state machine chart (SM) may be used to describe the behavior of a state machine. This is a special type of flow chart, called state machine flow chart. SM charts are often used to design control units for digital systems. In this chapter we first start with a brief introduction to state machines. Then we describe the properties of SM charts and how these are used in the design of state machines. Then two examples are discussed. One for a multiplier and the second for a dice game controller. Then construction of VHDL descriptions of these systems directly from the respective SM charts is dealt with. We then proceed with the design and show how PLA tables and logic equations can be derived from SM charts. Showing how alternative designs can be obtained by transforming the SM charts concludes the chapter. 1.1Logic circuits: The classification of logic circuits is given below

Logic circuits Combinational circuits sequential circuits (State machines)

Synchronous or clock asynchronous mode. Fundamental mode pulse mode

A combinational circuit is a circuit whose outputs are determined totally by its external inputs, on other hand a circuit is sequential if its output are determined not only by its external inputs but also by the past history of the circuit. 1.1.1State machines: Another name for a sequential logic circuit is a “state machine”. Since the storage capacity or number of bistable devices is not infinite in a sequential logic circuit, the term ‘finite state machine’ is commonly used. There are three types of circuit models for synchronous state machines. Each model is different because of its output method. The circuit model in fig 1.1 is called a synchronous state machine with Moore outputs. Moore type external outputs are dependant on only the present state of the circuit. They are independent of the external inputs to the circuit.


System clock

Fig 1.1 Moore type machine

The external outputs in the synchronous state machine circuit model shown in fig 1.2 are dependant on both the external inputs and the present state of the circuit. These are called Mealy state machines.

System clock

Fig 1.2 Mealy type machine.

The circuit model illustrated in fig 1.3 is a synchronous state machine with both Moore and Mealy type external outputs is called a mixed type machine.

System clock

Fig 1.3 Mixed type machine.

Input combinational logic.

Bistable memory device

Output combinational logic.

Input combinational logic.



Input Combinational logic.




1.2 State machine charts Flow charts are useful not only in software design but also in the hardware design of digital systems. In this section the usefulness of MS charts in hardware design of digital system is discussed. SM chart is also called an algorithmic state machine (ASM) chart. It is easier to understand the operation of digital system by inspection of the SM chart compared to a state graph. In order to have completely specified proper state graph in which the next state is always uniquely defined for every input combination, the following constraints on the input labels for every state Sk are placed. 1. If Ii and Ij are any pair of input labels on arcs exiting state Sk, then IiIj = 0 if I is not equal to j. With respect to the following figure the conditions are: (X1) (X1’ X2’) = 0 (X1) (X1’ X2) = 0 (X1’ X2’) (X1’ X2) = 0

2. If n arcs exit state Sk and the n arcs have input labels I1, I2,…………In, respectively, then I1 + I2 +. …………+ In =1 The conditions for a proper state graph are automatically satisfied for an SM chart. A given SM chart can be converted into several equivalent forms, and each form leads directly to a hardware realization. An SM chart is different from an ordinary flow chart. Certain specific rules must be followed in constructing the SM chart. When these rules are followed, the SM chart is equivalent to a state graph, and it directly leads to a hardware realization.


1.3 Components of an SM chart: The fig 1.4 shows the 3 principal components of an SM chart, namely state box, decision box and the conditional output box. (Optional state code) xxx (true branch) (false branch)

c) 1 0 a) State Box b) Decision Box c) Conditional Output Box Fig.1.4 Components of an SM chart 1.3.1 State Box: A state box represents the state of the system. The state box contains a state name followed by a slash (/) and an optional output list. After a state assignment has been made, a state code may be placed outside the box at the top. 1.3.2 Decision Box: This box will have two branches. The condition placed in the box is a Boolean expression that is evaluated to determine which branch to select. 1.3.3 The conditional output box: It contains a conditional output list. The conditional outputs depend on both the state of the system and the inputs. 1.4 Construction of SM charts: SM chart is constructed from SM blocks. Each SM block contains exactly one state box, together with the decision boxes and conditional output boxes associated with that state. An SM block has one entrance path and one or more exit paths. Each SM block describes the machine operation during the time the machine is in one state. When a digital system enters the state associated with a given SM block, the outputs on the output list in the state box become true. The conditions in the decision boxes are evaluated to determine which path is followed through SM block. When a conditional output box is encountered along such a path, the corresponding outputs become true. If an output is not encountered along a path, that output is false by default. A path through an SM block from entrance to exit is referred to as a “link path”.

State_ name/ Output list Conditional

output list Condition


1.5 Example of a SM block: The example of SM block is given in fig.1.5. 0ne entrance path

One-s One- state 0 1 Link path a Link path b 0 1 0 1 1 2 3 4 To next states……………………………………………………… Fig1.5 S1-State name, Z1, Z2……….List of outputs, X1, X2………Inputs. When the machine enters the stat S1, outputs Z1 and Z2 become 1. If input X1=0, Z3 and Z4 become 1. If X1 = X2 = 0, at the end of the state time the machine goes to the next via exit path1. On the other hand, if X1 = 1 and X3 = 0, the output Z5 = 1, and exit to the next state will occur via exit path 3. Since Z3 and Z4 are not encountered along this link path, Z3 = Z4 =0 by default.

S1/Z1, Z2,

X1

Z3,Z4

X2 X3

Z5


Equivalent SM block: A given SM block can generally be drawn in several different formats. The following two figures are equivalent SM blocks. 0 1 0 1 1 1 1 0 1 0 0 Fig 1.6 Equivalent SM Blocks

X1 X2

Z2

X2

X1 X1

Z2 Z2

S1/Z1 S1/Z1

S2/ S3/

S2/ S3/


1.5 Example of an ASM chart: A S-R latch built by NOR gates is taken as an example. Fig 1.7 shows the latch, the state diagram and the ASM chart for the SR latch. S R 0 1 1 1 S 0 0 Q 0 0 0 0 1 0 1 0 R 0 Q’ 1 0 a) S-R Latch 1 0 b) State diagram c) ASM Chart Fig.1.7 S-R Latch 1.4 Derivation of SM charts: In this section, method used to design and construct an SM chart for a given sequential control network is discussed. Two examples of SM charts are taken up. They are i) Binary multiplier ii) An electronic dice game. Conversion of an SM chart to a VHDL code process is discussed at the end of this section. 1.4.1 Construction of SM charts: The construction of an SM chart for a sequential control network is similar to that used to derive a state graph. Steps are:

i) First draw a block diagram of the system that we are controlling. ii) Define the required input and output signals to the control network. iii) Then construct the chart that tests the input signals and generates the proper

sequence of output signals.

a/0 b/0

a/0

b/0

S.R’

R’


1.5 Binary Multiplier: The first example that is discussed is Binary multiplier. As per the procedure, the block diagram of the 4-bit * 4-bit multiplier is shown in fig 1.8 Product Accumulator Load SH ADD

Multiplier

Done DONE ST Clk M Multiplicand Fig 1.8 Block diagram for the Multiplier 1.7.1Design: In this section a multiplier for unsigned binary numbers is discussed and designed. If the product aimed at is A*B, the first operand A is called multiplicand and the second operand is called multiplier. Binary multiplication requires shifting and adding operations. Illustration: Let us take an example where in A = 12 (multiplicand) and B =11(multiplier) 1 1 0 0 *1 0 1 1 1 1 0 0 (multiply by M = 1) 1 1 0 0 - (multiply by M = 1 and shift) 1 0 0 1 0 0 (add) 0 0 0 0 - - (multiply by M = 0 and shift) 1 0 0 1 0 0 (add) 1 1 0 0 - - - (multiply by M = 1 and shift) 1 0 0 0 0 1 0 0 This is equivalent to 132 in decimal.

8 7 6 5 4 3 2 1 0

C O N T R O L

Cm 4-bit Adder


Multiplication of two 4 –bit numbers requires 1. a 4-bit multiplicand register, 2. a 4-bit multiplier register, 3. a 4-bit full adder, and 4. an 8-bit register for the product.

The product register serves as an accumulator to accumulate the sum of partial products. If the multiplicand were shifted left each time before it was added to the accumulator, as was done in the example, an 8-bit adder would be needed. So it is better to shift the contents of the product register to the right each time, as shown in the block diagram of the Figure 2.3.This type of multiplier is sometimes called a serial-parallel as the multiplier bits are processed serially and the addition takes place in parallel. 4 bits from the ACC and 4 bits from the multiplicand register are connected to the adder inputs. The 4 sum bits from the multiplicand register are connected back to the ACC. When an add signal (Ad) occurs, the adder outputs transferred to the ACC by the next clock pulse, thus causing the multiplicand to be added to the accumulator. The carry output from Cm is temporarily stored at the extra bit (8th) at the left end of the product register. When a shift signal (Sh) occurs, all 9 bits of ACC are shifted right by the next clock pulse. Since the lower 4 bits of the product register are initially unused, the multiplier is stored in this location instead of storing in a separate register. As each multiplier bit is used, it is shifted out to the right end of the register to make room for additional product bits. A shift signal (SH) is used to shift the contents of the product register. Shifting occurs at the every clock pulse. The control circuit puts out the proper sequence of add and shift signals after a start signal (ST=1) has been received. If the current multiplier bit (M) is 1, the multiplicand is added to the accumulator followed by a right shift. If the multiplier bit is 0, the addition is skipped, and only the right shift occurs. The multiplication example (of 12*11) is reworked below showing the location of the bits in the register at each clock time. 8 7 6 5 4 3 2 1 0 M(11) Initial contents of product register

0 0 0 0 0 1 0 1 1

Add multiplicand(12)since M=1 1 1 0 0 After addition 0 1 1 0 0 1 0 1 1 After shift 0 0 1 1 0 0 1 0 1 Add multiplicand since M=1 1 1 0 0 After addition 1 0 0 1 0 0 1 0 1 After shift 0 1 0 0 1 0 0 1 0 Skip addition since M=0 After shift 0 0 1 0 0 1 0 0 1 Add multiplicand since M=1 1 1 0 0 After addition 1 0 0 0 0 1 0 0 1 After shift (final answer) 132 0 1 0 0 0 0 1 0 0

Fig 1.9 Illustration Binary Multiplier.


The control circuit must be designed to output the proper sequence of add and shift signals. The fig 1.10 shows a state graph for the control circuit. In this figure ‘S0’is the reset state, and the network stays in ‘S0’ until a start signal (ST=1) received. This generates a ‘load’ signal, which causes the multiplier to be loaded into the lower 4 bits of the accumulator (4<<) and the upper 5 bits of the accumulator to be cleared. In state ‘S1’, the low order bits of the multiplier (M) are tested. If M=1, an add signal is generated, and if M=0, a shift signal is generated. Similarly, in states S3, S5 andS7, the current multiplier bit (M) is tested to determine whether to generate an add or shift signal. A shift signal is always generated at the next clock time following an add signal (states S2, S4, & S8). After 4 shifts have been affected, the control network goes to S9, and a done signal is generated returning to ‘S0’.

1.7.2 SM chart for control of the binary multiplier: Fig1.10 shows the multiplier control St Done Load Ad M Sh K Fig 1.10 Multiplier control.

Add or shift

control

Counter


The add-shift control generates the required sequence of add and shift signals. The counter counts the number of shift and outputs K=1 just before the last shift occurs. The SM chart for the multiplier control is shown in fig 1.12. 0 1 0 1 0 1 1 0

Fig 1.11 SM chart for binary multiplier In state S0, when the start signal St is 1, the registers are loaded. In S1, the multiplier bit M is tested. If M=1, an add signal is generated and the machine goes to state S2. if M=0, a shift signal is generated and K is tested. If K=1, this will be last shift and the next state is S3. in S2, a shift signal is generated as a shift must always follow an add. If K=1, the network goes to S3 at the time of the last shift; otherwise, the network goes break to S1. In S3 the done signal is turned ON. Conversion of an SM chart to a VHDL process is straightforward. A case statement can be used to specify what happens in each state. Each condition box corresponds directly to an ‘if’ statement. The VHDL code is given in Fig 1.13

S0/

St

Load

S1/

S2/sh

K

K

M

Sh Ad

S3/Done


1.8 EXAMPLE NO.2: ELECTRONIC DICE GAME: This is a game based on a dice, which will have 6 faces with numbers 1,2,3,4,5,6. In this game two dices will be thrown, and depending on the sum of the numbers seen on the faces of the dices, the result is decided. One can come out with many conditions to decide whether a player has won or not. The purpose of this example is to design a circuit that will simulate the above said idea. Fig.1.14 shows the block diagram for the dice game. Two counters are used to simulate the ROLL of DICE. Each counter counts in the sequence 1,2,3,4,5,6,1,………Thus after the ROLL of the DICE the SUM of the values in the two counters will be in the range 2 through 12.The rules of the game are as follows: 1. After the first ROLL of the DICE, the player wins if the SUM is 7 or 11.Th player LOSES if the SUM is 2,3 or 12. Otherwise the SUM the player obtained on the first ROLL is referred to as a POINT, and the player must ROLL the DICE again. 2. On the second or subsequent ROLL of the DICE, the player WINS if the SUM is 7. Otherwise, the player must ROLL again until he or she finally WINS or LOSES or RESETS (starts a new game). The inputs to the DICE game come from push buttons RB (Roll Button) and RESET. RESET is used to initiate a new game. When the ROLL button is pushed, the DICE counters count at high speed. So the values cannot be read on the display. When the Roll Button is released the values in the two counters are displayed and the game can proceed. If the WIN light is not on, the player must push the Roll Button again.


VHDL CODE for Binary Multiplier SM Chart: entity Multi is port (CLK, St, K, M: in bit; Load, Sh.Ad, Done: out bit); end Mult; architecture SMbehave of Mult is signal state, Nextstate: integer range 0 to 3; begin process (St, K, M, State) --start if state or inputs change begin Load<=’0’; Sh<= ‘0’; Ad<=’0’; case State is When 0 => if St = ‘1’ then --St (state 0) Load <= ‘1’; Nextstate <= 1; else Nextstate <=0; --St’ end if; When 1=> if M = ‘1’ then --M (state 1) Ad<= ‘1’ Next state <=2; else Sh<= ‘1’ if K = ‘1’ then Nextstate <=3; --K else Nextstate <= 1 --K’ end if; end if; When 2 => Sh <= ‘1’ (-- state 2) if K = ‘1’ then Nextstate <=3; --K else Nextstate <=1; --K’ end if; When 3 => Done <= ‘1’; -- (stat3) Nextstate <= 0; end case; end process; Process (CLK) begin if CLK = ‘1’ then State <= Nextstate; --update state on rising edge end if; end process; end SMbehave;


Fig1.12 VHDL code for binary multiplier SM chart RB ROLL

RESET Sum D7, 11 WIN D2, 3,12 Eq LOSE

Sp Fig 1.13 Block diagram of the Electronic Dice Game

Display Display

1-6 counter 1-6 counter

Adder

Test Logic

C O N T R O L

POINT Register

Comparator

D7


Flow chart for DICE game: It is given in fig 1.14. After rolling the dice, the sum is tested. If it is 7 or 11, the player wins, if it is 2,3 or 12 the player loses. Otherwise the sum is saved in the point register, and the player wins. If it is 7, he or she loses. Otherwise the player rolls again. After winning or giving it up the player must push reset button again to begin a new game. The components of the dice game are: Adder-ads the output of two counters Register-stores the POINT Test Logic- determines the condition for a WIN or LOSE Control Network- Controls the dice game

Y N N Y Y N N Y

Y N N Y Y

Fig 1.14 Flow chart for Dice game

Roll dice

S=7/ 11

S=2,3,12

Store sum in point Reg

Roll Dice

S= Point

Sum

Lose

Reset

Win

Reset


Input signals to the control network are defined as follows: D7 = 1 If the sum of the dice (output of the counters) is 7 D7, 11 = 1 If the sum of the dice is 7 or 11 D2, 3,12 = 1 If the sum of the dice is 2,3 or 12 Eq = 1 If the sum of the dice equals the number stored in the Point Register. RB = 1 When the reset button is pressed Outputs from the control network are defined as follows:

ROLL = 1 Enables the dice counters Sp = 1 Causes the sum to be stored in the Point Register Win = 1 turns on the win light Lose = 1 turns on the Lose light

Using the control signals defined above, SM chart is derived and the same is shown in Fig 1.15.The control network waits in state S0 until the roll button is pressed (RB = 1). Then it goes to state S1, and the ROLL counters are enabled as long as RB = 1. As soon as the ROLL button is released (RB = 0), D7, 11 is tested. If the sum is 7 or 11, the network goes to states S2 and turns on the Win light; otherwise, D2, 3,12 is tested. If the sum is 2,3,or 12, the network goes to state S3 and turns on the Lose light; otherwise, the signal Sp becomes 1 and the sum is stored in the Point register. It then enters S4 and waits for the player to ROLL the dice again. In S3, after the ROLL button is released, if Eq = 1, the sum equals the Point and state S2 is entered to indicate a Win. If D7 = 1, the Sum is 7 and S3 is entered to indicate a Lose. Otherwise, control returns to S4 so that the player can roll again. When in S2 or S3, the game is reset to S0 when the reset button is pressed. End of section 1.8

Fig 1.15 SM chart for Dice game – Please refer to the annexure -1 1.9 Realization of SM charts: The realization consists of a combinational sub network, together with Flip-flop storing the state of the network. As an example SM chart for binary multiplier is taken up. This SM chart is given in Fig1.12.The controller for the multiplier can be realized using a PLA and D flip-flops. The controller chart has 4 states and you need 2 (2 = 4) D flip-flops. The PLA table is given table1.1.


Table1.1 PLA table for Multiplier Controller.

The PLA has 5 inputs and 6 outputs. Each row in the table corresponds to one of the link paths in the SM chart. Since So has two exit paths the table has two rows for present state So. The first row corresponds to the St = 0 exit path. So the next state and output are 0. In the second row, St = 1, so the next state is a don’t care in the corresponding rows. The outputs for each row can be filled in by tracing the corresponding link paths on the SM chart. For example, the link path from S1 to S2 passes through conditional output Ad, so Ad = 1 in this row. Since S2 has a Moore output Sh, Sh = 1 in both of the rows for which AB = 10. By inspection of the PLA table, the logic equations for the multiplier control are: A+ = A’BM’K + A’BM + AB’K; B+ = A’B’St + A’BM’ + AB’; Load = A’B’St Sh = A’B’St = AB’; Ad = A’BM’; Done = AB St Load Sp Ad M Done K Clock Fig. 1.19 PLA realization of Multiplier control

A B St M K A+ B+ Load Sh Ad Done So

0 0 0 - - 0 0 1 - -

0 0 0 0 0 0 0 1 1 0 0 0

S1

0 1 - 0 0 0 1 - 0 1 0 1 - 1 -

0 1 0 1 0 0 1 1 0 1 0 0 1 0 0 0 1 0

S2

1 0 - - 0 1 0 - - 1

0 1 0 1 0 0 1 1 0 1 0 0

S3 1 1 - - - 0 0 0 0 0 1

P L A

D Q

D Q


1.10 Linked State Machines When a sequential machine becomes large and complex, it is desirable to divide the machine up into several smaller machines that are linked together. Each of the smaller machines is easier to design and implement. Also, one of the submachines may be ‘called’ in several different places by the main machine. This is analogous to dividing a large software program into procedures that are called by the main program. Figure 1.20 shows the SM charts for two serially linked state machines. The machine (Machine ‘A’) executes a sequence of some states until it is ready to call the submachine (machine ‘B’). When state SA is reached, the output signal ZA activates machine B. Machine B then leaves its idle state and executes a sequence of other states. When it is finished, it outputs ZB before returning to the idle state. When machine A receives ZB, it continues to execute other states. These two machines are assumed to have a common clock. Machine ‘A’ Machine ‘B’ 0 1 0 1 Figure 1.20 SM charts for serially linked State Machines

SOME STATES

SA/ZA

OTHER STATES

IDLE

OTHER STATES

SB/ZB

ZB

ZA


1.11 Conclusions In this Chapter the following topics have been discussed.

i) An introduction to SM charts and basic of SM charts. ii) Procedure to design digital system based on the constructed SM chart.

a) Draw the block diagram of the digital system. b) Represent the control unit by an SM chart. c) Write the behavioral VHDL code based on this chart.

iii) Hardware implementation using PLAs. a) PLA tables and equations are derived by tracing link paths on an SM chart. b) Using the next state equations D flip-flops are used with PLA to arrive at Moore/Mealy machines for the control circuit designs.

iv) PLA size can be reduced by transforming the SM chart into a form in which only one input is tested in each state. v) However this generally increases the number of states and slows down the operation of

the system. vi) For complex systems, we can split the control unit into several sections by using linked state machines. References:

1. Charles H ROTH, Jr.: Digital Systems Design Using VHDL; Thomson, Books/Cole, 2004 2. Richard S. Sandige: Modern Digital Design; McGRAW- HILL International Editions; 1990 3. J. Bhaskar: VHDL Primer; Pearson Education Asia; III Edition.

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