Sequential Logic

References:

Adapted from: Digital Integrated Circuits: A Design

Perspective, J. Rabaey, Prentice Hall © UCB

Principles of CMOS VLSI Design: A Systems Perspective,

N. H. E. Weste, K. Eshraghian, Addison Wesley

Clocked Systems: Finite State Machines

Combinational

Logic

Inputs Outputs

DQ

Clock or clocks

Current state bits Next state bits

Registers

Out = f(In, State)

Registers serve as storage element to store past history

Clocked Systems: Pipelined Systems

Logic

Inputs OutputsQD

Clock

QD QDLogic

Registers

Registers serve as storage element to capture the output

of each processing stage

Storage Mechanisms

• Positive feedback

– Connect one or more output signals back to the input

– Regenerative, signal can be held indefinitely, static

• Charge-based

– Use charge storage to store signal value

– Need refreshing to overcome charge leakage, dynamic

Positive Feedback: Two Cascaded Inverters

Vi1 Vo1= Vi2 Vo2

Vi2= Vo1

Bi-Stability and Meta-Stability

Vi1=Vo2

Vi2=

Vo

1

A

B

C

Vi1=Vo2

Vi2=

Vo

1

A

B

C

Gain larger than 1 amplifies

the deviation from C

Gain less than 1 reduces

the deviation from A

SR-Flip Flop

• NOR-based SR flip-flop, positive logic

• NAND-based SR flip-flop, negative logic

Schematic Logic Symbol Characteristic table

Schematic Logic Symbol Characteristic table

Forbidden state

JK- Flip Flop

Schematic Logic Symbol Characteristic table

• Clock input to synchronize changes in the output

logic states of flip-flops

• Forbidden state is eliminated,

• But repeated toggling when J = K = 1, need to keep

clock pulse small < propagation delay of FF

Other Flip-Flops

Toggle or T flip-flop Delay or D flip-flop

Race Problem

• A flip-flop is a latch if the gate is transparent while the

clock is high (low)

• Signal can raise around when is high

• Solutions:

– Reduce the pulse width of

– Master-slave and edge-triggered FFs

Master-Slave Flip-Flop

• Either master or slave FF is in the hold mode

• Pulse lengths of clock must be longer than

propagation delay of latches

• Asynchronous or synchronous inputs to initialize the

flip-flop states

One-Catching or Level-Sensitive

QM

QS

Propagation Delay Based Edge-Triggered

• Depend only on the value of

In just before the clock

transition

Edge Triggered Flip-Flop

Flip-Flop: Timing Definitions

Maximum Clock Frequency

Tttt setupcombppFF ,

Timing Metrics in Sequential Circuits

Register

D Q

CLK

Register

D Qcomb.

logic

Setup Time (tsu) is the time that the data inputs must be valid before the

clock transition

Hold Time (thold) is the time that the data inputs must be valid after the

clock transition

Propagation delays (treg,max, treg,min) – D input is copied to Q

tlogic,max, tlogic,min

tsu , thold,

treg,max, treg,min

Setup Time, Hold Time, and Propagation Delay

Data

Stable

T

tsutreg,maxtreg,max tlogic,max

thold

Data

StableData

Stable

,max log ,maxreg ic setupt t t T

log ,min ,minic reg holdt t t

t

t

t

D

CLK

Q

Register

D Q

CLK

Multiplexer Based Latches

A latch is a level-sensitive device

D

Q

CLK

0

1

D

Q

CLK

CLK

___

CLK

NMOS-only MUX based Latch

CLK

___

CLK

D QM

__

QM

Load of only 2 transistors to clock signals

Passes a degraded high voltage of VDD – VTn

Master Slave Edge-Triggered Register

D

QM

CLK

1

0

Q

CLK

0

1

Master

Slave

A register is an edge-triggered storage element

A Flip-Flop is any bistable component formed by the cross-coupling

of gates

Master Slave Edge-Triggered Register

D

QM

CLK

___

CLK

Q

CLK

CLK

___

CLK

___

CLK

T2

T1

T4

T3

I2

I1

I3

I4

I5I6

Setup Time: 3*tinv + ttx (I1T1 I3I2)

Propagation Delay: ttx + tinv (T3 I6)

Hold Time: 0

CMOS Clocked SR Flip-Flop

M1

M2

M3

M4

M5

M6

M7

M8

S R

QQ

VDD

S

R

Q

Q

Transistor Sizing of SR Flip-Flop

• Assume transistors of inverters are sized so that VM

is VDD/2, mobility ratio n/ p = 3

– (W/L)M1 = (W/L)M3 = 1.8/1.2

– (W/L)M2 = (W/L)M4 = 5.4/1.2

• To bring Q from 1 to 0, need to properly ratio the

sizes of pseudo-NMOS inverter (M7-M8)-M4

– VOL must be lower than VDD/2

82||

82

2

4,

2

78,DDDD

tpDDMpDDDD

tnDDMn

VVVVk

VVVVk

3478 )/()/()/( MM

n

p

M LWLWLW

)2.1/6.3()/(2)/(2)/( 3787 MMM LWLWLW

Flip-Flop: Transistor Sizing

Propagation Delay

Pseudo-

NMOS

inverter

(M5-M6)-M2

Inverter

M3-M4

Complementary CMOS SR Flip-Flop

M1

M2

M3

M4

M5

M6

M7

M8

S R

QQ

VDD

S R

M9

M10

M11

M12

Eliminates pseudo-NMOS inverters

Faster switching and smaller transient current

6-Transistor SR Flip-Flop

M1

M2

M3

M4

R

QQ

VDD

S

CMOS D Flip-Flop

DQ

Q

D

QQ

VDD

D

Master-Slave D Flip-Flop

QQ

D

VDD

D

Negative-Level Sensitive D Flip-Flop

DQ

Q

D

QQ

VDD

D

Master-Slave D Flip-Flop

D

VDD

D

QQ

CVSL-Style Master-Slave D-FF

Q Q

VDD

D

VDD

Charge-Based Storage

Pseudo-static Latch

In D

D

Layout of a D Flip-Flop

In

Q

In Q

Q

Q

Master-Slave Flip-Flop

InA

B

• Overlapping clocks can cause

– race conditions

– undefined signals

D

2 Phase Non-Overlapping Clocks

1

2

In

1

2

A

D

1

2

12pt

Asynchronous Setting

1

2

In

1

2

A

D

-Set

Dynamic Edge-Triggered Register

DN1

Q

(0, 0) overlap

(1,1) overlap

___

CLK

___

CLK

CLK

CLK

N2

C2C1

T1 T2I1 I2

___

CLK

CLK

(0,0) 1 1 2overlap T I Tt t t t

(1,1)hold overlapt t

2-phase Dynamic Flip-Flop

1

2

InA

2

D

1

Input

sampled

Output

Enabled

Flip-flop Insensitive to Clock Overlap

VDD VDD

In

CL1CL2

-section -section

C2MOS Latch or Clocked CMOS Latch

M1

M2

M3

M4

M5

M6

M7

M8X D

C2MOS Latch Avoids Race Conditions

VDD VDD

In

CL1CL2

M1

M2

M3

M5

M6

M7

X D

• Cascaded inverters: needs one pull-up followed by

one pull-down, or vice versa to propagate signal

• (1-1) overlap: Only the pull-down networks are active,

input signal cannot propagate to the output

• (0-0) overlap: only the pull-up networks are active

1 1

C2MOS Latch Avoids Race Conditions

• C2MOS latch is insensitive to overlap, as long a the

rise and fall times of clock edges are sufficiently small

Clocked CMOS Logic

• Replace the inverter in a C2MOS latch with a

complementary CMOS logic

VDD

CL1

PDN

PUN

M3

M4X

VDD

CL2

PDN

PUN

M7

M8

In1-3

In1-3

• Divide the computation into stages: Pipelining

Pipelining

RE

GR

EG

a

b

log

RE

G

RE

GR

EG

a

b

log

RE

G

regsetuplogicpregp tttT ,,,min

RE

G

RE

G

regsetuppabspadderpregppipe tttttT ,log,,,,min, ),,max(

Non-pipelined Pipelined

Pipelined Logic using C2MOS

In F G

NORA CMOS (NO-RAce logic)

Race free as long as all the logic functions F and G

between the latches are non-inverting

C1 C2 C3

out

VDDVDDVDD

Example

VDD VDD

In

VDD

Number of static inversion should be even

NORA CMOS -module

Logic

Precharge

Evaluate

Latch

Hold

Evaluate

= 0

= 1

NORA CMOS -module

Logic

Evaluate

Precharge

Latch

Evaluate

Hold

= 0

= 1

NORA Logic

• NORA data path consists of a chain of alternating

and modules

• Dynamic-logic rule: single 0 1 (1 0) transition for

dynamic n-block ( p-block)

• C2MOS rule:

– If dynamic blocks are present, even number of static

inversions between a latch and a dynamic block

– Otherwise, even number of static inversions between latches

• Static logic may glitch, best to keep all of them after

dynamic blocks

Doubled C2MOS Latches

Doubled n-C2MOS latch Doubled p-C2MOS latch

TSPC - True Single Phase Clock Logic

Including logic into

the latch

Inserting logic between

the latches

Simplified TSPC Latches

A and A’ do not have full logic swing

Master-Slave Flip-flops

Positive-edge triggered D-FF Negative-edge triggered D-FF

Master-Slave Simplified TSPC Flip-Flops

• Positive edge-triggered D flip-flops

• Reduces clock load

Further Simplication

Schmitt Trigger

• VTC with hysteresis

• Restores signal slopes

Noise Suppression using

Schmitt Trigger

Sharp low-to-high transition

CMOS Schmitt Trigger

Moves switching threshold

of first inverter

Sizing of M3 and M4

• VM+ = 3.5V

– M1 and M2 are in saturation; M4 is in triode region

• VM- = 1.5V

– M1 and M2 are in saturation; M3 is in triode region

2||||

2

22

4

22

21

MDDMDDtpDDtpMDD

tnM

VVVVVVkVVV

k

VVk

Schmitt Trigger: Simulated VTC

CMOS Schmitt Trigger

• In = 0, at steady state, VOut = VDD, VX =

VDD - Vtn

• In makes a 0 1 transition

– Saturated load inverter M1-M5 discharges

X

– M2 inactive until VX = Vin - Vtn

– Use Vin to approximate VM-

– M1-M5 in saturation

2521

22MDDtnM VV

kVV

k

Multivibrator Circuits

Bistable Multivibrator

Monostable Multivibrator

Astable Multivibrator

flip-flop, Schmitt Trigger

one-shot

oscillator

S

R

T

Transition-Triggered Monostable

DELAY

td

In

Outtd

Detects changes in the input signal

produces a pulse to initialize subsequent circuitry

e.g., address transition detection in static memories

Monostable Trigger (RC-based)

Astable Multivibrators (Oscillators)

T = 2 tp N

Voltage Controller Oscillator (VCO)

Schmitt trigger

restores signal slopes

Current starved inverter

Decrease Vcontr to reduce discharge current

increase propagation delay of inverter

decreases oscillating frequency

(quadratic dependency)

Relaxation Oscillator

T = 2 (ln 3) RC