EE134 1

Digital Integrated Circuit (IC) Layout and Digital Integrated Circuit (IC) Layout and Design Design -- Week 4, Lecture 8Week 4, Lecture 8

! http://www.ee.ucr.edu/~rlake/EE134.html! HW 1 due next Tues.

EE134 2

ReadingReading

" Week 1 - Read Chapter 1 of text." Week 2 - Read Chapter 2 of text." Week 3 - Read Chapter 3 of text." Week 4 - Read Chapter 5 of text.

EE134 3

Review/FinishReview/Finish" Inverter (Ch. 5)

! Voltage transfer curve (VTC)! Switching Point

" Inverter (Ch. 5)! Capacitance! Switching delay time

NewNew

EE134 4

Simple Model versus SPICE Simple Model versus SPICE

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5x 10

-4

VDS (V)

I D(A

)

VelocitySaturated

Linear

Saturated

VDSAT=VGT

VDS=VDSAT

VDS=VGT

EE134 5

A Unified Model for Manual AnalysisA Unified Model for Manual Analysis

EE134 6

Transistor Model Transistor Model for Manual Analysisfor Manual Analysis

I keep all signs positive for PMOS and use VSG, VSD, ISD.

EE134

Voltage TransferVoltage TransferCharacteristicCharacteristic

EE134 8

CMOS Inverter Load CharacteristicsCMOS Inverter Load Characteristics

IDn

Vout

Vin = 2.5

Vin = 2

Vin = 1.5

Vin = 0

Vin = 0.5

Vin = 1

NMOS

Vin = 0

Vin = 0.5

Vin = 1Vin = 1.5

Vin = 2

Vin = 2.5

Vin = 1Vin = 1.5

PMOS

EE134 9

CMOS Inverter VTCCMOS Inverter VTC

Vout

Vin0.5 1 1.5 2 2.5

0.5

11.

52

2.5

NMOS resPMOS off

NMOS satPMOS sat

NMOS offPMOS res

NMOS satPMOS res

NMOS resPMOS sat

EE134 10

Switching Threshold as a function of Switching Threshold as a function of Transistor RatioTransistor Ratio

100

101

0.8

0.9

1

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

MV

(V)

W p/W

n

EE134 11

Determining VDetermining VIHIH and Vand VILIL

VOH

VOL

Vin

Vout

VM

VIL VIH

A simplified approach

Vout

Vin0.5 1 1.5 2 2.5

0.5

11.

52

2.5

NMOS resPMOS off

NMOS satPMOS sat

NMOS offPMOS res

NMOS s atPMOS res

NMOS resPMOS sat

EE134 12

Inverter GainInverter Gain

0 0.5 1 1.5 2 2.5-18

-16

-14

-12

-10

-8

-6

-4

-2

0

Vin (V)

gain

EE134 13

Gain as a function of VDDGain as a function of VDD

0 0.05 0.1 0.15 0.20

0.05

0.1

0.15

0.2

Vin (V)

Vou

t (V)

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5

Vin (V)

Vou

t(V)

Gain=-1

EE134 14

Impact of Process VariationsImpact of Process Variations

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5

Vin (V)

V out(V

)

Good PMOSBad NMOS

Good NMOSBad PMOS

Nominal

EE134 15

CMOS InverterCMOS InverterFirstFirst--Order DC AnalysisOrder DC Analysis

VOL = 0VOH = VDD

VM = f(Rn, Rp)

VDD VDD

Vin = VDD Vin = 0

VoutVout

Rn

Rp

EE134 16

CMOS Inverter: Transient ResponseCMOS Inverter: Transient Response

tpHL = f(Ron.CL)= 0.69 Rn CL

V outVout

R n

R p

V DDV DD

V in = V DDV in = 0

(a) Low-to-high (b) High-to-low

CLCL