digital integrated circuits a design...

Digital IC Introduction

Digital Integrated Circuits

A Design Perspective Designing Combinational

Logic Circuits Fuyuzhuo

School of Microelectronics,SJTU �

Digital IC 2

agenda •  Static CMOS design •  Ratioed logic design___Pseudo NMOS •  Pass transistor design •  Dynamic logic

Digital IC 3

Static CMOS logic •  Static CMOS review •  Static CMOS layout tricky •  Static CMOS VTC data dependency •  CMOS propagate delay definitions •  RC model •  Static CMOS size •  fan-in/fan-out tech. •  Logic effort •  CMOS power analysis

Digital IC 4

Static CMOS Circuit � •  At every point in time (except during the switching

transients) each gate output is connected to either VDD or VSS via a low-resistive path

•  The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods)

•  This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes

Digital IC

VTC is Data-Dependent

q  The threshold voltage of M2 is higher than M1 due to the body effect (γ)

VTn2 = VTn0 + γ(√(|2φF| + Vint) - √|2φF|) since VSB of M2 is not zero (when VB = 0) due to the presence of Cint

VTn1 = VTn0

A

B

F= A • B

A B

M1

M2

M3 M4

Cint

VGS1 = VB

VGS2 = VA –VDS1

D

D S

S 0

1

2

3

0 1 2

A,B: 0 -> 1B=1, A:0 -> 1A=1, B:0->1

0.5µ/0.25µ NMOS 0.5µ /0.25µ PMOS

weaker PUN

Digital IC 6

Delay Dependence on Input Patterns

-0.5

0

0.5

1

1.5

2

2.5

3

0 100 200 300 400

A=B=1→0

A=1, B=1→0

A=1 →0, B=1

time [ps]

Volta

ge [V

]

Input Data Pattern

Delay (psec)

A=B=0→1 69(max)

A=1, B=0→1 62

A= 0→1, B=1 50

A=B=1→0 35(min)

A=1, B=1→0 76

A= 1→0, B=1 57

NMOS = 0.5µm/0.25 µm PMOS = 0.75µm/0.25 µm CL = 100 fF

共享电容充电

共享电容放电

Digital IC 7

CMOS Properties •  Full rail-to-rail swing; high noise margins •  Logic levels not dependent upon the relative

device sizes; ratioless •  Always a path to Vdd or Gnd in steady state;

low output impedance •  Extremely high input resistance; nearly zero

steady-state input current •  No direct path steady state between power

and ground; no static power dissipation •  Propagation delay function of load

capacitance and resistance of transistors

Digital IC 8

Static CMOS logic •  CMOS static characteristic •  CMOS propagate delay •  Large fan-in technology •  Logic effort •  CMOS power analysis

Digital IC Slide 9

Delay Definitions •  tpdr: rising propagation delay

•  From input to rising output crossing VDD/2 •  tpdf: falling propagation delay

•  From input to falling output crossing VDD/2 •  tpd: average propagation delay(max-time)

•  tpd = (tpdr + tpdf)/2 •  tr: rise time

•  From output crossing 0.1 VDD to 0.9 VDD •  tf: fall time

•  From output crossing 0.9 VDD to 0.1 VDD

Digital IC Slide 10

Delay Definitions •  tcdr: rising contamination delay

•  Minimum time from input to rising output crossing VDD/2

•  tcdf: falling contamination delay •  Minimum time from input to falling output crossing

VDD/2 •  tcd: average contamination delay(min-time)

•  Minimum time from input crossing 50% to the output crossing 50%

•  tpd = (tcdr + tcdf)/2

Digital IC Slide 11

Simulated Inverter Delay •  Solving differential equations by hand is too hard •  SPICE simulator solves the equations numerically

•  Uses more accurate I-V models too! •  But simulations take time to write

(V)

0.0

0.5

1.0

1.5

2.0

t(s)0.0 200p 400p 600p 800p 1n

tpdf

= 66ps tpdr

= 83psVinVout

Digital IC Slide 12

Delay Estimation •  We would like to be able to easily estimate delay

•  Not as accurate as simulation •  But easier to ask “What if?”

•  The step response usually looks like a 1st order RC response with a decaying exponential.

•  Use RC delay models to estimate delay •  C = total capacitance on output node •  Use effective resistance R •  So that tpd = RC

•  Characterize transistors by finding their effective R •  Depends on average current as gate switches

Digital IC 13

Input Pattern Effects on Delay

•  Delay is dependent on the pattern of inputs

•  Low to high transition •  both inputs go low

• delay is 0.69 Rp/2 CL •  one input goes low

• delay is 0.69 Rp CL •  High to low transition

•  both inputs go high • delay is 0.69 2Rn CL

CL

B

Rn

A

Rp

B

Rp

A

Rn Cint

Digital IC Slide 14

Elmore Delay •  ON transistors look like resistors •  Pullup or pulldown network modeled as RC ladder •  Elmore delay of RC ladder

R1 R2 R3 RN

C1 C2 C3 CN

( ) ( )nodes

1 1 1 2 2 1 2... ...

pd i to source ii

N N

t R C

RC R R C R R R C

− −≈

= + + + + + + +

∑

Digital IC Slide 15

RC Delay Models •  Use equivalent circuits for MOS transistors

•  Ideal switch + capacitance and ON resistance •  Unit nMOS has resistance R, capacitance C •  Unit pMOS has resistance 2R, capacitance C

•  Capacitance proportional to width •  Resistance inversely proportional to width

kgs

dg

s

d

kCkC

kCR/k

kgs

dg

s

d

kC

kC

kC

2R/k

Digital IC Slide 16

3-input NAND Caps •  Annotate the 3-input NAND gate with gate and diffusion

capacitance.

9C

3C

3C3

3

3

222

5C5C

5C

Digital IC Slide 17

Example: 2-input NAND •  Estimate rising and falling propagation delays of a 2-

input NAND driving h identical gates.

h copies6C

2C2

2

224hC

B

Ax

Y

R

(6+4h)CY RChtpdr )46(2ln +=

Digital IC Slide 18

Example: 2-input NAND •  Estimate rising and falling propagation delays of a 2-

input NAND driving h identical gates.

h copies6C

2C2

2

224hC

B

Ax

Y

(6+4h)C2CR/2

R/2x Y

RCh

RRChRCtpdf

)47(2ln

)22

]()46[(2

22ln

+=⎭⎬⎫

⎩⎨⎧ +++=

Digital IC Slide 19

Delay Components •  Delay has two parts

•  Parasitic delay •  6 or 7 RC •  Independent of load

•  Effort delay •  4h RC •  Proportional to load capacitance

Digital IC Slide 20

Contamination Delay •  Best-case (contamination) delay can be substantially

less than propagation delay. •  Ex: If both inputs fall simultaneously

6C

2C2

2

224hC

B

Ax

Y

R

(6+4h)CYR

( )3 2cdrt h RC= +


Layout methodology �

Digital IC Slide 22

Layout Comparison •  Which layout is better?

AVDD

GND

B

Y

AVDD

GND

B

Y

Digital IC

7C

3C

3C3

3

3

222

3C

2C2C

3C3C

IsolatedContactedDiffusionMerged

UncontactedDiffusion

SharedContactedDiffusion

•  we assumed contacted diffusion on every s / d. •  Good layout minimizes diffusion area •  Ex: NAND3 layout shares one diffusion contact

•  Reduces output capacitance by 2C •  Merged uncontacted diffusion might help too

Slide 23

Diffusion Capacitance

Digital IC

Standard Cell Layout Methodology

signals

Routing channel

VDD

GND

What logic function is this?

Digital IC

OAI21 Logic Graph

C

A B

X = !(C • (A + B))

B

A C

i

j

j

VDD X

X

i

GND

A B

C

PUN

PDN A B C

Digital IC

Two Stick Layouts of !(C • (A + B))

A B C

X

VDD

GND

X

C A B

VDD

GND

uninterrupted diffusion strip

Digital IC

OAI22 Logic Graph

C

A B

X = !((A+B)•(C+D))

B

A

D

VDD X

X

GND

A B

C

PUN

PDN

C

D

D

A B C D

Digital IC

OAI22 Layout B A D

VDD

GND

C

X

Some functions have no consistent Euler path like

x = !(a + bc + de) (but x = !(bc + a + de) does!)


Transistor size �

Digital IC 30

Transistor Sizing

CL

B

Rn

A

Rp

B

Rp

A

Rn Cint

B

Rp

A

Rp

A

Rn

B

Rn CL

Cint 2 2

2 2

1 1

4 4

Digital IC 31

Transistor Sizing a Complex CMOS Gate

OUT = D + A • (B + C)

D A

B C

D

A B

C

1

2

2 2

4

4 8

8

6

3 6

6

Digital IC 32

Fan-In Considerations

D C B A

D

C

B

A CL

C3

C2

C1

Distributed RC model (Elmore delay) tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)

Propagation delay deteriorates rapidly as a function of fan-in quadratically in the worst case

Digital IC 33

tp (NAND)as a function of fan-in

tpLH

t p (p

sec)

fan-in

Gates with a fan-in greater than 4 should be avoided

0

250

500

750

1000

1250

2 4 6 8 10 12 14 16

tpHL

quadratic

linear

tp

Digital IC 34

tp as a function of fan-out

2 4 6 8 10 12 14 16

tpNOR2

t p (p

sec)

eff. fan-out

tpNAND2

tpINV

All gates have the same drive current

Slope is a function of “driving strength”

Digital IC

tp as a function of fan-In and fan-out

•  Fan-in: quadratic due to increasing resistance and capacitance

•  Fan-out: each additional fan-out gate adds two gate capacitances to CL

35

tp = a1FI + a2FI2 + a3FO

Digital IC 36

Static CMOS logic •  CMOS static characteristic •  CMOS propagate delay •  Large fan-in technology •  Logic effort •  CMOS power analysis

Digital IC

How to choose design techniques for large fan-in/fan-out �

•  Problems we are facing •  Larger parasitic capacitor, larger load to the

preceding gate •  Load is dominated by fan-out

•  Solution •  Progressive transistor sizing •  Transistor ordering •  Alternative logic structures •  Isolating fan-in from fan-out using buffer

insertion 37

Digital IC 38

Transistor ordering

C2

C1 In1

In2

In3

M1

M2

M3 CL

C2

C1 In3

In2

In1

M1

M2

M3 CL

critical path critical path

charged 1

0→1 charged

charged 1

delay determined by time to discharge CL, C1 and C2

delay determined by time to discharge CL

1

1

0→1 charged

discharged discharged

Digital IC 39

Progressive sizing •  Distributed RC line

•  M1 > M2 > M3 > … > MN

•  the closest to the output is the smallest

•  Can reduce delay by more than 20%; decreasing gains as technology shrinks

Digital IC 40

Alternative logic structures

F = ABCDEFGH

Digital IC 41

Isolating fan-in from fan-out using buffer insertion

CL CL

Large fan-in

Large fan-out isolating

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