digital integrated circuits a design perspectivesantos/ine5442/slides/aulas53-54.pdfdigital...

Digital Integrated Digital Integrated

CircuitsCircuits

A Design PerspectiveA Design Perspective

Semiconductor MemoriesSemiconductor Memories

Reference: Digital Integrated Circuits, 2nd edition, Jan M. Rabaey, AnanthaChandrakasan and Borivoje Nikolic

Disclaimer: slides adapted for INE5442/EEL7312 by José L. Güntzelfrom the book´s companion slides madeavailable by the authors.

© Digital Integrated Circuits2nd Semiconductor MemoriesSlide 2

Lecture SummaryLecture Summary

� Memory Classification

� Memory Architectures

� The Memory Core (ROM Memories)


Memory Timing: DefinitionsMemory Timing: Definitions

Write cycleRead access Read access

Read cycle

Write access

Data written

Data valid

DATA

WRITE

READ


Semiconductor Memory ClassificationSemiconductor Memory Classification

Read-Write MemoryNon-Volatile

Read-Write

Memory

Read-Only Memory

EPROM

E2PROM

FLASH

Random

Access

Non-Random

Access

SRAM

DRAM

Mask-Programmed

Programmable (PROM)

FIFO

Shift Register

CAM

LIFO


Memory Architecture: DecodersMemory Architecture: Decoders

Word 0

Word 1

Word 2

Word N2 2

Word N2 1

Storagecell

M bits M bits

N

w o r d s

S0

S1

S2

SN− 2

A 0

A 1

A K– 1

K = log2N

SN– 1

Word 0

Word 1

Word 2

Word N2 2

Word N2 1

Storagecell

S0

Input-Output(M bits)

Intuitive architecture for N x M memoryToo many select signals:

N words == N select signalsK = log2N

Decoder reduces the number of select signals


D e c o d e r


Ro

w D

eco

de

r

Bit line2L 2 K

Word line

AK

AK1 1

AL 2 1

A0

M.2K

AK2 1

Sense amplifiers / Drivers

Column decoder


Storage cell

ArrayArray--Structured Memory ArchitectureStructured Memory Architecture

Problem: ASPECT RATIO or HEIGHT >> WIDTH

Amplify swing torail-to-rail amplitude

Selects appropriateword–

–

–

+


Hierarchical Memory ArchitectureHierarchical Memory Architecture

Advantages:Advantages:

1. Shorter wires within blocks1. Shorter wires within blocks2. Block address activates only 1 block => power savings2. Block address activates only 1 block => power savings

Globalamplifier/driver

Controlcircuitry

Global data bus

Block selector

Block 0

Rowaddress

Columnaddress

Blockaddress

Block i Block P 2 1

I/O

–


Block Diagram of 4 Block Diagram of 4 MbitMbit SRAMSRAM

Subglobalrow decoder

Global row decoder

Subglobalrow decoder

Block 30

Block 31

128 K Array Block 0

Block 1

Clockgenerator

CS, WEbuffer

I/Obuffer

Y-addressbuffer

X-addressbuffer

x1/x4controller

Z-addressbuffer

X-addressbuffer

Predecoder and block selectorBit line load

Transfer gate

Column decoder

Sense amplifier and write driver

Local row decoder

[Hirose90]

32 128-bit

blocks

Local row decoder

Sub-global row decoder

Global rowdecoder


ContentsContents--Addressable MemoryAddressable Memory

A d d r e s s D e c o d e r

I / O B u f f e r s

C o m m a n d s

2

9

V a l i d i t y B i t s

P r i o r i t y E n c o d e r

A d d r e s s D e c o d e r

I / O B u f f e r s

C o m m a n d s

2

9

V a l i d i t y B i t s

P r i o r i t y E n c o d e r

Ad

dre

ss D

eco

de

r

Data (64 bits)

I/O

Bu

ffe

rs

Comparand

CAM Array2

9 words 3 64 bits

Mask

Control Logic R/W Address (9 bits)

Co

mm

an

ds

29 V

alid

ity B

its

Prio

rity

En

co

de

r

x


Memory Timing: ApproachesMemory Timing: Approaches

DRAM TimingMultiplexed Addressing

SRAM TimingSelf-timed

Addressbus

RAS

RAS-CAS timing

Row Address

AddressBus

Address transitioninitiates memory operation

Address

Column Address

CAS

DRAM external timing signals:

RAS= Row Address Strobe

CAS=Column Address Strobe

SRAM: no external timing signals!


ReadRead--Only Memory CellsOnly Memory Cells

WL

BL

WL

BL

1WL

BL

WL

BL

WL

BL

0

VDD

WL

BL

GND

Diode ROM MOS ROM 1 MOS ROM 2

MOS ROM1: BL must be resistively clamped to ground

MOS ROM2: BL must be resistively clamped to Vdd


MOS OR ROMMOS OR ROM

WL[0]

VDD

BL[0]

WL[1]

WL[2]

WL[3]

Vbias

BL[1]

Pull-down loads

BL[2] BL[3]

VDD

To reduce areaoverhead,

supply voltage

lines are shared

betweenadjacent rows

Data read


Data read

MOS NOR ROMMOS NOR ROM

WL[0]

GND

BL [0]

WL [1]

WL [2]

WL [3]

VDD

BL [1]

Pull-up devices

BL [2] BL [3]

GND

Each row is a pseudo-NMOS (WLs are the inputs)!


MOS NOR ROM LayoutMOS NOR ROM Layout

Programmming using the

Active Layer Only

Polysilicon

Metal1

Diffusion

Metal1 on Diffusion

Cell (9.5λ x 7λ)

WL[0]

WL[1]

WL[2]

WL[3]

GND]

GND]


MOS NOR ROM LayoutMOS NOR ROM Layout

Polysilicon

Metal1

Diffusion

Metal1 on Diffusion

Cell (11λ x 7λ)

Programmming using

the Contact Layer Only

WL[0]

WL[1]

WL[2]

WL[3]

GND]

GND]


MOS NAND ROMMOS NAND ROM

All word lines high by default with exception of selected row

WL [0]

WL [1]

WL [2]

WL [3]

VDD

Pull-up devices

BL [3]BL [2]BL [1]BL [0]


MOS NAND ROM LayoutMOS NAND ROM Layout

No contact to VDD or GND necessary;

Loss in performance compared to NOR ROM

drastically reduced cell size

Polysilicon

Diffusion

Metal1 on Diffusion

Cell (8λ x 7λ)

Programmming using

the Metal-1 Layer Only


NAND ROM LayoutNAND ROM Layout

Cell (5λ x 6λ)

Polysilicon

Threshold-altering

implant

Metal1 on Diffusion

Programmming using

Implants Only


Equivalent Transient Model for MOS NOR ROMEquivalent Transient Model for MOS NOR ROM

� Word line parasitics� Wire capacitance and gate capacitance� Wire resistance (polysilicon)

� Bit line parasitics� Resistance not dominant (metal)� Drain and Gate-Drain capacitance

Model for NOR ROM VDD

Cbit

rword

cword

WL

BL


Equivalent Transient Model for MOS NAND ROMEquivalent Transient Model for MOS NAND ROM

� Word line parasitics� Similar to NOR ROM

� Bit line parasitics� Resistance of cascaded transistors dominates� Drain/Source and complete gate capacitance

Model for NAND ROMVDD

CL

rword

cword

cbit

rbit

WL

BL


Decreasing Word Line DelayDecreasing Word Line Delay

Metal bypass

Polysilicon word lineK cells

Polysilicon word lineWL

Driver

(b) Using a metal bypass

(a) Driving the word line from both sides

Metal word line

WL

(c) Use silicides


PrechargedPrecharged MOS NOR ROMMOS NOR ROM

PMOS precharge device can be made as large as necessary,but clock driver becomes harder to design.

WL [0]

GND

BL [0]

WL [1]

WL [2]

WL [3]

VDD

BL [1]

Precharge devices

BL [2] BL [3]

GND

pref

digital integrated circuits a design perspectivesantos/ine5442/slides/aulas53-54.pdfdigital...

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