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EE141© Digital Integrated Circuits2nd Manufacturing1

Digital Integrated

CircuitsA Design Perspective

Manufacturing

Process

Jan M. Rabaey

Anantha Chandrakasan

Borivoje Nikolic

July 30, 2002


CMOS Process


A Modern CMOS Process

p-well n-well

p+

p-epi

SiO2

AlCu

poly

n+

SiO2

p+

gate-oxide

Tungsten

TiSi2

Dual-Well Trench-Isolated CMOS Process


Circuit Under Design

VDD VDD

VinVout

M1

M2

M3

M4

Vout2


Its Layout View


The Manufacturing Process

For a great tour through the IC manufacturing process

and its different steps, check

http://www.fullman.com/semiconductors/semiconductors.html


oxidation

opticalmask

processstep

photoresist coatingphotoresistremoval (ashing)

spin, rinse, dryacid etch

photoresist

stepper exposure

development

Typical operations in a single

photolithographic cycle (from [Fullman]).

Photo-Lithographic Process


Patterning of SiO2

Si-substrate

Si-substrate Si-substrate

(a) Silicon base material

(b) After oxidation and depositionof negative photoresist

(c) Stepper exposure

Photoresist

SiO2

UV-light

Patternedoptical mask

Exposed resist

SiO2

Si-substrate

Si-substrate

Si-substrate

SiO2

SiO2

(d) After development and etching of resist,chemical or plasma etch of SiO

2

(e) After etching

(f) Final result after removal of resist

Hardened resist

Hardened resist

Chemical or plasmaetch


CMOS Process at a Glance

Define active areas

Etch and fill trenches

Implant well regions

Deposit and patternpolysilicon layer

Implant source and drainregions and substrate contacts

Create contact and via windowsDeposit and pattern metal layers


CMOS Process Walk-Through

p+

p-epi (a) Base material: p+ substrate with p-epi layer

p+

(c) After plasma etch of insulatingtrenches using the inverse of the active area mask

p+

p-epiSiO

2

3SiN

4

(b) After deposition of gate-oxide andsacrificial nitride (acts as abuffer layer)


CMOS Process Walk-ThroughSiO

2

(d) After trench filling, CMPplanarization, and removal of sacrificial nitride

(e) After n-well and V

Tpadjust implants

n

(f) After p-well andV

Tnadjust implants

p



(g) After polysilicon depositionand etch

poly(silicon)

(h) After n+ source/drain andp+source/drain implants. These

p+n+

steps also dope the polysilicon.

(i) After deposition of SiO2insulator and contact hole etch.

SiO2



(j) After deposition and patterning of first Al layer.

Al

(k) After deposition of SiO2insulator, etching of via’s,

deposition and patterning ofsecond layer of Al.

AlSiO

2


Advanced Metallization


Design Rules


3D Perspective

Polysilicon Aluminum


Design Rules

Interface between designer and process

engineer

Guidelines for constructing process masks

Unit dimension: Minimum line width

scalable design rules: lambda parameter

absolute dimensions (micron rules)


CMOS Process Layers

Layer

Polysilicon

Metal1

Metal2

Contact To Poly

Contact To Diffusion

Via

Well (p,n)

Active Area (n+,p+)

Color Representation

Yellow

Green

Red

Blue

Magenta

Black

Black

Black

Select (p+,n+) Green


Layers in 0.25 mm CMOS process


Intra-Layer Design Rules

Metal24

3

10

90

Well

Active3

3

Polysilicon

2

2

Different PotentialSame Potential

Metal1


Transistor Layout

1

2

5

3

Tra

nsi

sto

r


Vias and Contacts

1

2

1

Via

Metal toPoly ContactMetal to

Active Contact

1

2

5

4

3 2

2


Select Layer

1

3 3

2

2

2

WellSubstrate

Select3

5


CMOS Inverter Layout

A A’

np-substrate Field

Oxidep+n+

In

Out

GND VDD

(a) Layout

(b) Cross-Section along A-A’

A A’


Layout Editor


Design Rule Checker

poly_not_fet to all_diff minimum spacing = 0.14 um.


Sticks Diagram

1

3

In Out

VDD

GND

Stick diagram of inverter

• Dimensionless layout entities

• Only topology is important

• Final layout generated by

“compaction” program


Packaging


Packaging Requirements

Electrical: Low parasitics

Mechanical: Reliable and robust

Thermal: Efficient heat removal

Economical: Cheap


Bonding Techniques

Lead Frame

Substrate

Die

Pad

Wire Bonding


Tape-Automated Bonding (TAB)

(a) Polymer Tape with imprinted

(b) Die attachment using solder bumps.

wiring pattern.

Substrate

Die

Solder BumpFilm + Pattern

Sprocket

hole

Polymer film

Lead

frame

Test

pads


Flip-Chip Bonding

Solder bumps

Substrate

Die

Interconnect

layers


Package-to-Board Interconnect

(a) Through-Hole Mounting (b) Surface Mount


Package Types


Package Parameters


Multi-Chip Modules

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