digital integrated circuits© prentice hall 1995 devices the mos transistor

Digital Integrated Circuits © Prentice Hall 1995DevicesDevices

The MOS Transistor

n+n+

p-substrate

Field-Oxyde

(SiO2)

p+ stopper

Polysilicon

Gate Oxyde

DrainSource

Gate

Bulk Contact

CROSS-SECTION of NMOS Transistor


Cross-Section of CMOS Technology


MOS transistors Types and Symbols

D

S

G

D

S

G

G

S

D D

S

G

NMOS Enhancement NMOS

PMOS

Depletion

Enhancement

B

NMOS withBulk Contact


Threshold Voltage: Concept

n+n+

p-substrate

DSG

B

VGS

+

-

Depletion

Region

n-channel


Current-Voltage Relations

n+n+

p-substrate

D

SG

B

VGS

xL

V(x) +–

VDS

ID

MOS transistor and its bias conditions


Current-Voltage Relations


Transistor in Saturation

n+n+

S

G

VGS

D

VDS > VGS - VT

VGS - VT+-


I-V Relation

0.0 1.0 2.0 3.0 4.0 5.0

VDS (V)

1

2

I D (

mA

)

0.0 1.0 2.0 3.0VGS (V)

0.010

0.020

÷ I

D

VT

SubthresholdCurrent

Triode Saturation

VGS = 5V

VGS = 3V

VGS = 4V

VGS = 2V

VGS = 1V

(a) ID as a function of VDS (b) ID as a function of VGS

(for VDS = 5V).

Sq

ua

re D

ep

end

en

ce

VDS = VGS-VT

NMOS Enhancement Transistor: W = 100 m, L = 20 m


A model for manual analysis


The Sub-Micron MOS Transistor

• Threshold Variations

• Parasitic Resistances

• Velocity Sauturation and Mobility Degradation

• Subthreshold Conduction

• Latchup


Threshold Variations

VT

L

Long-channel threshold Low VDS threshold

Threshold as a function of the length (for low VDS)

Drain-induced barrier lowering (for low L)

VDS

VT


Parasitic Resistances

W

LD

Drain

Draincontact

Polysilicon gate

DS

G

RS RD

VGS,eff


Velocity Saturation (1)

EV/m)Esat

n (c

m/s

ec)

sat = 107

Constant mobility (slope = )

constant velocity

EtV/m)

n (c

m2 /V

s)

n0

(b) Mobility degradation(a) Velocity saturation

0

700

250


Velocity Saturation (2)

VDS (V)

I D (

mA

)

Lin

ea

r D

ep

en

de

nc

e

VGS = 5

VGS = 4

VGS = 3

VGS = 2

VGS = 1

0.0 1.0 2.0 3.0 4.0 5.0

0.5

1.0

1.5

(a) ID as a function of VDS (b) ID as a function of VGS(for VDS = 5 V).

0.0 1.0 2.0 3.0VGS (V)

0

0.5

I D (

mA

)

Linear Dependence on VGS


Sub-Threshold Conduction

0.0 1.0 2.0 3.0VGS (V)

10 12

10 10

10 8

10 6

10 4

10 2

ln(I

D)

(A)

Subthreshold exponential region

Linear region

VT


Latchup

(a) Origin of latchup (b) Equivalent circuit

VDD

Rpsubs

Rnwell p-source

n-source

n+ n+p+ p+ p+ n+

p-substrateRpsubs

Rnwell

VDD

n-well


SPICE MODELS

Level 1: Long Channel Equations - Very Simple

Level 2: Physical Model - Includes VelocitySaturation and Threshold Variations

Level 3: Semi-Emperical - Based on curve fittingto measured devices

Level 4 (BSIM): Emperical - Simple and Popular


MAIN MOS SPICE PARAMETERS


SPICE Transistors Parameters


SPICE Parameters for Parasitics


Technology Evolution


The CMOS Inverter: A First Glance

VDD

Vin Vout

CL


VTC of Real Inverter

0.0 1.0 2.0 3.0 4.0 5.0Vin (V)

1.0

2.0

3.0

4.0

5.0

Vo

ut (V

)

VMNMH

NML


Dynamic Behavior of MOS Transistor

DS

G

B

CGDCGS

CSB CDBCGB


Delay Definitions

tpHL

tpLH

t

t

Vin

Vout

50%

50%

tr

10%

90%

tf

VDD VDD

VinVout

M1

M2

M3

M4Cdb2

Cdb1

Cgd12

Cw

Cg4

Cg3

Vout2

Fanout

Interconnect

VoutVin

CL

SimplifiedModel


CMOS Inverters

Polysilicon

InOut

Metal1

VDD

GND

PMOS

NMOS

1.2 m=2


Using Cascaded Buffers

C2C1

Ci

CL

1 u u2 uN-1

In Out

uopt = e


COMBINATIONAL LOGIC


Static CMOS

VDD

VSS

PUN

PDN

In1

In2

In3

F = G

In1

In2

In3

PUN and PDN are Dual Networks

PMOS Only

NMOS Only


Example Gate: NAND


4-input NAND Gate

Out

In1 In2 In3 In4

In3

In1

In2

In4

In1 In2 In3 In4

VDD

Out

GND

VDD

In1 In2 In3 In4

Vdd

GND

Out


Where Does Power Go in CMOS?

• Dynamic Power Consumption

• Short Circuit Currents

• Leakage

Charging and Discharging Capacitors

Short Circuit Path between Supply Rails during Switching

Leaking diodes and transistors


SEQUENTIAL LOGIC


Master-Slave Flip-Flop

S

R

Q

Q Q

QS

R

Q

Q

J

K

MASTER SLAVE

QJ

K Q

PRESET

CLEAR

SI

RI


The Ellmore Delay


The Clock Skew Problem

CL1 R1 CL2 R2 CL3 R3In Out

t’ t’’ t’’’

tl,min

tl,max

tr,min

tr,max

ti

Clock Edge Timing Depends upon Position

Clock Rates as High as 500 Mhz in CMOS!

digital integrated circuits© prentice hall 1995 devices the mos transistor

Documents

digital integrated circuits

devices latchup slide

devices transistor

saturation slide

devices static cmos

nand slide

devices sequential logic

concept slide