digital integrated circuits - universidade federal de ...j.guntzel/ine5442/csi_aulas37-40.pdf ·...

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1© Digital Integrated Circuits2nd

Arithmetic Circuits

Digital Integrated Digital Integrated

CircuitsCircuitsA Design PerspectiveA Design Perspective

Arithmetic CircuitsArithmetic CircuitsReference: Digital Integrated Circuits, 2nd edition, Jan M. Rabaey, AnanthaChandrakasan and Borivoje Nikolic

Disclaimer: slides adapted for INE5442/EEL7312 by José L. Güntzelfrom the book´s companion slides madeavailable by the authors.

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Arithmetic Circuits

A Generic Digital ProcessorA Generic Digital Processor

MEM ORY

DATAPATH

CONTROL

INP

UT

-OU

TP

UT

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Arithmetic Circuits

Building Blocks for Digital ArchitecturesBuilding Blocks for Digital Architectures

Arithmetic unit

- Bit-sliced datapath (adder, multiplier, shifter, comparator, etc.)

Memory

- RAM, ROM, Buffers, Shift registers

Control

- Finite state machine (PLA, random logic.)

- Counters

Interconnect

- Switches

- Arbiters

- Bus

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Arithmetic Circuits

An Intel MicroprocessorAn Intel Microprocessor

9-1

Mu

x9

-1 M

ux

5-1

Mu

x2

-1 M

ux

ck1

CARRYGEN

SUMGEN

+ LU

1000um

b

s0

s1

g64

sum sumb

LU : Logical

Unit

SU

MS

EL

a

to Cache

node1

RE

G

Itanium has 6 integer execution units like this

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Arithmetic Circuits

BitBit--Sliced DesignSliced Design

Bit 3

Bit 2

Bit 1

Bit 0

Regis

ter

Ad

der

Sh

ifte

r

Mu

ltip

lexer

ControlD

ata

-In

Data

-Ou

t

Tile identical processing elements

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Arithmetic Circuits

BitBit--Sliced Sliced DatapathDatapath

Adder stage 1

Wiring

Adder stage 2

Wiring

Adder stage 3

Bit s

lice 0

Bit s

lice 2

Bit s

lice 1

Bit s

lice

63

Sum Select

Shifter

Multiplexers

Loopback B

us

From register files / Cache / Bypass

To register files / Cache

Loopback B

us

Loopback B

us

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Arithmetic Circuits

Itanium Integer Itanium Integer DatapathDatapath

Fetzer, Orton, ISSCC’02

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Arithmetic Circuits

AddersAdders

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Arithmetic Circuits

FullFull--AdderAdderA B

Cout

Sum

Cin Fulladder

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Arithmetic Circuits

The Binary AdderThe Binary Adder

S A B Ci

⊕ ⊕⊕ ⊕⊕ ⊕⊕ ⊕=

A= BCi ABCi ABCi

ABCi

+ + +

Co

AB BCi

ACi

+ +=

A B

Cout

Sum

Cin Fulladder

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Arithmetic Circuits

Express Sum and Carry as a function of P, G, DExpress Sum and Carry as a function of P, G, D

Define 3 new variable which ONLY depend on A, B

Generate (G) = AB

Propagate (P) = A ⊕ B

Delete = A B

Can also derive expressions for S and Co based on D and P

Propagate (P) = A ++++ B

Note that we will be sometimes using an alternate definition for

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Arithmetic Circuits

The RippleThe Ripple--Carry AdderCarry Adder

Worst case delay linear with the number of bits

Goal: Make the fastest possible carry path circuit

FA FA FA FA

A0 B0

S0

A1 B1

S1

A2 B2

S2

A3 B3

S3

Ci,0 Co,0

(= Ci,1)

Co,1 Co,2 Co,3

td = O(N)

tadder = (N-1)tcarry + tsum

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Arithmetic Circuits

Complimentary Static CMOS Full AdderComplimentary Static CMOS Full Adder

28 Transistors

A B

B

A

Ci

Ci A

X

VDD

VDD

A B

Ci BA

B VDD

A

B

Ci

Ci

A

B

A CiB

Co

VDD

S

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Arithmetic Circuits

Inversion PropertyInversion Property

A B

S

CoCi FA

A B

S

CoCi FA

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Arithmetic Circuits

Minimize Critical Path by Reducing Inverting StagesMinimize Critical Path by Reducing Inverting Stages

Exploit Inversion Property

A3

FA FA FA

Even cell Odd cell

FA

A0 B0

S0

A1 B1

S1

A2 B2

S2

B3

S3

Ci,0 Co,0 Co,1 Co,3Co,2

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Arithmetic Circuits

A Better Structure: The Mirror AdderA Better Structure: The Mirror Adder

VDD

Ci

A

BBA

B

A

A B

Kill

Generate"1"-Propagate

"0"-Propagate

VDD

Ci

A B Ci

Ci

B

A

Ci

A

BBA

VDD

SCo

24 transistors

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Arithmetic Circuits

Mirror AdderMirror Adder

Stick Diagram

Ci

A B

VDD

GND

B

Co

A Ci

Co

Ci

A B

S

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Arithmetic Circuits

The Mirror AdderThe Mirror Adder

•The NMOS and PMOS chains are completely symmetrical. A maximum of two series transistors can be observed in the carry-generation circuitry.

•When laying out the cell, the most critical issue is the minimization of the capacitance at node Co. The reduction of the diffusion

capacitances is particularly important.

•The capacitance at node Co is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell .

•The transistors connected to Ci are placed closest to the output.

•Only the transistors in the carry stage have to be optimized foroptimal speed. All transistors in the sum stage can be minimal size.

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Arithmetic Circuits

Transmission Gate Full AdderTransmission Gate Full Adder

A

B

P

Ci

VDDA

A A

VDD

Ci

A

P

AB

VDD

VDD

Ci

Ci

Co

S

Ci

P

P

P

P

P

Sum Generation

Carry Generation

Setup

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Arithmetic Circuits

Manchester Carry ChainManchester Carry Chain

CoC

i

Gi

Di

Pi

Pi

VDD

CoC

i

Gi

Pi

VDD

φφφφ

φφφφ

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Arithmetic Circuits


G2

φφφφ

C3

G3

Ci,0

P0

G1

VDD

φφφφ

G0

P1

P2

P3

C3

C2

C1

C0

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Arithmetic Circuits


Pi + 1

Gi + 1

φ

Ci

Inverter/Sum Row

Propagate/Generate Row

Pi

Gi

φ

Ci - 1

Ci + 1

VDD

GND

Stick Diagram

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Arithmetic Circuits

CarryCarry--Bypass AdderBypass Adder

FA FA FA FA

P0 G1 P0 G1 P2 G2 P3 G3

Co,3Co,2Co,1Co,0Ci ,0

FA FA FA FA

P0 G1 P0 G1 P2 G2 P3 G3

Co,2Co,1Co,0Ci,0

Co,3

Mu

ltip

lexer

BP=PoP1P2P3

Idea: If (P0 and P1 and P2 and P3 = 1)

then Co3 = C0, else “kill” or “generate”.

Also called

Carry-Skip

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Arithmetic Circuits

CarryCarry--Bypass Adder (cont.)Bypass Adder (cont.)

Carrypropagation

Setup

Bit 0–3

Sum

M bits

tsetup

tsum

Carrypropagation

Setup

Bit 4–7

Sum

tbypass

Carrypropagation

Setup

Bit 8–11

Sum

Carrypropagation

Setup

Bit 12–15

Sum

tadder = tsetup + Mtcarry + (N/M-1)tbypass + (M-1)tcarry + tsum

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Arithmetic Circuits

MultipliersMultipliers

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Arithmetic Circuits

The Binary MultiplicationThe Binary Multiplication

Z X··

Y× Zk2k

k 0=

M N 1–+

∑= =

Xi2i

i 0=

M 1–

∑

Yj2j

j 0=

N 1–

∑

=

XiYj2i j+

j 0=

N 1–

∑

i 0=

M 1–

∑=

X Xi2i

i 0=

M 1–

∑=

Y Yj2j

j 0=

N 1–

∑=

with

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Arithmetic Circuits

The Binary MultiplicationThe Binary Multiplication

x

+

Partial products

Multiplicand

Multiplier

Result

1 0 1 0 1 0

1 0 1 0 1 0

1 0 1 0 1 0

1 1 1 0 0 1 1 1 0

0 0 0 0 0 0

1 0 1 0 1 0

1 0 1 1

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Arithmetic Circuits

The Array MultiplierThe Array Multiplier

Y0

Y1

X3 X2 X1 X0

X3

HA

X2

FA

X1

FA

X0

HA

Y2X3

FA

X2

FA

X1

FA

X0

HA

Z1

Z3Z6Z7 Z5 Z4

Y3X3

FA

X2

FA

X1

FA

X0

HA

Z2

Z0

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Arithmetic Circuits

The The MxNMxN Array MultiplierArray Multiplier

—— Critical PathCritical Path

HA FA FA HA

HAFAFAFA

FAFA FA HA

Critical Path 1

Critical Path 2

Critical Path 1 & 2

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Arithmetic Circuits

CarryCarry--Save MultiplierSave Multiplier

HA HA HA HA

FAFAFAHA

FAHA FA FA

FAHA FA HA

Vector Merging Adder

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Arithmetic Circuits

Multiplier Multiplier FloorplanFloorplan

SCSCSCSC

SCSCSCSC

SCSCSCSC

SC

SC

SC

SC

Z0

Z1

Z2

Z3Z4Z5Z6Z7

X0X1X2X3

Y1

Y2

Y3

Y0

Vector Merging Cell

HA Multiplier Cell

FA Multiplier Cell

X and Y signals are broadcasted

through the complete array.

( )

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Arithmetic Circuits

ShiftersShifters

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Arithmetic Circuits

The Binary ShifterThe Binary Shifter

Ai

Ai-1

Bi

Bi-1

Right Leftnop

Bit-Slice i

...

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Arithmetic Circuits

The Barrel ShifterThe Barrel Shifter

Sh3Sh2Sh1Sh0

Sh3

Sh2

Sh1

A3

A2

A1

A0

B3

B2

B1

B0

: Control Wire

: Data Wire

Area Dominated by Wiring

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Arithmetic Circuits

4x4 barrel shifter4x4 barrel shifter

BufferSh3S h2Sh 1Sh0

A3

A2

A 1

A 0

Widthbarrel ~ 2 pmM

digital integrated circuits - universidade federal de ...j.guntzel/ine5442/csi_aulas37-40.pdf ·...

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