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Digital Logic and Design (EEE-241)Lecture 10

Dr. M. G. Abbas Malikabbas malik@ciitlahore edu [email protected]

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Previous lecturePrevious lectureAnalysis of Combinational LogicDesign of multilevel NAND combinational circuitsAnalysis of multilevel NAND combinational i itcircuits

Design of multilevel NOR combinational circuitsA l i f ltil l NOR bi ti l i itAnalysis of multilevel NOR combinational circuitsHowe work:

Design and Analysis of Exclusive OR andDesign and Analysis of Exclusive-OR and Equivalence logic circuits

Dr. M. G. Abbas Malik – COMSATS Lahore2

Combinational Circuit – Cost Anal sisAnalysisDesign Procedure - Constraints1. Minimum number of gates2. Minimum number of inputs to a gate3 Mi i ti ti f th i l th h th3. Minimum propagation time of the signal through the

circuit4. Minimum number of interconnections4. Minimum number of interconnections5. Limitations of the driving capabilities of each gate

Since all these criteria cannot be satisfied simultaneously and importance of each constraint is dictated by the particular application, it is difficult to make a general statement.


make a general statement.

Combinational Circuit – Cost Anal sisAnalysis

Given two circuits that perform the same function:The circuit with fewer gates is preferable and is costThe circuit with fewer gates is preferable and is cost effective.This is not necessarily true when Integrated Circuits (IC) are used( )

Since several gates are included in a single IC package, it becomes economical to use as many gates from an already used package even if, by doing

fso, we increase the total number of gates.Some of the interconnections among gates ICs are internal to the chip.It is economical to use as many internal connections as possible to minimize the number of wires between external pins of ICs.


Combinational Circuit with ICsCombinational Circuit with ICsIn several occasions, the classical method will not produce the best combinational circuit for a givenproduce the best combinational circuit for a given function.Truth Table simplification becomes too cumbersome if the number of input variable is excessively large.the number of input variable is excessively large.With Integrated Circuits, it is not the count of gates that determines the cost but the number and types of ICs employed and the number of externalICs employed and the number of external interconnections needed to implement the given Boolean function.In many cases the application of an alternate design y pp gprocedure can produce a combinational circuit for a given function that is far better than the one obtained by the classical design method.


Combinational Circuit with ICsCombinational Circuit with ICsThe classical method constitutes a general procedure that if followed guarantees to produce a resultthat, if followed, guarantees to produce a result.Before going through a detailed design of a combinational circuit, one should look whether the function is already available in an IC package.function is already available in an IC package.

SSI – Small-scale IntegrationMSI – Medium-scale IntegrationLSI – Large-scale IntegrationLSI Large scale Integration

In this lecture, we will study examples of combinational circuits designed by methods other than the classical procedure.pAll of the examples demonstrate the internal construction of existing MSI.


Binary Parallel AdderBinary Parallel AdderThe full-adder forms the sum of two bits and a previous carry.Two binary numbers of n bits each can be added by means of this circuitby means of this circuit.When pair of bits are added through the full-adder, the circuit produces a carry to be used with thethe circuit produces a carry to be used with the pair of bits one higher significant position


Binary Parallel AdderBinary Parallel AdderThe bits are added with full-adders, starting from the least significant position, to form the sum bit and carry bit.The sum of two n bit binary numbers A and BThe sum of two n-bit binary numbers A and B, can be generated in two ways: either in serialfashion or in parallel.pThe serial addition method uses only one full-adder circuit and a storage device to hold the generated output carry and sum.The parallel method uses n full-adder circuits.


Binary Parallel AdderBinary Parallel AdderA binary parallel adder is a digital function that produces the arithmetic sum of two binary numbers in parallel.Example: 4 bit Binary Parallel Adder CircuitExample: 4-bit Binary Parallel Adder Circuit


Binary Parallel AdderBinary Parallel AdderAn n-bit parallel adder requires n full-addersIt can be constructed from 4-bit, 2-bit and 1-bit full-adders ICs by cascading several packages.Th 4 bit bi ll l dd i t i lThe 4-bit binary parallel adder is a typical example of an MSI function.It can be used in many applications involvingIt can be used in many applications involving arithmetic operations.The application of this MSI function to the design e app ca o o s S u c o o e des gof a combinational circuit is demonstrated in the example of BCD to excess-3 code converter.


Binary Parallel AdderBinary Parallel AdderExample: BCD to excess-3 code converter

A = BCS CodeB = 0011B = 0011


Binary Parallel AdderBinary Parallel AdderCarry Propagation

The addition of two binary numbers in parallel impliesThe addition of two binary numbers in parallel implies that all the bits of the augend and the addend are available for computation at the same time.As in any combinational circuit the signal mustAs in any combinational circuit, the signal must propagate through the gates before the correct output sum is available in the output terminals.The total propagation time is equal to the propagationThe total propagation time is equal to the propagation delay of a typical gate times the number of gate levels in the circuit.The longest propagation delay time in a parallel adderThe longest propagation delay time in a parallel adder is the time it takes the carry to propagate through the full-adders



The number of gate levels for the carry propagation can be found from the circuit of the full adderfull adderThe signal from the Carry (Ci) to the output carry (Ci+1) propagates through 2 gate levels(Ci+1) propagates through 2 gate levels



If there are four full-adders in the parallel adder, the output carry C5 would have 2 × 4 = 8 gate levels from C1 to C5.C1 to C5.The total propagation time in the adder would be the propagation time in one half adder plus eight gate l llevelsFor an n-bit parallel adder, there are 2n gate levels for the carry to propagate through.for the carry to propagate through.The carry propagation time is a limiting factor on the speed with which two numbers are added in parallel.



All th ith ti ti i l t dAll other arithmetic operations are implemented by successive additions, the time consumed during the addition process is very critical.g p yOne way to reduce the carry propagation delay time is to employ faster gates with reduced delaysA th l ti i t i th i tAnother solution is to increase the equipment complexity in such a way that the carry delay time is reduced.The most widely used technique employs the principle of look-ahead carry.



Look ahead CarryLook-ahead CarryIf we define two variables:

Pi = Ai ⊕ BiGi = AiBi

Gi is called a carry generate and it produces an output carry when both Ai and Bi are one.Pi is called a carry propagate because it is the term associated with the propagation of the carry Ci to Ci+1The output sum and carry can be expressed as:p y p

Si = Pi ⊕ CiCi+1 = Gi + PiCi



Look-ahead CarryThe Boolean functions for the carry output of each tstage are:



Look-ahead CarryCircuit diagram of a look-ahead carry generator


Binary Parallel AdderBinary Parallel Adder4-bit Full-adders with Look-ahead carry


Decimal Adder BCD AdderDecimal Adder – BCD AdderComputers or calculators that perform arithmetic operations directly in the decimal number systemoperations directly in the decimal number system represent decimal numbers in binary-coded form.An adder for such a computer must employ arithmetic circuits that accept Binary Coded Decimal (BCD)circuits that accept Binary Coded Decimal (BCD) numbers and present results in the accepted code.A decimal adder requires a minimum of nine inputsand five outputs:and five outputs:Inputs

Four bits are required to code each decimal digit (8)One input carry (1)p y ( )

OutputsFour bits to represent the output decimal digit (4)One bit for output carry (1)


p y ( )

Decimal Adder BCD AdderDecimal Adder – BCD AdderTo design a 9-input, 5-output combinational circuit b the classical method req ires a tr th table ithby the classical method requires a truth table with 29 = 512 entries.Many of the input combinations are “Don’t Care” y pconditions.An alternate procedure is to add the numbers with full adder circuits taking into considerationwith full-adder circuits, taking into consideration the fact that six combinations in each 4-bit input are not used.The output must be modified so that VALID binary combinations of the decimal code are generated


Decimal Adder BCD AdderDecimal Adder – BCD AdderConsider the arithmetic addition of two decimal digits in BCD, together with a possible carry from a previous stage.The input digit cannot exceed 9 so the outputThe input digit cannot exceed 9, so the output sum cannot be greater than

9+9+1(input carry)=19( p y)If we apply two BCD digits to a 4-bit binary adder, the adder will form the sum in binary and produced a result in a range from 0 to 19.

0 0 0 11 0 0 11 0 0 1


1 0 0 1---------

1 0 0 1 1

Output of 4-bit adder – Binary Sum BCD SumDecimal

K Z8 Z4 Z2 Z1 C S8 S4 S2 S1

0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 2

0 0 0 1 1 0 0 0 1 1 3

0 0 1 0 0 0 0 1 0 0 40 0 1 0 0 0 0 1 0 0 4

0 0 1 0 1 0 0 1 0 1 5

0 0 1 1 0 0 0 1 1 0 6

0 0 1 1 1 0 0 1 1 1 7

0 1 0 0 0 0 1 0 0 0 8

0 1 0 0 1 0 1 0 0 1 9

0 1 0 1 0 1 0 0 0 0 10

0 1 0 1 1 1 0 0 0 1 110 1 0 1 1 1 0 0 0 1 11

0 1 1 0 0 1 0 0 1 0 12

0 1 1 0 1 1 0 0 1 1 13

0 1 1 1 0 1 0 1 0 0 14

0 1 1 1 1 1 0 1 0 1 15

1 0 0 0 0 1 0 1 1 0 16

1 0 0 0 1 1 0 1 1 1 17

1 0 0 1 0 1 1 0 0 0 18


1 0 0 1 1 1 1 0 0 1 19

Decimal Adder BCD AdderDecimal Adder – BCD AdderWhen the binary sum is equal to or less than 1001, th di BCD i id ti lthe corresponding BCD sum is identical.When binary sum is greater than 1001, we obtain an invalid BCD representation.invalid BCD representation.A correction of BCD is need when the binary sum has an output carry K = 1. The other six combinations ffrom 1010 to 1111 that need a correction has Z8 = 1 and further more either Z4 or Z2 must be 1.

C = K + Z8Z4 + Z8Z2C K + Z8Z4 + Z8Z2

When C = 1, it is necessary to add 0110 to the binary sum and provide an output carry for the next stage.


Decimal Adder BCD AdderDecimal Adder – BCD AdderA BCD adder is a circuit that adds two BCD digits in parallel and produces a sum digit in BCD and a carry.A BCD adder must include the correction logic inA BCD adder must include the correction logic in its internal construction.To add 0110 to the binary sum, we use a secondTo add 0110 to the binary sum, we use a second 4-bit binary adder.


Decimal Adder BCD AdderDecimal Adder – BCD Adder


Decimal Adder BCD AdderDecimal Adder – BCD AdderA BCD adder can be constructed with three IC packagespackages

2 MSI package: 2 4-bit adders1 SSI package: three gates for the correction logicp g g g

To achieve shorter propagation delay, an MSI BCD adder includes the necessary circuits for look ahead carrieslook-ahead carries.A Decimal parallel adder that adds n decimal digits needs n BCD adder stages. The output g gcarry from one stage must be connected to the input carry of the next higher-order stage.


Home workHome workChapter 5: Section 5-4

Magnitude Comparator


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