digital system testing_1

8/3/2019 Digital System Testing_1

1/83

Click to edit Master subtitle style

4/27/12

Digital System Testing


2/83

4/27/12

Why Testing..?

To determine the presence of faults,not the absence of faults, in a givencircuit.

No amount of testing can guarantee that acircuit (chip, board or system) is fault free.

We carry out testing to increase our confidence

in proper working of the circuit. Verification is an alternative to

testing, used to verify the

correctness of a design.


3/83

4/27/12

Testing basics

Verification:Predictive analysis to ensure thatthe synthesized design, when manufactured,will perform the given I/O function.

Test: A manufacturing step that ensures thatthe physical device, manufactured from the

synthesized design, has no manufacturing

defect.


4/83

4/27/12

Testing vs. Verification

Testing Verifies correctness ofmanufactured hardware.

Two-part process:

1. Test generation: softwareprocess executed onceduring design

2. Test application:

electrical tests applied tohardware

Test application performed onevery manufactured device.

Responsible for quality ofdevices.

Verification Verifies correctnessof design.

Performed bysimulation, hardwareemulation, or formal

methods.


5/83

4/27/12

Levels of Testing

Testing can be carried out at the levelof

Chip

Board

System

Cost :: Rule of 10 It costs 10 times more to test a device

as we move to the next higher level in

the product manufacturing process.


6/83

4/27/12

Levels of Testing

Other ways to define levels:

Important to develop correct faultmodels and simulation models.

Transistor

Gate

RTL (Mux, ALU, Reg, etc.,)

Functional/Behavioral


7/83

4/27/12

Costs of Testing

Design For Testability (DFT)

Chip area overhead and yield reduction

Performance overhead Software processes of test

Test generation and fault simulation

Test programming and debugging

Manufacturing test

Automatic test equipment(ATE) capitalcost


8/83

4/27/12

Basic Testing Principle


9/83

4/27/12

Basic Testing Principle


10/83

4/27/12

Defects, Errors, and Faults

Defect: A defectin an electronic systemis the unintended difference between theimplemented hardware and its intended

design. Error: A wrong output signal produced

by a defective system is called an error.An error is an effect whose cause issome defect.

Fault: A representation of a defect atthe abstracted function level is called a

fault.


11/83

4/27/12

Example

Consider a digital system consisting of two inputs a and b,one output c, and one two-input AND gate. The system isassembled by connecting a wire between the terminal aand the first input of the AND gate. The output of the gateis connected to c. But the connection between b and the

gate is incorrectly made b is left unconnected and thesecond input of the gate is grounded. The functional outputof this system, as implemented, is c=0, instead of thecorrect output c=ab.

For this system, we have:

Defect: a short to ground.

Fault: signal b stuck at logic 0.

Error: a=1,b=1 output c=0; correct output c=1.


12/83

4/27/12

Some Real Defects in Chips

Processing defects

Missing contact windows

Parasitic transistors

Oxide breakdown

. . .

Material defects

Bulk defects (cracks, crystal imperfections)

Surface impurities (ion migration)

. . .

Time-dependent failures

Dielectric breakdown

Electromigration

. . .


13/83

4/27/12

Yield

A manufacturing defect is a finitechip area with electricallymalfunctioning circuitry caused by

errors in the fabrication process.

A chip with no manufacturing defect

is called a good chip.

Fraction (or percentage) of good

chips produced in a manufacturing


14/83

4/27/12

Yield

Wafer

Defec

ts

Faultychips

Goodchips

Unclustered defectsWafer yield = 12/22 = 0.55

Clustered defects (VLSI)Wafer yield = 17/22 = 0.77


15/83

4/27/12

Fault Modeling

I/O function tests inadequate formanufacturing (functionality versuscomponent and interconnect testing)

Real defects (often mechanical) toonumerous and often not analyzable

A fault model identifies targets for testing

A fault model makes analysis possible


16/83

4/27/12

Common Fault Models

Stuck-at faults

Single, multiple

Transistor faults open and short faults

Memory faults

Coupling, pattern sensitive

PLA faults

stuck-at, cross-point, bridging


17/83

4/27/12

Stuck-at Faults

Some lines in the circuit arepermanently stuck at logic 0 or logic1.

Two types

Single stuck-at faults

Multiple stuck-at faults


18/83

4/27/12

Single Stuck-at Fault

Simpler to handle computationally

Reasonably good fault coverage

A test set for detecting single stuck-atfaults detects a large percentage ofmultiple stuck-at faults as well

Three properties define a single

stuck-at fault Only one line is faulty

The faulty line is permanently set to 0 or

1


19/83

4/27/12

Single Stuck-at Fault

For a circuit with k lines, the totalnumber of single stuck-at faultspossible is 2k.

Most widely used fault model in theindustry.


20/83

4/27/12

Example 1 (No Fanout)

1

XStuck-at-1

0(1)

0(1)

True

Response

Faulty

Response

1

1

0

0

TestVector


21/83

4/27/12

Example 2 (Fanout)

XOR circuit has 12 fault sites ( ) and24 single stuck-at faults

a

b

c

d

e

f

10

g hi1

s-a-0j

k

z

0(1)

1(0)

1

Test vector forh s-a-0 fault

Good circuitvalue

Faulty circuitvalue


22/83

4/27/12

Fault sites

Number of fault sites in a Booleangate circuit = #PI + #gates + #(fanout branches).


23/83

4/27/12

Fault Equivalence

Fault equivalence:Two faults f1and f2 are equivalent if all tests thatdetect f1 also detect f2.

If faults f1 and f2 are equivalent thenthe corresponding faulty functions

are identical.

Two faults of a Boolean circuit are

called equivalent iff they transform


24/83

4/27/12

Fault collapsing

All single faults of a logic circuit canbe divided into disjoint equivalencesubsets, where all faults in a subset

are mutually equivalent. A collapsedfault set contains one fault from eachequivalence subset.

faultsallofSet

faultscollapsedofSetRatioCollapse =


25/83

4/27/12

Equivalence Rules

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0sa1

sa0sa1

sa0

sa0sa1

sa1

sa0

sa0

sa0sa1

sa1

sa1

AND

NAND

OR

NOR

WIRE

NOT

FANOUT


26/83

4/27/12

Equivalence Example


27/83

4/27/12

Equivalence Example

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

Faults inblueremovedbyequivalen

cecollapsing

20Collapse ratio = -----


28/83

4/27/12

Fault Dominance

If all tests of some fault F1 detectanother fault F2, then F2 is said todominate F1.

Dominance fault collapsing:

If fault F2 dominates F1, then F2 isremoved from the fault list.

When dominance fault collapsing isused, it is sufficient to consider onlythe input faults of Boolean gates.


29/83

4/27/12

Fault Dominance

In a tree circuit (without fanouts) PIfaults form a dominance collapsedfault set.

If two faults dominate each otherthen they are equivalent.


30/83

4/27/12

Dominance Example

s-a-1F1

s-a-1F2

001110 010

000

101 100 011

All tests ofF2

Only test of F1s-a-1

s-a-1s-a-1

s-a-0

A dominance collapsed fault set


31/83

4/27/12

Dominance Collapsing

An n-input Boolean gate requires n +1 single stuck-at faults to bemodeled.

To collapse faults of a gate, all faultsfrom the output can be eliminatedretaining one type (s-a-1 for AND andNAND; s-a-0 for OR and NOR) of faulton each input and the other type (s-

a-0 for AND and NAND; s-a-1 for OR


32/83

4/27/12

Checkpoints

Primary inputs and fanout branchesof a combinational circuit are calledcheckpoints.

Checkpoint theorem: A test set thatdetects all single (multiple) stuck-atfaults on all checkpoints of acombinational circuit, also detects allsingle (multiple) stuck-at faults in

that circuit.


33/83

4/27/12

Checkpoints

Total fault sites = 16

Checkpoints ( ) = 10


34/83

4/27/12

Transistor (Switch) Faults

MOS transistor is considered an idealswitch and two types of faults aremodeled:

Stuck-open -- a single transistor ispermanently stuck in the open state.

Stuck-short -- a single transistor ispermanently shorted irrespective of its gatevoltage.

Detection of a stuck-open faultrequires two vectors.

-


35/83

4/27/12

Stuck-Open Example

Two-vector s-op test

can be constructed byordering two s-at testsA

B

VD

D

C

pMOSFETs

nMOSFETs

Stuck-open

1

0

0

0

0 1(Z)

Good circuit states

Faulty circuit states

Vector 1: test forA s-a-0(Initialization vector)

Vector 2 (test forA s-a-1)


36/83

4/27/12

Stuck-Short Example

A

B

VDD

C

pMOSFETs

nMOSFETs

Stuck-short

1

0

0 (X)

Good circuit state

Faulty circuit state

Test vector forA s-a-0

IDDQ path infaulty circuit

i


37/83

4/27/12

Automatic Test-PatternGenerator

ATPG algorithms inject a fault into acircuit, and then use a variety ofmechanisms to activate the fault and

cause its effect to propagate throughthe hardware and manifest itself at acircuit output.


38/83

4/27/12

Random Pattern GenerationStart

Set inputprobabilities

Generate a randomvector

Simulate Faults

CheckCoverage

Stop

ChangeProbabilities

Adequate

Inadequate


39/83

4/27/12

Random Pattern Generation

Use to get tests for 60-80% of faults,then switch to ATPG(Automatic TestPattern Generation) for rest.

No. of patterns

FaultCoverage

100%

30

0

F ti l St t l


40/83

4/27/12

Functional vs StructuralATPG

Functional ATPG programs generate acomplete set of test-patterns tocompletely exercise the circuit

function.

Structural test only exercises theminimal set of stuck-at faults on eachline of the circuit, after discardingequivalent faults.

F ti l St t l


41/83

4/27/12

Functional vs StructuralATPG

Example 64 bit adder

FunctionalBlock


42/83

4/27/12

Functional ATPG

Generate complete set of tests forcircuit input-output combinations.

129 inputs, 65 outputs

2129 =680,564,733,841,876,926,926,749,214,863,536,422,912

input patterns required.

Fastest automatic test equipment(ATE),

operating at 1GHZ would take2.1580566142x1022 years to apply all thesepatterns.


43/83

4/27/12

Structural ATPG

Sum Circuit


44/83

4/27/12

Structural ATPG

Carry Circuit


45/83

4/27/12

Structural ATPG

In the adder

No redundant adder hardware, 64 bitslices.

Each with 27 faults

At most 64x27 = 1728 faults (tests)

Takes 0.000001728 s on 1GHZ ATE.

In practice

Designer gives small set of functional

tests.


46/83


4/27/12

Design For Testability

(DFT)


47/83

4/27/12

Definition

Design for testability(DFT) refers to thosedesign techniques that make test generation andtest application cost-effective.

DFT methods for digital circuits:

Ad-hoc methods

Structured methods:

Scan

Partial Scan

Built-in self-test(BIST)

Boundary scan

DFT method for mixed-signal circuits:


48/83


4/27/12

Ad-hoc methods


49/83

4/27/12

Ad-Hoc DFT Methods

Good design practices learnt through experienceare used as guidelines:

Do-s and Donts

Avoid asynchronous (unclocked) feedback.

Avoid delay dependant logic.

Avoid self resetting logic.

Avoid gated clocks.

Avoid redundant gates. Avoid large fanin gates.

Make flip-flops initializable.

Separate digital and analog circuits.

Provide test control for difficult-to-control signals.


50/83

4/27/12

Design reviews conducted by experts or designauditing tools.

Disadvantages of ad-hoc DFT methods:

Experts and tools not always available.

Test generation is often manual with no guarantee of highfault coverage.

Design iterations may be necessary.


51/83


4/27/12

Structured methods


52/83

4/27/12

1.Scan Design

Objectives

Simple read/write access to all subset ofstorage elements in a design.

Direct control of storage elements to anarbitrary value (0 or 1)

Direct observation of the state of

storage elements and hence the internalstate of the circuit.

Enhanced controlability and

observability


53/83

4/27/12

Scan Design

Circuit designed using pre-specifieddesign rules.

Test structure added to the verifieddesign

Add one(or more) test control(TC)primary input.

Replace flip-flops by scan flip-flops andconnect to form one or more shiftregisters in the test mode.

Make input/output of each scan shift


54/83

4/27/12

Scan Design

Use combinational ATPG to obtain testsfor all testable faults in thecombinational logic.

Add shift register tests and convertATPG tests into scan sequences for usein manufacturing test.


55/83

4/27/12

Scan Design Rules

Use only clocked D-type of flip-flopsfor all state variables.

At least one PI pin must be availablefor test; more pins, if available, canbe used.

All clocks must be controlled fromPIs.

Clocks must not feed data inputs offlip-flops.


56/83

4/27/12

Correcting a Rule ViolationCorrecting a Rule Violation

All clocks must be controlled from PIs.

Comb.

logic Comb.

logic

D

1D2C

K

Q

FF

Comb.

logic

D1D

2 CK

Q

FF

Comb.

logic


57/83

4/27/12

Scan Flip-Flop (SFF)

DTC

SD

C

K

Q

QMUX

D flip-

flop

Masterlatch

Slavelatch

CK

TC

Normal mode, D

selected

Scan mode, SD

selected

Masteropen

Slaveopen

t

t

Logicoverhead


58/83

4/27/12

Adding Scan Structure

SFF

SFF

SFF

Combinational

logic

PI PO

SCANOUT

SCANIN

TC or TCK Not shown: CKor

MCK/SCK feed


59/83

4/27/12

Combinational Test Vectors

I2

I1 O1 O2

S2S1 N2N1

Combinational

logic

P

I

Presen

tstate

P

O

Nex

tstate

SCANINTC

SCANOUT


60/83

4/27/12

Testing Scan Register

Scan register must be tested prior toapplication of scan test sequences.

A shift sequence 00110011 . . . of

length nsff+4 in scan mode (TC=0)produces 00, 01, 11 and 10transitions in all flip-flops andobserves the result at SCANOUToutput.


61/83

4/27/12

Multiple Scan Registers

Scan flip-flops can be distributed among anynumber of shift registers, each having a separatescanin and scanoutpin.

Test sequence length is determined by the longest

scan shift register. Just one test control (TC) pin is essential.

SFF

SFF

SFF

Combinational

logic

PI/SCANIN

MUX

CK

TC


62/83

4/27/12

Scan Overheads

IO pins: One pin necessary.

Area overhead:

Gate overhead = [4 nsff/(ng+10nff)] x100%,

where ng = comb. gates; nff = flip-flops;

Example ng= 100k gates, nff = 2k flip-flops, overhead = 6.7%.

More accurate estimate must considerscan wiring and layout area.


63/83

4/27/12

Hierarchical Scan

Scan flip-flops are chained within subnetworksbefore chaining subnetworks.

Advantages:

Automatic scan insertion in netlist

Circuit hierarchy preserved helps in debugging and designchanges

Disadvantage: Non-optimum chip layout.SFF

1

SFF2

SFF3

SFF

4 SFF3SFF1

SFF2

SFF4

Scanin

Scanout

Scanin Scanou

t

Hierarchical

netlist

Flat

layout


64/83

4/27/12

Scan Design - Summary

Scan is the most popular DFTtechnique:

Rule-based design

Automated DFT hardware insertion

Combinational ATPG

Advantages:

Design automation

High fault coverage; helpful in diagnosis

Hierarchical scan-testable modules areeasily combined into large scan-testable

systems


65/83

4/27/12

Scan Design - Summary

Disadvantages: Additional pin requirement.

Test hardware slows down the clock

Large test data volume and long test time

Basically a slow speed (DC) test


66/83

4/27/12

2.Partial-Scan Definition

A subset of flip-flops is scanned.

Objectives:

Minimize area overhead and scan sequencelength, yet achieve required fault coverage

Exclude selected flip-flops from scan:

Improve performance Allow limited scan design rule violations

Allow automation:

In scan flip-flop selection


67/83

4/27/12

Partial-Scan Architecture

FFFF

SFF

SFF

Combinational

circuit

PI

PO

CK1

CK

2SCANOUT

TC


68/83

4/27/12

Partial-Scan -Summary

Partial-scan is a generalized scanmethod; scan can vary from 0 to100%.

Partial-scan has lower overheads(area and delay) and reduced test

length.

Partial-scan allows limited violations


69/83

4/27/12

3.Built-In Self-Test (BIST)

Useful for field test and diagnosis(less expensive than a localautomatic test equipment)

Software tests for field test anddiagnosis:

Low hardware fault coverage

Low diagnostic resolution Slow to operate

Hardware BIST benefits:

Lower system test effort

Test Problems Alleviated by


70/83

4/27/12

Test Problems Alleviated byBIST

Increasing chip logic-to-pin ratio harder observability

Increasingly dense devices and

faster clocks Increasing test generation and

application times

Increasing size of test vectors storedin ATE

Expensive ATE needed for 1 GHz

clocking chips


71/83

4/27/12

BIST Costs

Chip area overhead for: Test controller

Hardware pattern generator

Hardware response compacter

Testing of BIST hardware

Pin overhead -- At least 1 pin needed to

activate BIST operation

Performance overhead extra path delaysdue to BIST


72/83

4/27/12

BIST Architecture

BILBO Built-in Logic Block


73/83

4/27/12

BILBO Built in Logic BlockObserver

Programmable hardware block.

Can work as both a Test PatternGenerator(TPG) and a Response

Compactor(RC). Four modes of operation:

1. Flip-flop

2. LFSR pattern generator

3. LFSR response compacter

4. Scan chain for flip-flops


74/83

4/27/12

S


75/83

4/27/12

LFSR

4 B d S


76/83

4/27/12

4.Boundary Scan

IEEE 1149.1 JTAG Boundary ScanStandard

S T L i


77/83

4/27/12

System Test Logic

Elementary Boundary Scan


78/83

4/27/12

Elementary Boundary ScanCell

S i l B d / MCM S


79/83

4/27/12

Serial Board / MCM Scan

P ll l B d / MCM S


80/83

4/27/12

Parallel Board / MCM Scan


81/83

4/27/12

Tap Controller

Boundary Scan Instructions

TESTING PORTIONS


82/83

4/27/12

TESTING -PORTIONS

ROTH-339 to 354 ,361 to 365

P 457 to461 p477 ,481 to 483,

P 1-8 ,p93 to 106 P 343 to 369


83/83


Thank You

All the Best

digital system testing_1

Documents