digital technique handoutt#11

Digital Technique Mrs. Sunita M Dol, CSE Dept

Walchand Institute of Technology, Solapur

HANDOUT#11

AIM:

Verify the truth table of

1. RS Flip Flop

2. JK Flip Flop

3. D Flip Flop

4. T Flip Flop

LEARNING OBJECTIVES:

- To learn about various flip flop

- To verify the truth table of various flip flop

COMPONENT REQUIRED:

- Logic gates (IC) trainer kit.

- Connecting patch chords.

- IC 7400, IC 7408, IC 7404, IC 7473

Sr. No. Component Specification

1 JK FF IC 7473

2 NOT gate IC7404

3 AND gate IC7408

4 NAND gate IC 7400

THEORY:

Sequential circuit

Logic circuits that incorporate memory cells are called sequential circuit. In this

type of circuit, output depends not only upon the present value of input but also

upon the previous values.

Sequential logic circuit often requires the timing generator i.e. clock for their

operation.

The basic digital sequential circuit is known as flip flop. It has two stable states

which are known as state 1 and state 0. It can be obtained by using NAND or NOR

gates.



SR Flip Flop

In 1-bit memory cell, there is no way of entering the desired digital information to

be stored in it. When the power is switched on, the circuit switches to one of the

stable state (Q = 1 or 0) and it is not possible to predict the state.

Hence the inverters are replaced with 2-input NAND gates, the other terminals of

NAND gates can be used to enter the desired information. The modified circuit is

known as SR flip flop.

The condition S = R = 1 is forbidden and it must not be allowed to occur. It is often

required to set or reset the memory cell in synchronism with the train of pulses

known as clock. Such circuit is referred to as clocked SR flip flop.

S R Qn+1

0 0 Qn

0 1 0

1 0 1

1 1 ?



JK Flip Flop

The uncertainty in the state of an SR flip flop when Sn = Rn = 1 can be eliminated

by converting it into a JK flip flop. The data inputs are J and K which are ANDed

with and Q respectively to obtain S and R inputs such that .

But when J = K = 1 then output toggles. When flip flop is level triggered then flip

flop is active till active level is present

J K Qn+1

0 0 Qn

0 1 0

1 0 1

1 1 ?



D Flip Flop

If we use only the middle two rows of the truth table of SR flip flop or JK flip flop

then we obtain D flip flop. It has only one input referred to as D input or data

input.

Since the input data appears at the output end of the clock pulse, the transfer of

data from the input to output is delayed and hence the name delay (D) flips flop.

CLK D Qn+1

1 0 0

1 1 1

T Flip Flop

In a JK flip flop, if J = K, the resulting flip flop is referred to as T flip flop. If T =

1, it acts as toggle switch.



CLK T Qn+1

1 0 Qn

1 1 Toggle

PROCEDURE:

1. Check the components for their working.

2. Insert the appropriate IC into the IC base.

3. Make connections as shown in the circuit diagram.

4. Provide the input data via the input switches and observe the output on

output LEDs

5. Give various combinations of inputs and note down the output with help of

LED for all gate ICs one by one.

RESULT:

Thus we have verified the truth table of

1. RS Flip Flop

2. JK Flip Flop

3. D Flip Flop

4. T Flip Flop

digital technique handoutt#11

Engineering