1

Abstract Frequency domain Vector Fitting (VF) is a well known

technique to generate circuital models of a spatially discretized

lossy transmission lines from theoretical formulation of losses.

The sub-picosecond time steps required by multi-gigahertz

bandwidths and short transmission lines included in the models,

determine long Spice simulation times. A 100X speedup can be

gained using the Digital Wave Simulator (DWS) instead of

Spice. DWS processes the waves of a Digital Network built up

connecting together scattering blocks (circuit elements, nodes

and S-parameter multi-ports) coming from a Spice-like

description. Being a DSP wave processor instead of a classical

nodal equations solver, DWS is computationally very fast and

numerically stable. Comparisons with commercial simulators like

Microcap11 and CST Cable Studio show a good matching of

results. A further 10-100X simulation speedup is obtained if

Piecewise-Linear Fitting (PWLF) is used to describe the time-

domain behaviors of Scattering Parameters. Single or multiple

cell Behavioral Time Models (BTM) can be extracted by PWLF

from TDR/TDT measurements and processed by DWS fast

convolution algorithms. A setup de-embedding can be

performed by pwl breakpoints optimization to fit actual

measurements. A RG58 coaxial cable is analyzed and its VF-

derived eye-diagrams are compared to PWLF measurement-

derived results. At multi-gigabit rates significant differences,

due to cable physical implementation effects, are observed. The

modeling/simulation alternatives (VF/Spice, VF/DWS and

PWLF/DWS) are compared together and the advantages of

PWLF/DWS in term of simplicity, stability and speed are

highlighted.

Index Terms— Behavioral Time Modeling (BTM), , Digital

Wave Network (DWN), Digital Wave Simulator (DWS), Device

Under Test (DUT), Eye Diagrams (ED), Fast Fourier Transform

(FFT), Inter-Symbol Interference (ISI), Nodal Analysis (NA),

Printed Circuit Board (PCB), Piece-Wise Linear (PWL), Piece-

Wise Linear Fitting (PWLF), Pseudo Random Bit Sequence

(PRBS), Signal Integrity (SI), Time-Domain Reflectometer

(TDR), Time-Domain Transmission (TDT), Transmission Line

(TL), Vector Fitting (VF), Vector Network Analyzer (VNA),

Wave Digital Filter (WDF), Worst Case Eye Diagram (WCED).

I. DIGITAL WAVE SIMULATION: HISTORICAL

BACKGROUND

The application of digital wave algorithms to high-speed

circuit simulations started at CSELT Labs (Turin, Italy) in the

early '70s [1],[2]. This activity was inspired by prof. Alfred

Fettweis [3] early works on Wave Digital Filters (WDF).

While WDF work was focused on a class of digital filters able

to mimic the behavior of analog filters, the aim of CSELT

researchers was to build up a digital wave model of

interconnects among high-speed integrated circuits. The

digital wave equivalent of a Transmission Line (TL) was the

key element of a modular wave network used in the early

simulation program ETA (Easy Transient Analysis) [1]. The

I/O models of active devices were extracted from TDR

measurements and automatically fitted by simulation to predefined lumped/distributed (RLC-TL) electrical models.

Measurements, model fitting and simulation programs ran on

the same HP9821 desktop computer as shown in Fig.1 [2]. In

the following decade a new version of the simulator called

APICE (Advanced Program for Interconnect Circuital

Evaluation) was developed with extension to lossy

interconnects [4], crosstalk analysis and Worst Case Eye

Diagram (WCED) calculations [5]. In the following years

started the development of a simulation program for general

topology linear and nonlinear circuits. It was conceived with a

Spice-like netlist syntax and its proprietary algorithms

developed by P. Belforte and G. Guaschino included the solution of the well known DFL (Delay Free Loop) WDF

topology problem. Multi-port S-parameters blocks, piecewise

-linear description of time-domain behaviors, fast convolution

algorithms and nonlinear/time varying resistors were other

features of SPRINT (Simulation Program of Response of

Integrated Network Transients). The companion application

SIGHTS (Standard Interface for Graphic Handling of

Transient Signals) included simulated waveform plotting and

post-processing. WCED calculation, FFT and graphic PWL

extraction. SPRINT and SIGHTS were produced by HDT

(High Design Technology), the company founded in 1988 by P. Belforte and G. Guaschino. General applications to several

fields including analog and chaotic circuits, mixed analog,

logic and timing analysis were shown in [6]. Signal and Power

Integrity analysis included multi-port nonlinear IBIS-like

macromodels of driver/receivers [6]. A collection of state-of-

the art design applications was presented at the HP Digital

Design Symposium in 1993 [7] while an application to

modeling of Multi-Chip Modules lossy interconnects is

reported in [8]. Starting from the mid '90s, the HDT tools

were included in THRIS (Telecom Hardware Robustness

Inspection System) developed within a CSELT-HDT cooperation [9]. Simulation of radiated emissions (EMIR) was

added in the mid '90s [10]. After HDT's end of activity in

2001, the founders developed DWS (Digital Wave Simulator)

[11] and DWV (Digital Wave Viewer) [12]. From 2012 to

2015 a cloud-based version of DWS called Spicy SWAN was

developed including a schematic entry. In 2015 several

comparisons between DWS and Ngspice simulations were

performed in cooperation with the Ngspice developer team

[13]. The advantages of DWS applied to PEEC modeling have

Digital Wave Simulation of Lossy Lines for

Multi-Gigabit Applications

Piero Belforte, Member, IEEE

2

been presented at the recent SPI2016 IEEE Workshop in

May 2016 [14]. A more detailed story of DWS is also

available in reference [34].

Fig.1. CSELT LABS, Turin, year 1975: An early application of first-

generation Digital Wave simulator ETA in the design of a .5Gbps high-speed

Multichip Module. The 500Mhz simulated clock waveforms are plotted as eye

diagrams to evaluate jitter and skews.

II. VECTOR VS PIECEWISE-LINEAR FITTING

TECHNIQUES

The basic concepts of two fitting techniques for system

identification suitable for both signal and power integrity simulation are discussed. Both methods can deal with both

mono and two-dimensional signal propagation related to

lossy interconnects (cables, traces etc.) and power

distribution planes of printed circuit boards. The traditional

method is based on Vector Fitting (VF) [16], [17], a well

known technique to approximate complex functions of

frequency by a rational polynomial expression in terms of

poles and residues. The second is a full time-domain approach

mainly based on behavioral models (BTM) supported by

DWS [6], [7], [8], [9], [11], [12]. DWS processes the waves

of a Digital Network built up connecting together scattering

blocks (traditional circuit elements, nodes and S-parameter blocks) coming from a Spice-like description. The two

methods are schematically compared in the flow of Fig. 2.

A. The traditional way: Frequency domain Vector Fitting

and Spice simulation

Vector Fitting modeling flow is shown at the left side of Fig. 2. In case of mono-dimensional propagation, as applies

to lossy interconnects, the physical line is discretized

according to a chosen spatial pitch in several equal

segments (unit cells) connected in cascade. The pitch is

related to the required model bandwidth. Each cell can be

implemented as a ZY-TL circuit where Z is a series impedance, Y a parallel admittance, both frequency

dependent, and TL is an ideal Transmission Line (TL) as

shown in Fig. 3. Starting from the geometrical and physical

crossection data, the TL characteristic impedance Z0 is

obtained from theoretical formulations related to the specific

cross-section. TL delay time is the ratio between the spatial

pitch and the propagation velocity. Z(ω) and Y(ω) are

obtained from the theoretical expressions of skin effect and

dielectric losses vs. frequency respectively [18].

Fig.2 . General modeling/simulation flow: on the left the classical method

based on impedance Vector Fitting , on the right the full time-domain

approach based on S-parameters and DWS processing.

ES

RS

Z()

Y()

TL Z0, td Z0,td*Delt

Fig.3 . ZY-TL unit cell related to a spatial segmentation pitch

Using the VECTFIT code [17] applied to theoretical

frequency behaviors, unit-cell poles and zeros can be extracted and then mapped into RL or RLC circuits leading to a Spice-

like cellular model of the interconnect. This ZY-TL model

can be simulated in time domain using a conventional Nodal

Analysis solver like Spice. A careful choice of Spice version is

needed because the presence of several electrically "short"

Transmission Lines requires both an accurate TL model and

the ability to work at small (picosecond or even

subpicosecond) fixed time step. Only a subset of commercial

Spice versions is able to satisfy the previous conditions, while

other versions could lead to inaccurate results or convergence

problems. MicroCap11 (MC11) by Spectrum Software [19] is a Spice versions able to deal with this class of circuits.

B. An alternative way: Frequency-domain Vector Fitting

and DWS processing

DWS can be conveniently used to replace MC11 to

simulate the ZY-TL models because it requires typically

1/100 of the simulation time working at the same time step.

This means that sub-picosecond time steps can be used to get

accurate results in short times.

3

C. The unconventional way: Time-domain PWL Fitting and

DWS processing

This method can be applied when the time-domain S-

parameters step responses of the DUT are available. Sources

of such responses are TDR/TDT measurements, analytical formulas [32], or 2D/3D field solvers. In case of measurement,

a setup de-embedding is needed to extract the required

intrinsic DUT S-parameters. Modern TDR and VNA can

directly perform this task, otherwise a de-embedding loop

procedure can be performed by DWS simulation, as shown in

the flowchart of Fig.2. A Behavioral Time-domain Model

(BTM) [7], [8], can be created directly from the files

containing the samples of the de-embedded S-parameters

using the FILE mode description supported by DWS [11]. A

more computationally efficient way is to use the piecewise

linear fitting (PWLF) of S-parameter step response behaviors

as shown in Fig.2. This task can be done manually on the plotted waveforms using the MCS (Model Capture System)

facility [7] included in DWV [12], the DWS graphic

postprocessor, online tools, or even automatically on the

imported files coming from measurements or simulations. In

case of spatial segmentation in several BTM cells connected in

cascade (micro-behavioral model) [24], [25], [30] pwl

breakpoint optimization can be performed by comparing the

simulated result of the whole cascade of cells to

measurements or to imported simulations. At the end of this

optimization process a de-embedded model of the DUT is

obtained. A similar procedure can be applied to 2D BTM models of p.c.b power distribution planes [7]. Thanks to the

fast convolution algorithm included in DWS, the processing

time of PWL BTM models is 10 to 100 times shorter than the

time required using the circuital model.

III. COAXIAL CABLE CASE STUDY

A RG58 coaxial cable was chosen as a case study to

compare together modeling methods and simulation tools.

The results coming this study can be extended to lossy lines with different geometries like other cables and PCB

interconnects.

Time-domain pulse response of coaxial cables has been

deeply studied and several papers have been written in the past

on this topic. Significant papers on pulse response of coaxial

cable are available in [21],[22]. Several documents regarding

the comparisons between measurements and simulations

related to the RG58 coaxial cable have been written by P.

Belforte and S. Caniggia in recent years [23], [24], [25].

According to these documents, the fully terminated 1.83m

long cable interconnect of Fig.4 has been analyzed. A perfect cylindrical shape, like that considered by CST Cable Studio,

has been considered for the cable cross section, assuming the

conductors made by solid and homogeneous copper. The

geometrical and electrical parameters used for computing

Z(ω) and Y(ω) taking into account respectively skin effect and

dielectric losses are shown in Fig. 4, where εr is the relative

permittivity and tan δ the loss factor of the dielectric. The

related formulas can be found at chapter 7 of the book [18]. In

order to compare the results, tan is set to the default value used by CST Cable Studio for the RG58 cable. This value is

8e-4, four times the nominal values for polyethylene (2e-4).

The coaxial cable is segmented adopting a 3cm ZY_TL unit

cell physical length (. The equivalent circuits of Z() and

Y() have been extracted by S. Caniggia by means of the VECTFIT code [17] using 8 poles each. Two series and

parallel RL networks have been respectively synthesized to

map the 8 poles in frequency domain. TL characteristic

impedance Z0 and delay TD are obtained from the well known

coaxial cable formulas. For a 3cm unit cell length TD resulted to be 151.7608895659 ps. This delay value will be rounded or

interpolated according to the chosen simulation time step and

DWS option. The DWS netlist of this unit cell is shown on

the right side of Fig.5. A cascade of 61 ZY-TL 3 cm long

cells is used to model the 1.83m long cable.

Fig. 4. RG58 coaxial cable theoretical cross section (CST data) and matched

interconnection schematic.

A. Comparative simulations of the unit cell using Spice and DWS

Several simulations have been carried out using both

DWS and the evaluation version of MicroCap 11 (MC11)

[19]. These comparative benchmarks have been performed to

compare Digital Wave and Nodal Analysis methods in linear

and nonlinear transmission line situations requiring fixed time

step to get accurate results.

As a significant example of comparison, the 3cm ZY-TL unit

cell related to RG58 coaxial cable has been chosen. To stress

the numerical stability of both simulators a fully mismatched

configuration was selected as benchmark circuit. The schematic of this configuration is shown in Fig.5. A DWS

cascadable cell (RG58_3CM) is used to describe the ZY-TL

circuit. Serial adaptors (AS) and grounded inductors are used

to calculate two-port inductors according to the trapezoidal

rule [11]. A 2V ideal step generator V0 is connected to the

port P2 of the ZY-TL cell while the port P1 is open terminated

by a 50 Gigaohm resistor R0. The generator V0 stimulates the

ZY-TL cell with a 2V step having total rise-time of 10

femtoseconds. The voltage step propagates along the circuit

and when reaches the port P1 is reflected back by the open

termination. At port P2 the signal is inverted and reflected

back by the near zero impedance of generator V0. In this way a free oscillation voltage pattern is generated at port P1. At

each oscillation the waveform edges are slowed down by an

increasing dispersion due to cell losses modeled by the ZY-TL

network. Fig. 5 shows the simulated voltage waveform at

port P1 for the first 5ns. To get an accurate result a simulation

time step of 1 femtosecond has been chosen for both Spicy

SWAN and MC11. This implies the calculation of 10 Million

samples on the 10ns window for both simulators.

Z0=50Ω, tpd=5.058ns/m, L=1.83m 50Ω 50Ω

tr Vg

Vi Vo 0

2V

Conductor radius=0.395mm Shield inner radius =1.397mm, εr=2.3,

tanδ=0.8x10-3

4

Fig. 5. ZY-TL unit cell related to a 3cm RG58 coaxial cable segment in a free

oscillation test configuration. DWS cell description on the bottom.

The maximum difference resulted to be about 1 microvolt peak to peak, confirming a very good match between the

simulator responses. The time required for a 10ns simulation

on an Intel Quad-Core i7-2630QM 2.00GHz CPU is about 52

minutes for MC11 and 35 seconds for DWS (speedup 90X).

Fig.6. Simulated voltages at port P1 on a 5ns time window. DWS and

MicroCap11 results at 1Femtosecond time step (solid lines) and differences

(DELTA, dotted line).

B. Effects of simulation time step

The circuit of Fig.4 has been simulated using a cascade of

61 ZY-TL 3cm unit cells to model the 1.83m long cable. Two

ramp rise-times of 100ps and 1ps respectively have been used

for the input ramp to evaluate the effect of DWS simulation

time-step choice on the output waveform. The results are

shown in Fig. 7. Time step dependence is more significant

with the faster 1ps rise-time input. A significant error occurs

with a 5ps time step. A slight difference on the edge foot is

still visible between the responses related to 0.5ps and 1ps time steps. This difference is negligible with the 100ps ramp

input. From previous results, a good tradeoff between

simulation speed and accuracy is to choose a 1ps simulation

time step for input rise times in the order of 10ps.

Fig. 7. Cable output voltage related to the schematic of Fig. 4 using the 61

ZY-TL model at 3 different DWS simulation time steps: .5ps (solid line), 1ps

(dash dot line), 5ps (dotted line), 1ps and 100ps rise-time input ramps

C. Effects of spatial segmentation pitch

The effect of line length segmentation on digital bandwidth

has been evaluated in terms of Worst Case Eye Diagram inner

profile. Exploiting the DWS computational speed a

comparison has been carried out between a 61-cell (3 cm unit

length) and a 610-cell ZYTL (3 mm unit length) models in the

configuration of Fig. 4. The chosen input transition time is 17ps (20%-80%) with an erfc shape. The result in terms of

inner WCED contours is shown in Fig.8.

Fig. 8. 20 Gbps WCED inner contours comparison for a 3cm and 3mm ZYTL

cell length. 17ps transition time of erfc input signal. DWS simulation time

step=500 femtosec.

The difference between the two WCEDs is relatively small.

This means that the more computationally efficient 61 ZY-TL

cell model can be used at least up to 20-30Gbps getting a slightly optimistic result in terms of eye opening.

D. DWS vs. CST/Cable Studio comparison

A larger bandwidth eye-diagram comparison between

CST/CS 2014 and DWS was performed using a 40Gbps 255-

bit PRBS (25ps bit-time) input sequence.

In this case the time step was set to 1ps for both simulators

in order to achieve a good result accuracy taking into account

the 10ps (total) linear edges of the input signal. CST's CS

2014 has been used with modal model and 40Ghz bandwidth

settings. The eye-diagram comparison is shown in Fig. 9. The eye diagrams look similar in terms of both opening and ISI

5

jitter despite the high bit-rate used for this comparison. This

happens because also CST Cable Studio uses a VF-derived

ZY-TL cascade of cells to model the cable. The Y portion that

models the dielectric losses is implemented by CST using a

RC instead of the RL network of Fig.5 used with DWS.

Fig. 9. 40 Gbps 255-bit PRBS eye diagrams at cable output: upper CST/CS

2014, lower DWS, 10ps input ramp total transition time, time window=20ns,

Time step=1ps for both simulators.

A remarkable difference between the two simulators is the

CPU time required to get the eye diagrams of Fig.9 starting

from the calculated models. An Intel Quad-Core i7-2630QM

2.00GHz CPU requires 12 min with 4 CPU working in parallel

for CST/CS2014 while about 4 sec with a single CPU

engaged is required by DWS. The observed DWS/CST-

CS2014 speedup factor is 720X.

D. Experimental characterization of an actual cable

A RG58/CU 1.83m long coaxial cable has been

characterized using the setup shown in Fig. 10. The chosen sample is manufactured by Tasker company. The internal

conductor is composed by 19x0.18mm stranded tinned copper

wires while the 3mm diameter shield is composed by tinned

copper wires with 98% covering. The dielectric is

polyethylene while the 5mm diameter sheath is made in PVC.

The manufacturer gives also these data: 40milliohm/m DC

resistance, 66% relative propagation velocity, and a 6 values

of insertion loss vs. frequency from 50Mhz to 1Ghz. At

50Mhz the attenuation is 9.7 dB/100m while at 1Ghz it is 51.8

dB/100m. The TDR/TDT setup is shown in Fig. 10. In order

to get maximum simplicity and minimum cost, the launch/termination semi-rigid cables are soldered to the DUT

by means of short (1-2mm) splices. The outer conductors of

the same 60mm long SMA semi-rigid cables and those of the

RG58 cable are all soldered to a common ground plane of a

small metalized board. The 22ps (10%-90%) SD24 head

pulse rise-time is fast enough to get significant measurement

up to about 30Ghz. No particular calibration procedure is

required.

Fig. 10. CSA803C/SD24 TDR/TDT measurement setup for the RG58 CU

TASKER cable (l=1.83m) with details of connecting fixture (lower left) and

RG58 cable tip (lower right).

E. S-parameters de-embedding

An accurate mixed BTM-circuital model of the whole setup

has been developed on the basis of actual TDR response of

the setup alone. This model, shown in Fig.11, includes the actual SD24 pulse generator waveform , the SMA connectors,

the semi-rigid cables connected to DUT and the soldered

connections. The soldered connections, modeled by 115-

ohm 20ps TLs, act as markers on the measured waveform

simplifying the measurement of actual cable delay [23].

Fig.11 Schematic of the TDR/TDT setup of Fig.10 used for the de-embedding

of S21 pwl breakpoints

Fig.12 shows the measured S11 waveform on a 50 ns

window. Cable impedance micro-discontinuities due to cross

section variations (Fig. 19) are visible as well the narrow

impedance peaks due to soldered joints. S22 measurement

doesn't coincide with S11 due to the asymmetric effect of these

discontinuities. Fig.12 also shows an example of manually

extracted pwl approximation of S11. High frequency

impedance discontinuities are averaged to limit the number of

6

breakpoints. The narrow peaks due to reflections at soldered

joints are discarded.

Fig. 12. Example of PWL approximation of the measured S11 for the 1.83 m

RG58 CU TASKER coaxial cable (CSA 803C setup of Fig. 10).

The measured S21 rising edge is slowed down by the

setup effects. The S21 behavior de-embedding is performed starting from the pwl samples taken on the measured

waveform. This first approximated set of breakpoints is used

in the DWS simulative model of the whole setup (Fig. 11).

Breakpoint coordinates are then adjusted by iterations of the

optimization loop shown in Fig. 2. A comparison between the

measured S21 rising edge and the simulated edge including

the setup effects at the end of the fitting process is shown in

Fig. 13. The agreement is very good. The DWS netlist of the

extracted BTM cell and related optimized breakpoints are

shown in Fig.14.

Fig. 13. Measured S21 (edge, solid line) using the setup of Fig.11 vs.

the fitted BTM model including the setup effects (dotted line). 50ohm

terminations

Fig.14. DWS netlist of the de-embedded single-cell BTM model of the

1.83m RG58 coaxial cable

The de-embedded S21 waveform has a faster rising edge with respect the measured one. A total of 18 breakpoints are

required for S11 and 21 breakpoints for S21. The model of

Fig. 14 is supposed symmetrical for simplicity reasons. The

extracted BTM model has been also simulated configuring the

circuit of Fig.11 with TERM1 node connected to open

termination. The result is compared to the actual one-port

TDR measurement of the open cable. This comparison is

reported in Fig. 15 and shows a good agreement between

measurement and simulation with the exception of a slight

overestimation of reflected edge between 20ns and 23ns.

Fig.15. Measured TDR (solid line) vs. simulated waveform (dotted line)

including the setup of the RG58 cable open terminated.

The extracted pwl model of S-parameters is then used in

a circuit simulating an ideal TDR (1ps pulse rise-time) to get

the intrinsic response of the cable. In Fig.16 the 61-cell ZY-

TL theoretical model and the measurement-derived BTM

model of the RG58/CU cable are compared together with and

without setup effects.

Fig.16 Comparison of simulated S11 (upper) and S21 (lower) ZY-TL and

BTM models of the 1.83m RG58/CU cable. Both waveforms with and

without setup effects are shown.

Fig.16 points out significant differences between the two

models. The average magnitude of measurement-derived S11

is about 3 times larger than the value coming up from the

theoretically determined ZY-TL model. The measurement-derived S21 intrinsic rise-time (20%-80% , without setup) is

55ps, about twice the corresponding 30ps rise-time of the ZY-

TL model. A delay difference of 255ps between the intrinsic

model responses is also shown in Fig.16. The actual cable is

slightly faster than expected from the nominal relative

permittivity of polyethilene (Fig. 19).

7

F. Circuital vs. Behavioral model comparison

S21 rise-time difference has a substantial impact on high

bit-rate eye-diagrams as shown in Fig.17 for a 255-bit PRBS.

At 20Gbps the eye diagram is about closed using the

measurement-based BTM model and nearly open using the theory-derived ZY-TL model. The impact of S11 model

differences is not significant at the cable output , but becomes

remarkable in case of not fully terminated or bi-directional

transmission configurations [4].

Fig.17. Measurement-based BTM vs. ZY-TL model simulated eye

diagrams for a 20Gbps PRBS-255 bit sequence of the 1.83m RG58 coaxial

cable (DWS). Input risetime:17ps, erfc waveform.

An Intel Quad-Core i7-2630QM 2.00GHz CPU requires

about 0.4 sec to calculate the 100K samples of the BTM eye

diagram alone while about 30 sec are required for the

simultaneous simulation of both models. A comparative eye

diagram evaluation between RG58 and RG223 coaxial cables

using measurement-derived models is reported in [33].

G. Attenuation vs. frequency

Cable attenuation in dB/m has been obtained by

simulating the response of the RG58 models at various

frequencies and compared to manufacturer data in Fig.18.

Fig.18 Comparison of specific cable attenuation in dB/m, 50 MHz to 40 GHz

(upper) and 50MHz to 1GHz (lower).

A fair agreement between BTM model and manufacturer data

(up to 1GHz) is pointed out, while the attenuation produced by

the ZY-TL model is underestimated. The difference between

BTM and ZY-TL diverges for frequencies higher than 2Ghz

and becomes greater than 10dB beyond 20Ghz. The

differences observed at high frequencies can be explained considering that the actual cable shown in Fig. 19 is made

using tinned copper stranded conductors. Tin has a resistivity

7 times higher than copper. At 10 GHz the skin effect depth

for tin is in the order of 2 um and becomes comparable to tin

plating thickness.

Fig.19. a) Actual cross-section of the measured RG58 coaxial cable b)

detailed view of the tinned inner conductors

At higher frequencies (30-40GHz), the current flows

practically only on the tinned conductor surface. This explain

the attenuation difference considering that tin conductor

resistance is 7 times higher than copper, corresponding to a 17

dB higher attenuation. Other sources of different behaviors

can be conductor stranding and proximity effect not

considered in the ZY-TL model.

IV PERFORMANCE COMPARISON

The matrix depicted in Fig. 20 shows the performance

comparison among the three fitting and simulation

alternatives.

Fig. 20. Relative speedup matrix ( simulator vs. fitting method)

DWS simulations run typically 100X faster than Spice, while

the fast convolution applied to process PWLF behavioral time

models achieves a further 10-100X speedup. PWLF

combined with DWS processing offers several advantages

with respect VF combined with NA simulation. It is known

that time-domain S-parameters in matched conditions have

simpler behaviors than the corresponding frequency-domain

impedance behaviors [27]. This means that few pwl (tens)

breakpoints can approximate these behaviors with small

8

errors. To fit the equivalent impedances in frequency domain

a large number of poles and zeros could be required, leading

to potential numerical stability problems. These stability

problems can be corrected by conditioning in some way the

VF data. On the contrary the well known stability and

passivity of Digital Wave processing [15] doesn't require any conditioning of PWL description to prevent numerical

instability. Circuital models coming from Vector Fitting,

BTM models and even s-plane/z-plane descriptions can be

mixed to IBIS models of active devices in very complex

networks containing hundreds of thousands scattering

elements [31]. Thanks to a linear growth of simulation time

vs. network complexity, these models can be processed by

DWS in times that are more than 4 orders of magnitude

lower than those required by NA simulators. More BTM

modeling applications to p.c.b. interconnects, coupled traces

and p.c.b. power planes are reported in [29] and [30].

ACKNOWLEDGEMENT

The author thanks Mr. Spartaco Caniggia for the useful

discussions and for the calculated ZY-TL unit-cell data.

REFERENCES

[1] P. Belforte, U. Colonnelli, G. Guaschino "Use of Equivalent Digital Wave

Networks in the simulation of the interconnects among high-speed logic

devices," Alta Frequenza Vol.11 1976 pp 649-660 (Original version in

Italian ) http://dx.doi.org/10.13140/RG.2.1.4546.2240 [2] P. Belforte, "Early applications of DWS modeling and simulation."

Techn. Rep., Jan 2009, http://dx.doi.org/10.13140/2.1.3845.9684 [3] A. Fettweis, https://www.researchgate.net/profile/Alfred_Fettweis

[4] P. Belforte, B. Bostica, G. Guaschino, "Time-domain simulation of lossy

interconnection using digital wave networks", ISCAS '82 Rome,

http://dx.doi.org/10.13140/RG.2.1.3019.2804

[5] P. Belforte, G. Guaschino, "Electrical simulation using digital wave

networks," IASTED '85 Paris,

http://dx.doi.org/10.13140/RG.2.1.4447.9207

[6] P. Belforte, "SPRINT & SIGHTS Applications," HDT Handbook 1989,

http://dx.doi.org/10.13140/RG.2.1.3792.5605

[7] P. Belforte, HDT (High Design Technology), "A high-performance

environment for modeling and simulation of digital systems," HP High -

Speed Digital Systems Design and Test Symposium 1993,

http://www.hparchive.com/seminar_notes/1993_High-

Performance_Environment_for_Modelling_and_Simulation_of_Digital_

Systems.pdf

[8] P. Belforte, F. Maggioni, J. Torres, "Characterization and modeling of

MCM (Multi-Chip Module) substrates and components" IEEE

Transactions on Computers, June 1993 ,

http://dx.doi.org/10.13140/RG.2.1.3006.1287, [9] P. Belforte, F. Maggioni, G.Guaschino, G.Morelli "A new system for the

evaluation of telecom hardware robustness," EMC'96 Rome, ETW97,

http://dx.doi.org/10.13140/RG.2.1.2678.4488

[10] P. Belforte, F. Maggioni, F.Canavero, alii of CSELT, HP, HDT,

Politecnico di Torino "Predictive vs. experimental approach for the

evaluation of global robustness of Digital Apparatus," Hewlett-Packard

Design & Integration Symposium Milan, September 25 1997,

http://dx.doi.org/10.13140/RG.2.1.3464.8804

[11] P. Belforte, G. Guaschino "DWS 8.5: Digital Wave Simulator," User

manual 2015, http://dx.doi.org/10.13140/RG.2.1.1892.0160

[12 ] P. Belforte, G. Guaschino "DWV: Digital Wave Viewer," User

manual 2015 http://dx.doi.org/10.13140/RG.2.1.1300.7529

[13] P. Belforte, M. Hendrix, S. Lannutti, R. Larice, "Digital Wave vs. Nodal

Analysis for Circuit Simulation: an experimental comparison" , Jan 2016,

http:/dx.doi.org/10.13140/RG.2.1.4696.3289

[14] P.Belforte, G. Antonini, L. Lombardi, D. Romano, "Digital Wave

formulation of quasi-static Partial Element Equivalent Circuit method",

SPI 2016 20th IEEE Workshop on Signal and Power Integrity, 8-11 May

2016, Turin, Italy,

,http://www.spi2016.org/slides/PEEC_DWS_SPI_2016def2.pdf

[15] A. Fettweis, "Wave Digital Filters: Theory and Practice," Proc. of IEEE,

vol. 74, no. 2, Feb. 1986, pp. 270-327

[16] B. Gustavsen, A. Semlyen, “Rational approximation of frequency

domain responses by vector fitting”, IEEE Trans. Power Delivery, vol.

14, July. 1999, pp. 1052-106

[17] Vector Fitting Website, https://www.sintef.no/projectweb/vectfit/

[18] S. Caniggia, F. Maradei, “Signal Integrity and Radiated Emission,” John

Wiley & Sons Ltd, 2008

[19] Spectrum Software "Micro-Cap 11.0," http://www.spectrum-

soft.com/index.shtm

[20] CST , "Cable Studio," https://www.cst.com/Products/CSTCS

[21] Lawrence Livermore Radiation Laboratory, UC Berkeley, 1964 "Pulse

response of coaxial cables," http://lss.fnal.gov/archive/other/lbl-cc-2-

1b.pdf

[22] J.H.R. Schrader, "Wireline Equalization using Pulse Width Modulation,"

Twente University Thesis 2007,

http://www.nikhef.nl/pub/services/biblio/theses_pdf/thesis_J_R_Schrade

r.pdf, SCHRADER 2007

[23] P. Belforte, "TDR measurements of a RG58 coaxial cable," Tech. Rep.

2013, http://dx.doi.org/10.13140/2.1.5156.6888 [24] P.Belforte, "RG58 coaxial cable: BTM vs analytical models," Tech. Rep.

2013, http://dx.doi.org/10.13140/2.1.4950.3529 [25] P.Belforte, S.Caniggia, "RG58 coaxial cable S-parameters, CST vs DWS

vs Spice," Tech. Rep. 2013, http://dx.doi.org/10.13140/2.1.2197.8406

[26] J. Schutt-Ainé, P. Goh, Y. Mekonnen, J. Tan, F. Al Hawari, P. Liu, W.

Dai "Comparative Study of Convolution and Order Reduction

Techniques for Blackbox Macromodeling Using Scattering Parameters,"

IEEE Trans. Comp Packag Manufact. Techol, vol. 1, no. 10, Oct. 2011,

pp. 1642-1650

[27] P. Goh, M.F. Ain "Fast S-parameter Convolution for Eye Diagram

Simulations of High-Speed Interconnects," SICASE 190 2013

[28] R.B Wu "Fast Eye-Diagram Analysis," National University of Taiwan,

EDAP 2013

[29] P. Belforte, "DWS application videos,"

https://www.youtube.com/playlist?list=PLoyVchXc6Iro65tkestKgtiKbTYzgx

32G

[30] P Belforte, "Research Gate Website,"

https://www.researchgate.net/profile/Piero_Belforte

[31] P.Belforte, F.Maggioni, "DWS model of a complex multi-layer pcb,"

Tech. Rep 2001, http://dx.doi.org/10.13140/RG.2.1.2467.0242 [32] P.Belforte,"Step response of lossy lines," Tech. Rep 2015,

http://dx.doi.org/10.13140/RG.2.1.2287.0882

[33] P.Belforte,"Physical implementation effects on multi-gigabit/sec coaxial

cable performance," Tech. Rep 2015,

https://dx.doi.org/10.13140/RG.2.1.3588.7204 [34] P. Belforte, "DWS story," http://dx.doi.org/10.13140/2.1.3134.1609,

DWS STORY

Piero Belforte Born in Turin in 1947, he

received his Laurea degree in Electronics

Engineering summa cum laude in 1970

from the Politecnico of Turin. From 1970

to 2000 he worked in CSELT, the Research

Center of Telecom Italia as Head of

Switching Techniques Department and

then as Head of Hardware Qualification

Department. His main activity was focused

to state-of-the-art digital switching systems

and qualification tools for the Telecom

network.

In 1975 he started the development of several generations of high-speed

modeling and simulation tools using innovative DSP algorithms for fast

computer simulation of high-speed electronic systems. These tools have been

utilized from the beginning up to present for the design of both state-of-the-

art prototypes and commercial products. In 1988 he founded and directed the

company HDT (High Design Technology) for the development of state-of.-the

art CAE tools for SI/PI/EMC prediction based on digital wave simulation. In

the last years of his activity in CSELT he also created the hardware quality

project THRIS involving several high tech companies and Universities.. From

2001 to present he continues his research activity as Independent Researcher.

In 2012 he started the development of Spicy SWAN, cloud-based circuit

simulation application. In 2016 he started the project PEEC-DWS in

partnership with prof. G. Antonini of University of L'Aquila. He is author of

several publications and international patents in the field of digital electronics

9

with reference to digital switching systems and techniques for telecom

networks, high-speed electronics, signal and power integrity, circuital

modeling and simulation, electromagnetic compatibility and test equipment

for high performance digital systems.

Email: piero.belforte@gmail.com Sites: https://www.linkedin.com/in/pierobelforte https://www.researchgate.net/profile/Piero_Belforte