IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 2, MARCH 2008 627

Digital Predictive Feed-Forward Controller for aDCDC Converter in Plasma Display Panel

Suyong Chae, Student Member, IEEE, Byungchul Hyun, Student Member, IEEE, Pankaj Agarwal,Woosup Kim, Student Member, IEEE, and Bohyung Cho, Senior Member, IEEE

AbstractThis paper describes a new digital control method toenhance the dynamic performance of a dcdc converter used inplasma display panel (PDP). A simple digital PID compensatorwith duty ratio feed-forward control is proposed to minimizethe output voltage variation while the load current is continu-ously changing. The duty ratio feed-forward is calculated usingnoise-free load current information which is predicted by theavailable video data of the PDP. No separate current sensingcircuit is required. A small signal -domain feed-forward modelis derived for the performance analysis and controller design.The proposed control method is experimentally verified on anasymmetrical half bridge dcdc converter which supplies powerto a 42 in PDP.

Index TermsDCDC converter, digital feed-forward control,load current prediction, plasma display panel (PDP).

I. INTRODUCTION

I N the area of flat panel display technology, the plasma dis-play panel (PDP) stands out as a leading device with benefitsincluding large screen size, high contrast ratio, and good colorreproduction capability.

The PDP requires various dc voltages ranging from 100to 200 V to generate driving pulses for displaying image data.The driving pulse sequence is controlled by the digital videoprocessing circuit using the input video data. The PDP powersystem normally consists of at least five dcdc converters tosupply those dc voltages. The important role of the PDP powersystem is to provide a precisely regulated output voltage ofabout 190 V during the sustaining period [1], [2] in order forhigh image quality; namely, bright uniformity.

As the PDP typically uses a periodic pulsed type drivingscheme [3], [4] for displaying the video data, the load currentof the dcdc converter is continuously changing from no loadto full load with a 16.7 ms time constant. The video datacan be another source of information to the dcdc converter,in addition to the output voltage, since the load current is

Manuscript received March 21, 2007; revised July 26, 2007. This work waspresented in part at the IEEE Applied Power Electronics Conference and Ex-position (APEC), Anaheim, CA, 2007. This work was supported by SamsungSDI, Korea. Recommended for publication by Associate Editor S. Y. R. Hui.

S. Y. Chae, B. C. Hyun, W. S. Kim, and B. Cho are with the Departmentof Electrical Engineering and Computer Science, Seoul National University,Seoul 151744, Korea (e-mail : sychae05@snu.ac.kr; novasa@pesl.snu.ac.kr;wskim77@snu.ac.kr; bhcho@snu.ac.kr).

P. Agarwal is with the Visual Display Division, Samsung Electronics, Suwon443742, Korea (e-mail : pankaj_ag_iitk@hotmail.com).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2007.915646

proportional to the level of the video data. The digital con-trol approach is advantageous when applied to the converterbecause the new information is digital and the digital videoprocessing circuit can integrate the controller without an addedcost. The conventional method of meeting the tight regulationspecifications at this load condition is to design a feedbackcompensator with a wide bandwidth and a high dc gain. A twoloop analog feedback control is normally applied to the dcdcconverter in the PDP. However, this control method may havea bandwidth limitation depending on the power stage topology.In the case of the digital control scheme [5], [6], the increaseof bandwidth is additionally limited by the sampling effect andthe computation delay.

The load current feed-forward control has been used to im-prove the transient response and the regulation performance ofdcdc converters. The previous methods [7][12] were designedusing the sensed load current. The feed-forward controller in[13] used the estimated load current, but the estimation wasbased on the sensed output inductor current and the output ca-pacitor current.

The digital predictive control method [14][17] normallyfocuses on the inductor current in implementing a current modecontroller. However, the proposed method uses the predictedload current to enhance the performance of the low speedvoltage mode feedback controller.

This paper introduces a digitally implemented duty ratiofeed-forward control method to improve the load regulationdynamics of the converter. To predict the load current informa-tion, the internal digital video data of the PDP is used withouta separate sensing network. The proposed control method cal-culates the required duty ratio variation from the predicted loadcurrent. This method operates at both continuous conductionmode (CCM) and discontinuous conduction mode (DCM),where the operation mode is decided from the predicted loadcurrent.

This paper is organized as follows. Section II explains the pro-posed feed-forward algorithm including the load current predic-tion method. The small signal -domain model and the stabilityanalysis are introduced in Section III. Section IV presents thesimulated and actual test results of the 400 W asymmetrical halfbridge (AHB) dcdc converter on a 42 in PDP. The conclusionwill be presented in the final section.

II. CONTROL METHOD AND LOAD CURRENT PREDICTION

A. System ConfigurationFig. 1 shows the proposed digital control scheme, which in-

cludes the duty ratio feed-forward and load current prediction

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628 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 2, MARCH 2008

Fig. 1. 400 W AHB dcdc converter for a 42 in PDP.

block, in addition to the digital PID compensator. The outputload current of the next switching period is predicted using thevideo information in the load current prediction block. In thecase of the digital display device like the PDP, the input videodata is rearranged by considering the driving method and driverintegrated circuits (ICs) [18]. After the rearrangement of thevideo information, the dcdc converter supplies current to thePDP for displaying the image on the screen. Hence, there exista constant time interval between the input of video data and thechange of the load current. During this time interval, the loadcurrent of the next switching cycle is predicted using the inputvideo information. The predicted current information is utilizedin the duty ratio feed-forward block to calculate the requiredduty ratio variation with respect to the slowly varying dutyratio . This instantaneous adjustment of the duty ratio forthe load current variation enhances the dynamic performanceof the converter, especially for load regulation. In addition, it isadvantageous for noise immunity, because the proposed methoddoes not use a current sensing circuit to obtain the load currentinformation.

B. Duty Ratio Feed-Forward in CCM

The inductor current waveform in CCM is shown in Fig. 2(a).The predicted load current is denoted by for the thswitching period. It is also possible to determine 1 inadvance because we can use the video information before thechange of the load current. The operation mode is decided bythe following condition:

CCM

DCM (1)

Fig. 2. Inductor current and output load current waveform. (a) Continuous con-duction mode. (b) Discontinuous conduction mode.

where is the steady state duty ration in CCM, is the turnsratio of the transformer and is the switching period.

The relation between the output load current and the dutyratio is

(2)

CHAE et al.: DIGITAL PREDICTIVE FEED-FORWARD CONTROLLER 629

Fig. 3. DCDC converter and input filter of PDP.

Then is given by

(3)

Since is restricted from 0 to 0.5 by the converter char-acteristic, the required duty ratio variation is

(4)

C. Duty Ratio Feed-Forward in DCMThe inductor current waveform in DCM is shown in Fig. 2(b).

The output load current at the 1 th switching period isexpressed by

(5)

If we define the voltage gain as M and the ratio of the inductorcurrent falling period as is given by

(6)

The duty ratio, , can be pre-calculated for the whole DCMrange of 1 . The calculated value of is saved as alookup table in the digital controller and indexed by 1during operation. Furthermore, is obtained by a simplesubtraction process .

D. Load Current PredictionAs the frequency and peak value of the discharge current is

very high (400 kHz, 100 A), an input filter, as shown in Fig. 3,is generally used in the driving circuit of the PDP. The currenttransfer function between and is

(7)

where is the input filter capacitance, is the input filterinductance and is the closed loop output impedance of thedcdc converter. Normally, the output impedance, , is muchsmaller than the impedance of the inductance, , as the con-

Fig. 4. Load current comparison.

verter control loop should be designed to avoid interaction withthe input filter. The current transfer function can be approxi-mated as

where (8)

The discharge current frequency of the PDP coincides withthe frequency of the sustaining driving pulse. The sustainingdriving pulse is generated by the full-bridge panel driver [19],[20] and its sequence is controlled by the digital video pro-cessing circuit of the PDP as shown in Fig. 1. From this digitalsequence control signal (SCS), the timing information of thedischarge current is obtained. The amplitude of the dischargecurrent is proportional to the average signal level (ASL) of thevideo data [4]. The SCS and ASL are digitally transferred to theload current prediction block from the digital video processingcircuit. The discharge current, , is simply modeled as

(9)

where the SCS is a 1 b logic signal and the ASL is an 8 b logicvector. The multiplication of (9) is realized using a simple com-binational logic approach. The state of the SCS is periodicallychecked by a logic comparator and it determines the value of .If the state of the SCS is logic 1, is equal to the value of theASL. Otherwise, is set to be zero.

The -domain representation of with a fast samplingperiod, , is as follows:

(10)

This current transfer function is implemented digitally in theload current prediction block of the controller. The load cur-rent, , is predicted immediately by inputting into the digitalcurrent transfer function, .

Fig. 4 shows the predicted and measured load current in thewhite image mode. It is shown in Fig. 4 that the predicted loadcurrent tracks the real load current to within 0.3A.

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III. SMALL SIGNAL MODELING AND ANALYSIS

A. Small Signal ModelingThe performance and stability of the proposed controller is

analyzed by means of a small signal model. The derivation ofa small signal model is executed for the case in which the con-verter operates in CCM. The AHB dcdc converter in Fig. 1 hastwo state equations within one switching period,

where

(11)

From (11), the averaged discrete time state equation is derivedusing a discrete time modeling method [21]

where

(12)

If we consider a small perturbation from its steady statevalue

, the

Fig. 5. Open loop transfer functions.

open loop small signal -domain model of the converter can becalculated

(13)

The and with parameters used in the experimentalprototype are shown in Fig. 5. It is observed in Fig. 5 that thesecond resonance of and limits the bandwidth increaseof the feedback compensator [22], [23].

The discrete time small signal modeling of the feed-forwardcontroller is derived as follows. The duty ratio and outputload current are composed of a steady state value and a smallperturbation

(14)

Using (14) the linearization of (3) results in a -domain smallsignal representation of the feed-forward block

(15)

The small signal block diagram, including the feed-forwardmodel, , is depicted in Fig. 6.

B. Output Impedance and StabilityThe load unterminated closed loop output impedance, , is

expressed by

(16)

where is the open loop output impedancewith a feed-forward block, , and is theload unterminated loop gain with a digital PID compensator,

CHAE et al.: DIGITAL PREDICTIVE FEED-FORWARD CONTROLLER 631

Fig. 6. Small signal model block diagram.

Fig. 7. Closed loop output impedance comparison.

. In order to examine the influence of the feed-forward con-troller, the closed loop output impedance is plotted using theconverter parameters that are used in the experiment. It is ob-served in Fig. 7 that the feed-forward controller decreases theclosed loop output impedance, which results in a reduced outputvoltage variation in comparison to the conventional digital PIDfeedback controller at the same output load current.

The load, , terminated small signal loop gain, , is de-rived for the stability assessment

(17)

The load unterminated loop gain, , is designed to be stableas shown in Fig. 8. Fig. 8 also shows that the magnitude of theloading factor, , is lower than 0 dB for the entire frequencyrange. From these observations we can judge that the systemis stable without interaction between the converter and the load[24]. Finally, it is confirmed in Fig. 9 that the load terminatedloop gain, , is stable.

Fig. 8. Load unterminated loop gain(T ) and loading factor(T ).

Fig. 9. Load terminated loop gain.

IV. SIMULATIONS AND EXPERIMENTAL RESULTS

A. Converter Implementation

To demonstrate the performance improvement of the pro-posed control algorithm, a 400 W AHB dcdc converter oper-ating at a 70 kHz switching frequency was implemented. Theconverter parameters are listed in Table I. The output capaci-tance, , is selected to maintain the output voltage ripple below0.3 V. The output inductance, , is designed for CCM op-eration above 30% load. The input filter inductance, , andcapacitance, , are the same as that in a 42 in PDP. The dcblocking capacitance, , is the minimum possible value tokeep the dc voltage. The transformer magnetizing inductance,

, is chosen to prevent core saturation and the turns ratio,, is selected to limit the maximum duty ratio to 0.45. The

damping resistance, , and capacitance, , are selected ex-perimentally. The overall conversion efficiency of the prototypeconverter is 92%.

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TABLE IEXPERIMENTAL CONVERTER PARAMETERS

B. SimulationsSimulations are performed by MATLAB SIMULINK to

verify the reduction of the output voltage variation by theproposed controller.

The digital voltage mode PID controller, , is designed forthe loop gain, , to have a 2 kHz bandwidth and 70 phasemargin, as shown in Fig. 9. The bandwidth is selected to avoidthe second resonance of the converter and to guarantee sufficientphase margins while considering the digital sampling effects.The simulation is executed in full white image mode.

Fig. 10 clearly shows that the output voltage variation is re-duced from 3 V to 1.5 V by the proposed control method.

C. ExperimentsThe proposed digital control algorithm is implemented using

a Xilinx FPGA. The control performance is verified experimen-tally on a 42 in PDP.

The feedback compensator is digitally implemented withthe same parameters as the simulation. An analog peak currentmode controlled [25] AHB converter with a 2 kHz bandwidthand 110 phase margin as shown in Fig. 11 is tested for the sakeof comparison. All experiments are executed using a 42 in PDPoperating in full white image mode, at which the PDP requiresthe maximum load current.

It is shown in Figs. 12 and 13 that the proposed methodreduced the output voltage variation by 50% when comparedto the digital PID compensator without the feed-forward

Fig. 10. Simulated output voltage variation.

Fig. 11. Transfer functions of the analog controller.

controller. The waveforms marked as (d) in Figs. 12 and 13represent the duty ratio of the digital controller. The duty ratioin Fig. 12 changes faster than that in Fig. 13 in order to track thecontinuously changing load current. Through this fast tracking,the proposed method demonstrates better performance.

The output voltage variation of the analog peak current modecontrolled AHB converter is shown in Fig. 14. From Figs. 12and 14, it is observed that the output voltage variation of theproposed method is reduced by 25% in comparison with theresult of the two loop analog controller.

The same PDP driving waveforms marked as (c) inFigs. 1214 guarantee that all experiments are performedunder the same conditions.

V. CONCLUSIONThis paper introduces a new digital control method for a

dcdc converter, which utilizes the internal video informationof the PDP. From this video information, the load current ofa dcdc converter is predicted by a digital current transferfunction. No separate current sensing circuit is required. Theproposed method can be implemented without any added cost,

CHAE et al.: DIGITAL PREDICTIVE FEED-FORWARD CONTROLLER 633

Fig. 12. Digital controller with feed-forward: (a) output voltage V (50 V/div),(b) ac coupled V (1 V/div), (c) PDP driving waveform (200 V/div), and (d)duty ratio(1 V/div).

Fig. 13. Digital controller without feed-forward: (a) output voltage V(50 V/div), (b) ac coupled V (1 V/div), (c) PDP driving waveform (200 V/div),and (d) duty ratio(1 V/div).

Fig. 14. Analog peak current mode controller: (a) output voltage V (50 V/div),(b) ac coupled V (1 V/div), and (c) PDP driving waveform (200 V/div).

as there is enough available room in the digital video processingcircuit of the PDP. The simulation and experimental resultsshow that the variation of the output voltage is reduced by 50%compared to the conventional digital PID compensator. Theproposed method also demonstrates an improved performancein comparison to an analog peak current mode controller. Testresults were obtained with a 400 W AHB dcdc converter of a42 in PDP operating in full white image mode.

REFERENCES[1] A. Sobel, Plasma displays, IEEE Trans. Plasma Sci., vol. 19, no. 6,

pp. 10321047, Dec. 1991.[2] J. Y. Lee, J. S. Kim, M. S. So, and B. H. Cho, New energy re-

covery concept for ac PDP sustaining driver using current injectionmethod(CIM), J. Power Electron., vol. 2, no. 3, pp. 189198, Jul.2002.

[3] T. Shinoda and K. Awamoto, Plasma display technology for large areascreen and cost reduction, IEEE Trans. Plasma Sci., vol. 34, no. 2, pp.279286, Apr. 2006.

[4] M. Kasahara, M. Ishikawa, T. Morita, and S. Inohara, New drivesystem for PDPs with improved image quality : Plasma AI, in SIDSymp. Dig., 1999, pp. 158161.

[5] A. Prodic, D. Maksimovic, and R. W. Erickson, Design and imple-mentation of a digital PWM controller for a high-frequency switchingdcdc power converter, in Proc. IEEE Ind. Electron. Conf., 2001, pp.893898.

[6] S. Chattopadhyay and S. Das, A digital current-mode control tech-nique for dcdc converters, IEEE Trans. Power Electron., vol. 21, no.6, pp. 17181726, Nov. 2006.

[7] R. Redl and N. O. Sokal, Near-optimum dynamic regulation of dcdcconverters using feed-forward of output current and input voltage withcurrent-mode control, IEEE Trans. Power Electron., vol. 1, no. 3, pp.181192, Jul. 1986.

[8] M. Karppanen, M. Hankaniemi, T. Suntio, and M. Sippola, Dynamicalcharacterization of peak-current mode-controlled buck converter withoutput-current feedforward, IEEE Trans. Power Electron., vol. 22, no.2, pp. 444451, Mar. 2007.

[9] D. M. Van de Sype, K. D. Gusseme, A. P. M. Van den Bossche, and J. A.Melkebeek, Duty-ratio feedforward for digitally controlled boost PFCconverters, IEEE Trans. Ind. Electron., vol. 52, no. 1, pp. 108115,Feb. 2005.

[10] R. Redl, B. P. Erisman, and Z. Zansky, Optimizing the load transientof the buck converter, in Proc. IEEE Appl. Power Electron. Conf.,1998, pp. 170176.

[11] S. Kanemaru, T. Hamada, T. Nabeshima, T. Sato, and T. Nakano,Analysis and optimum design of a buck-type dc-to-dc converteremploying load current feedforward, in Proc. IEEE Power Electron.Spec. Conf., 1998, pp. 309314.

[12] B. Johansson, Analysis of dcdc converters with current-mode controland resistive load when using load current measurements for control,in Proc. IEEE Power Electron. Spec. Conf., 2002, pp. 165172.

[13] A. V. Peterchev and S. R. Sanders, Load-line regulation with es-timated load-current feedforward : Application to microprocessorvoltage regulators, IEEE Trans. Power Electron., vol. 21, no. 6, pp.17041717, Dec. 2006.

[14] S. Bibian and J. Hua, High performance predictive dead-beat digitalcontroller for dc power supplies, IEEE Trans. Power Electron., vol.17, no. 3, pp. 420427, May 2002.

[15] P. Mattavelli, Digital control of dcdc boost converters with inductorcurrent estimationref, in Proc. IEEE Appl. Power Electron. Conf.,2004, pp. 7480.

[16] H. Peng and D. Maksimovic, Digital current-mode controller fordcdc converters, in Proc. IEEE Appl. Power Electron. Conf., 2005,pp. 899905.

[17] J. Chen, A. Prodic, R. W. Erickson, and D. Maksimovic, Predictivedigital current programmed control, IEEE Trans. Power Electron., vol.18, no. 1, pp. 411419, Jan. 2003.

[18] B. Mercier, E. Benoit, and Y. Blache, A new video storage architecturefor plasma display panels, IEEE Trans. Consum. Electron., vol. 42, no.1, pp. 121127, Feb. 1996.

[19] S. K. Han, G. W. Moon, and M. J. Youn, A resonant energy-recoverycircuit for plasma display panel employing gas-discharge current com-pensation method, IEEE Trans. Power Electron., vol. 20, no. 1, pp.209217, Jan. 2005.

[20] S. K. Han and M. J. Youn, High performance and low cost singleswitch current-fed energy recovery circuits for ac plasma displaypanels, J. Power Electron., vol. 6, no. 3, pp. 253263, Jul. 2006.

[21] D. J. Packard, Discrete Modeling and Analysis of Switching Regula-tors, Ph.D. dissertation, California Inst. Technol., Pasadena, 1976.

[22] S. Korotkov, V. Meleshin, A. Nemchinov, and S. Fraidlin, Small-signal modeling of soft-switched asymmetrical half-bridge dc/dc con-verter, in Proc. IEEE Appl. Power Electron. Conf., 1995, pp. 707711.

[23] B. Choi, W. Lim, S. Bang, and S. Choi, Small-signal analysis and con-trol design of asymmetrical half-bridge dcdc converers, IEEE Trans.Ind. Electron., vol. 53, no. 2, pp. 511520, Apr. 2006.

634 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 2, MARCH 2008

[24] D. Lee, B. Choi, J. Sun, and B. H. Cho, Interpretation and predictionof loop gain characteristics for switching power converters loaded withgeneral load subsystem, in Proc. IEEE Power Electron. Spec. Conf.,2005, pp. 10241029.

[25] R. B. Ridley, A new, continuous-time model for current-mode con-trol, IEEE Trans. Power Electron., vol. 6, no. 2, pp. 271280, Apr.1991.

Suyong Chae (S07) received the B.S. and M.S.degrees in electrical engineering from the KoreaAdvanced Institute of Science and Technology(KAIST), Daejon, in 1998 and 2000, respectively,and is currently pursuing the Ph.D. degree at SeoulNational University, Seoul, Korea.

From 2000 to 2005, he was a Research Engineerwith Samsung SDI where he developed plasma dis-play panel video processing circuits. His research in-terests include digital display power systems and dig-ital control approach of dcdc converters.

Byungchul Hyun (S07) received the B.S. degreefrom KyungPook National University (KNU),Daegu, Korea, in 2004 and the M.S. degree fromSeoul National University (SNU), Seoul, Korea,in 2006 where he is currently pursuing the Ph.D.degree.

His interests include resonant converters, multipleoutput converters, and power factor correction (PFC)circuits.

Pankaj Agarwal received the B.S. degree from theIndian Institute of Technology (IIT), Kanpur, in 2004and the M.S. degree in electrical engineering andcomputer science from Seoul National University,Seoul, Korea, in 2006.

He is currently a Research Engineer in the Ad-vanced R & D Group, Visual Display Division,Samsung Electronics, Suwon, Korea. He has workedon the energy recovery circuits and power supplyof PDP and other capacitive loads. His interestsinclude analysis and design of resonant converters

and inverters especially for display applications.

Woosup Kim (S07) received the B.S. degree fromKwangwoon University, Seoul, Korea, in 2003 and iscurrently pursuing both the M.S. and Ph.D. degreesat Seoul National University.

His interests include HID ballast, resonant con-verters, and flat panel device driver circuits.

Bohyung Cho (M89SM95) received the B.S. andM.S. degrees from the California Institute of Tech-nology, Pasadena, and the Ph.D. degree from the Vir-ginia Polytechnic Institute and State Universtiy (Vir-ginia Tech), Blacksburg, all in electrical engineering.

Prior to his research at Virginia Tech, he workedas a member of technical staff with the Power Con-version Electronics Department, TRW Defense andSpace System Group. From 1982 to 1995, he wasa Professor with the Department of Electrical Engi-neering, Virginia Tech. In 1995, he joined School of

Electrical Engineering, Seoul National University, Seoul, Korea, where he iscurrently a Professor. His research interests include power electronics, mod-eling, analysis and control of spacecraft power processing equipment, and dis-tributed power systems.

Dr. Cho received the 1989 Presidential Young Investigator Award from theNational Science Foundation. He is a member of Tau Beta Pi.