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April 18, 2023April 18, 2023 Concepts in VLSI Des. Lec. 14Concepts in VLSI Des. Lec. 14 11

332:479332:479 Concepts in VLSI Concepts in VLSIDesignDesign

Lecture 14Lecture 14Logic Gate Families and LayoutLogic Gate Families and Layout

Michael L. Bushnell -- CAIP Center and WINLABMichael L. Bushnell -- CAIP Center and WINLABECE Dept., Rutgers U., Piscataway, NJECE Dept., Rutgers U., Piscataway, NJ

• XOR gatesXOR gates• Critical PathsCritical Paths• Logic LayoutsLogic Layouts• Transmission Gate LayoutsTransmission Gate Layouts• Clocked CMOS LogicClocked CMOS Logic• Pass Transistor LogicPass Transistor Logic• Standard Cells and Gate ArraysStandard Cells and Gate Arrays• SummarySummary


Material from: Material from: Principles of CMOS VLSI DesignPrinciples of CMOS VLSI Design

By Neil E. Weste and Kamran EshraghianBy Neil E. Weste and Kamran Eshraghian


XOR GatesXOR Gates• nnMOS XNOR gate: CMOS XOR gate:MOS XNOR gate: CMOS XOR gate:

• Complement Complement AA, , BB, or , or OUTOUT to get an equivalence gate to get an equivalence gate

A

B

A

B

OUTB

OUT

B

A


Causes of Incorrect Gate Causes of Incorrect Gate OperationOperation

• Insufficient or noisy power linesInsufficient or noisy power lines• Gate input noiseGate input noise• Faulty transistorsFaulty transistors• Faulty transistor connectionsFaulty transistor connections• Incorrect transistor ratiosIncorrect transistor ratios• Charge sharing or bad clocking of dynamic gatesCharge sharing or bad clocking of dynamic gates• Ratioed and dynamic gates not used in Ratioed and dynamic gates not used in application specific application specific

integrated circuitsintegrated circuits (ASIC’s) (ASIC’s)– Used in microprocessorsUsed in microprocessors


Critical PathsCritical Paths

• Slowest timing paths that limit a chip’s speedSlowest timing paths that limit a chip’s speed• Affect critical paths at these levels:Affect critical paths at these levels:

– ArchitectureArchitecture– RTL/Logic gate levelsRTL/Logic gate levels– Circuit levelCircuit level– Layout levelLayout level

• RTL/logic level – pipelining, gate types, fanin & fanoutsRTL/logic level – pipelining, gate types, fanin & fanouts• Circuit level – resize transistors to speed upCircuit level – resize transistors to speed up• Layout level – speed up by changing physical layoutLayout level – speed up by changing physical layout• False pathsFalse paths – appear to be critical paths, but cannot propagate – appear to be critical paths, but cannot propagate

transitions due to Boolean value conflictstransitions due to Boolean value conflicts


New Gate NotationNew Gate Notation

• Bubble on transistor closest to gate outputBubble on transistor closest to gate output• Stage ratioStage ratio – increase in transistor size in successive – increase in transistor size in successive

logic stageslogic stages• Use gates with # series inputs of 2-5 for best speedUse gates with # series inputs of 2-5 for best speed


ExampleExample


Worst-Case Rise Delay for m-Worst-Case Rise Delay for m-Input NANDInput NAND


ReformulationReformulation


New Delay ModelNew Delay Model

• ttdrdr = t = tinternal-rinternal-r + k t + k toutput-routput-r

• ttinternal-rinternal-r = R = Rpp C Cgg m r m r

• ttoutput-routput-r = R = Rpp C Cgg 1 + 1 + q (k)q (k)

n kn k

• ttff equation is similar equation is similar

• Assume equal-sized Assume equal-sized nn & & pp transistors transistors

(( ))


Different Delay ModelDifferent Delay Model

• ttrr = t = tff

• NAND gate: NAND gate: RRpp = m R = m Rnn

• WWpp = W = Wnn

mm

• NOR gate: NOR gate: RRnn = m R = m Rpp

• WWnn = W = Wpp

mm


Delay of 1-3 Input GatesDelay of 1-3 Input Gates


Delay of 4-8 Input GatesDelay of 4-8 Input Gates


NAND/NOR Delays Measured NAND/NOR Delays Measured with SPICEwith SPICE


Effective Channel ResistancesEffective Channel Resistances


Choice of Fastest Gate Choice of Fastest Gate ImplementationImplementation


Comparison Results for Different Comparison Results for Different 8-Input AND Gates8-Input AND Gates


Logic Design GuidelinesLogic Design Guidelines

• Avoid long resistive charging / discharging paths in CMOSAvoid long resistive charging / discharging paths in CMOS• Use NAND’s wherever possibleUse NAND’s wherever possible• Place inverters at high fanout nodesPlace inverters at high fanout nodes• Avoid NOR’s in high-speed circuitsAvoid NOR’s in high-speed circuits

– With fanin > 4 and large fanoutWith fanin > 4 and large fanout

• Keep fanout below 5-10Keep fanout below 5-10• Use minimum-sized gates on high fanout nodes to keep Use minimum-sized gates on high fanout nodes to keep CCLL

downdown• Keep rising (falling) edges sharpKeep rising (falling) edges sharp• When power or area is a constraint, use large fanin static gatesWhen power or area is a constraint, use large fanin static gates


CMOS Inverter LayoutsCMOS Inverter Layouts


High Drive InvertersHigh Drive Inverters


NAND Gate Layout GuidelinesNAND Gate Layout Guidelines

• Use metal3 or highest metal layer for power and Use metal3 or highest metal layer for power and groundground

• Place transistors in complex gates:Place transistors in complex gates:– Horizontal channels in diffusionHorizontal channels in diffusion– Vertical poly gatesVertical poly gates– Use “line of diffusion” rule for gate layoutUse “line of diffusion” rule for gate layout


NAND Gate LayoutsNAND Gate Layouts


NOR Gate LayoutsNOR Gate Layouts


Complex Logic Gate LayoutComplex Logic Gate Layout


XNOR LayoutsXNOR Layouts


Full-Custom Density Full-Custom Density ImprovementImprovement

1.1. Route wires over cellsRoute wires over cells2.2. Use merged source/drain connectionsUse merged source/drain connections3.3. Use white space in sparse gatesUse white space in sparse gates4.4. Use smaller, optimal device sizesUse smaller, optimal device sizes


Reducing Reducing CCLL• Use better physical designUse better physical design


Inferior Gate LayoutInferior Gate Layout


Superior Gate LayoutSuperior Gate Layout

• Less Less CC on output node on output node


Transmission Gate LayoutsTransmission Gate Layouts


Two-Input MUXTwo-Input MUX


Standard (Sandia) CellsStandard (Sandia) Cells

• Fixed height (pitch)Fixed height (pitch)• Width varies with gate functionWidth varies with gate function• Automatically placed in rows and wires routed by Automatically placed in rows and wires routed by

Cadence Envisia toolCadence Envisia tool


Example Standard CellExample Standard Cell


More Standard Cell LayoutsMore Standard Cell Layouts


Gate Array (Sea of Gates) LayoutGate Array (Sea of Gates) Layout


Sea of Gates LayoutSea of Gates Layout


Gate Array LayoutsGate Array Layouts• Isolate gates from each other with vertical poly strips Isolate gates from each other with vertical poly strips

tied to tied to VVSSSS ( (VVDDDD))


Clocked CMOS Dynamic LogicClocked CMOS Dynamic Logic

CC22MOS – Used to:MOS – Used to:• Interface with dynamic CMOS logicInterface with dynamic CMOS logic• Same input Same input CC as static CMOS – longer as static CMOS – longer ttrr & & ttff

• Faster if clocking transistors at centerFaster if clocking transistors at center• Better for hot eBetter for hot e---- problems if clock transistor is next to problems if clock transistor is next to

groundground– CLOCKCLOCK is last input to change is last input to change– However, this defeats the isolation purpose of CHowever, this defeats the isolation purpose of C22MOSMOS


Clocked CMOS LogicClocked CMOS Logic

CLKCLK


SummarySummary

• XOR gatesXOR gates• Critical PathsCritical Paths• Logic LayoutsLogic Layouts• Transmission Gate LayoutsTransmission Gate Layouts• Clocked CMOS LogicClocked CMOS Logic• Pass Transistor LogicPass Transistor Logic• Standard Cells and Gate ArraysStandard Cells and Gate Arrays

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