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Direct Interface Bus (DIB) Intel®Stratix® 10 FPGA IP User Guide

Updated for Intel® Quartus® Prime Design Suite: 20.2

IP Version: 19.3.0

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Contents

1. About the DIB Intel® Stratix® 10 FPGA IP User Guide.....................................................3

2. About the DIB Intel Stratix 10 FPGA IP...........................................................................42.1. Release Information...............................................................................................42.2. Device Support for DIB Intel Stratix 10 FPGA IP.........................................................42.3. DIB Intel Stratix 10 FPGA IP Features.......................................................................52.4. Latency................................................................................................................6

3. Functional Description.................................................................................................... 73.1. Bypass Mode.........................................................................................................8

3.1.1. AUX Channel Settings.................................................................................93.2. Asynchronous Mode............................................................................................. 103.3. Synchronous Mode...............................................................................................12

3.3.1. Same Rate Synchronous Mode...................................................................14

4. Creating and Parameterizing the Intel FPGA IP............................................................ 164.1. IP Catalog and Parameter Editor............................................................................ 164.2. Creating a New Intel Quartus Prime Project............................................................. 164.3. Parameterizing and Generating the IP.....................................................................174.4. Compiling the DIB Intel Stratix 10 FPGA IP Design................................................... 174.5. Programming an FPGA Device................................................................................18

5. Designing with the DIB Intel Stratix 10 FPGA IP.......................................................... 195.1. Reset Architecture................................................................................................195.2. Clocking in Asynchronous and Synchronous Modes................................................... 19

5.2.1. Clocking Options......................................................................................205.2.2. Clock Synchronization...............................................................................22

5.3. Timing Closure.................................................................................................... 235.3.1. Timing Transfer for Bypass Mode................................................................245.3.2. Timing Transfer for TDM Modes..................................................................25

5.4. Setting Bypass, Asynchronous, and Synchronous Modes in One DIB Instance...............25

6. DIB Intel Stratix 10 FPGA IP Interface......................................................................... 276.1. DIB Intel Stratix 10 FPGA IP Clocks........................................................................ 276.2. DIB Intel Stratix 10 FPGA IP User Interface Signals.................................................. 28

7. DIB Intel Stratix 10 FPGA IP Parameters......................................................................31

8. Document Revision History for the DIB Intel Stratix 10 FPGA IP User Guide................ 33

A. Die-to-Die Mapping.......................................................................................................34

B. Example Pin Locations for One DIB Channel................................................................. 48

Contents

Direct Interface Bus (DIB) Intel® Stratix® 10 FPGA IP User Guide Send Feedback

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1. About the DIB Intel® Stratix® 10 FPGA IP User GuideThis user guide provides the features, architecture description, steps to instantiate,and guidelines to design the DIB Intel® Stratix® 10 FPGA IP, specifically for IntelStratix 10 GX 1SG10M variant.

Intended Audience

This document is intended for:

• Design architect to make IP selection during system level design planning phase

• Hardware designers when integrating the IP into their system level design

• Validation engineers during system level simulation and hardware validation phase

Related Documents

The following table lists other reference documents which are related to the DIBInterface Intel Stratix 10 IP.

Table 1. Related Documents

Reference Description

Intel Stratix 10 GX/SX Device Overview Provides information about Intel Stratix 10 GX 10M variant.

Intel Stratix 10 Device Data Sheet Provides information about the electrical characteristics,switching characteristics, configuration specifications, andtiming for Intel Stratix 10 devices.

Direct Interface Bus (DIB) Intel Stratix 10 FPGA IP ReleaseNotes

Lists the changes made in a particular release.

Acronyms and Glossary

Table 2. Acronym List

Acronym Expansion

DIB Direct Interface Bus

DUT Device under test

TDM Time-division multiplexing

TX Transmitter

RX Receiver

Table 3. Glossary List

Term Description

Time-division multiplexing (TMD) Method of transmitting multiple data signals over one channel in a series of timeslots.

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Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/orother countries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.

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2. About the DIB Intel Stratix 10 FPGA IPThe Direct Interface Bus (DIB) Intel Stratix 10 FPGA IP enables direct communicationbetween the two dies in a Intel Stratix 10 GX 10M variant.

The Intel Stratix 10 GX 10M variant has two dies. Each die is configured separately.The connection that the DIB Intel Stratix 10 FPGA IP provides between the two dies isstatically set at configuration time.

• Each DIB instance must have at least one pin location assigned to allow for otherpin locations to be automatically assigned.

• The two dies in a Intel Stratix 10 GX 10M variant are identical; die 1 is rotated180 degrees to die 2.

2.1. Release Information

IP versions are the same as the Intel Quartus® Prime Design Suite software versionsup to v19.1. From Intel Quartus Prime Design Suite software version 19.2 or later, IPcores have a new IP versioning scheme.

The IP version (X.Y.Z) number may change from one Intel Quartus Prime softwareversion to another. A change in:

• X indicates a major revision of the IP. If you update your Intel Quartus Primesoftware, you must regenerate the IP.

• Y indicates the IP includes new features. Regenerate your IP to include these newfeatures.

• Z indicates the IP includes minor changes. Regenerate your IP to include thesechanges.

Table 4. Direct Interface Bus (DIB) Intel Stratix 10 FPGA IP Release Information

Item Description

IP Version 19.3.0

Intel Quartus Prime Pro Edition Version 20.2

Release Date 2020.06.22

Related Information

Direct Interface Bus (DIB) Intel Stratix 10 FPGA IP Release Notes

2.2. Device Support for DIB Intel Stratix 10 FPGA IP

The IP supports only the Intel Stratix 10 GX 10M variant.

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Table 5. Intel Device Support

Device Support Level

Intel Stratix 10 GX (1SG10M) Final

The following terms define IP core support levels for Intel FPGA IP cores:

• Advance support—the IP core is available for simulation and compilation for thisdevice family. Timing models include initial engineering estimates of delays basedon early post-layout information. The timing models are subject to change assilicon testing improves the correlation between the actual silicon and the timingmodels. You can use this IP core for system architecture and resource utilizationstudies, simulation, pinout, system latency assessments, basic timing assessments(pipeline budgeting), and I/O transfer strategy (data-path width, burst depth, I/Ostandards tradeoffs).

• Preliminary support—the IP core is verified with preliminary timing models forthis device family. The IP core meets all functional requirements, but might still beundergoing timing analysis for the device family. It can be used in productiondesigns with caution.

• Final support—the IP core is verified with final timing models for this devicefamily. The IP core meets all functional and timing requirements for the devicefamily and can be used in production designs.

2.3. DIB Intel Stratix 10 FPGA IP Features

The DIB Intel Stratix 10 FPGA IP offers three modes of operation: Bypass,Asynchronous, and Synchronous.

The DIB Intel Stratix 10 FPGA IP includes the following features:

• Time-division multiplexing (TDM) ratio

— Asynchronous mode: 1:1, 2:1, or 4:1

— Synchronous mode: 1:1, 2:1, or 4:1

• Maximum transfer clock rate of 400 MHz (Asynchronous and Synchronous modes)

• Bypass transfer latency of 2.5 ns (through direct interface bus only)

• Three subsystems; each subsystem consists of 24 standard channels and 1 AUXchannel

• Four banks per channel

• Maximum 22 I/Os per bank for Bypass mode and 20 I/Os for Asynchronous andSynchronous modes

• Read and Write I/Os set per bank

Table 6. Total I/Os Available

Mode TDM Ratio Total I/Os

Bypass Not applicable 6,564

Asynchronous or Synchronous 1:1 5,760

2:1 11,520

4:1 23,040

2. About the DIB Intel Stratix 10 FPGA IP

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Send Feedback Direct Interface Bus (DIB) Intel® Stratix® 10 FPGA IP User Guide

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2.4. Latency

For TDM modes, the latency for each TDM case includes the core-to-periphery andperiphery-to-core timing closures for both TX and RX instances. The latency numberdoes not include potential pipe stages needed to achieve a required maximumfrequency.For bypass modes, the latency number includes only the latency across theDIB interface (hard wire).

Table 7. Latency

DIB OperationMode

DIB ClockFrequency (MHz)

System/DUTClock Frequency

(MHz)

Hard TDM Ratio DIB Clock/System Clock

Ratio

DIB Pin-to-PinLatency (ns) (1)

Bypass Not Applicable Not Applicable Not Applicable Not Applicable 2.5

Synchronous 400 100 4:1 4:1 5–12.5 (2)

200 2:1 2:1 5–7.5 (2)

400 4:1 1:1 5

400 2:1 1:1 5

300 300 4:1 1:1 6.7

200 200 4:1 1:1 10

(1) Latency without pipe stage.

(2) The latency depends on the pointer value of the hardened TDM, in DIB clock cycles; 1 cycle =2.5 ns, 2 cycles = 5 ns, and so on.

2. About the DIB Intel Stratix 10 FPGA IP

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3. Functional DescriptionThe DIB Intel Stratix 10 FPGA IP provides three direct interface bus subsystems perIntel Stratix 10 GX 10M die.

Every DIB subsystem contains 24 standard channels, and the bypass operation modealso contains an extra AUX channel. Each channel has four banks, and each bankcontains 22 or 20 usable I/Os, depending on the mode of the operation.

The DIB Intel Stratix 10 FPGA IP provides three modes of operation for each DIBchannel instance:

• Bypass Mode

• Synchronous Mode

• Asynchronous Mode

Figure 1. DIB Intel Stratix 10 FPGA IP Interface Connections

dib[95:0]_ch23_x1y2 23DIB

SubsystemY2

0

23DIB

SubsystemY1

0

23DIB

SubsystemY0

0

dib_aux[95:0]_x1y2

dib[95:0]_ch0_x1y2

dib[95:0]_ch23_x1y1

dib_aux[95:0]_x1y1

dib[95:0]_ch0_x1y1

dib_aux[95:0]_x1y0

dib[95:0]_ch0_x1y0

dib[95:0]_ch23_x1y0

U2 U1

dib[95:0]_ch0_x1y0

dib_aux[95:0]_x1y0

dib[95:0]_ch23_x1y0

dib[95:0]_ch0_x1y1

dib_aux[95:0]_x1y1

dib[95:0]_ch23_x1y1

dib_aux[95:0]_x1y2

dib[95:0]_ch23_x1y2

dib[95:0]_ch0_x1y2

...

...

...

...

...

...

...

...

...

...

...

...

...

...

0DIB

SubsystemY1

23

0DIB

SubsystemY0

23

0DIB

SubsystemY2

23

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Figure 2. DIB Subsystem (24 Standard Channels and 1 AUX Channel)

U2 U1

dib[95:0]_ch23_x1y{0,1,2}

dib[95:0]_ch0_x1y{0,1,2}

dib_aux[95:0]_x1y{0,1,2}

.....................................

dib[95:0]_ch0_x1y{2,1,0}

dib[95:0]_ch23_x1y{2,1,0}

dib_aux[95:0]_x1y{2,1,0}

.....................................

Figure 3. Single DIB Channel

U2 U1

Bank 3 dib_pad_3[23:0]



dib_clkdib_ready_niopll_lockedrem_clksys_clk


dib_clkdib_ready_niopll_locked

rem_clksys_clk

core_rx_data_3[81:0]core_tx_data_3[81:0]




Bank 0dib_pad_0[23:0]






core_rx_data_3[81:0]core_tx_data_3[81:0]Bank 3dib_pad_3[23:0]

3.1. Bypass Mode

In Bypass mode, the DIB acts as a wire connection between dies.

The Bypass mode includes the following features:

• The propagation delay between dies is the wire delay.

• The latency between DIB pins is 2.5 ns.

• The directional granularity is at the bank level.

• This mode does not require a DIB clock.

• Use appropriate input or output delay constraints during Intel Quartus Primecompilation to accommodate the interface (refer to Timing Transfer for BypassMode on page 24).

• Enables both standard and AUX channels.

3. Functional Description

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Figure 4. Bypass Mode Block Diagram

DIB DIB

U2 U1

Figure 5. Bypass Mode Timing DiagramThe IP treats the connection between the TX die and RX dies as a wire signal. Ensure that the RX DUT clockrising edge (with respect to the TX DUT clock rising edge) accounts for the time delay from the TX side flip flop,across the interface, and to the receiving flip flop.

A1

TX Die

RX Die

DUT Clock

TX IO1

TX IO2

TX IO3

TX IOn

DUT Clock

RX IO1

RX IO2

RX IO3

RX IOn

A2 A3 A4 A5 A6 A7 A8

A1 A2 A3 A4 A5 A6 A7

B1 B2 B3 B4 B5 B6 B7

C1 C2 C3 C4 C5 C6 C7

D1 D2 D3 D4 D5 D6 D7

B1 B2 B3 B4 B5 B6 B7 B8

C1 C2 C3 C4 C5 C6 C7 C8

D1 D2 D3 D4 D5 D6 D7 D8

....

....

3.1.1. AUX Channel Settings

You can enable any combination settings for the AUX channel with certain restrictions.


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Follow these restrictions:

• Banks 0 and 3 are 22 bits wide and configurable as TX or RX.

• Bank 1 has a total width of 17 bits:

— 16 bits are for TX data only

— 1 bit is reserved for clock

• Bank 2 has a total width of 17 bits:

— 16 bits are for RX data only

— 1 bit is reserved for clock

Figure 6. AUX Channel Settings

3.2. Asynchronous Mode

In Asynchronous mode, the DIB uses the hard TDM provided by the IP.

The Asynchronous mode includes the following features:

• Use this mode when 1:1, 2:1, or 4:1 TDM multiplexing is required and no softTDM logic is required.

• System clock is not used.

— The DIB clock and DUT clock have a synchronous relationship.

— You may use your own asynchronous DUT clock, but the dut_clk input to aDIB instance must be connected to a clock of the ratio selected in theparameter editor.

• The DIB subsystem TDM block always ensures that all RX ports (four ports from4:1 TDM, two ports from 2:1 TDM, or single port from 1:1 TDM) are available tobe sampled in the next system clock (or DUT clock) on the RX side.

— The DIB TDM multiplexer halts the multiplexer select at the last data inputuntil all data are sampled at the RX system clock.

— When the data sampling is complete, the multiplexer select rolls back to theinitial location for a new phase of data on the TX side.

• You can connect the DIB clock to the DUT flip flops only in an asynchronousmanner.


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Figure 7. Asynchronous Mode Setup

Channel0

Clock A (DUT) Clock A (DUT)DIB Clock

(400 MHz)DIB Clock

(400 MHz)

DIB 4:1TDM TX

Block

IOPLL IOPLL

Die A Core Fabric Die A DIB Die B DIB Die B Core Fabric

DIB 4:1TDM RX

Block

Figure 8. Asynchronous Mode Timing Diagram

A0 A2A1

B0 A2B1

C0 C2C1

D0 D2D1

A0 A2A1

B0 B2B1

C0 C2C1

D0 D2D1

A0 A2A1

B0 B2B1

C0 C2C1

D0 D2D1

D0 D1

C0 C1

B0 B1

A0 A1

D0C0B0A0 D2B1A1 D1C1 D2A2 C2

D0C0B0A0 D2B1A1 D1C1 D2A2 C2

TX DUT Clock

TX Core 1

TX Core 2

TX Core 3

TX Core 4

TX DIB Clock

DIB TX1 Register

DIB TX2 Register

DIB TX3 Register

DIB TX4 Register

DIB Serialized Data

RX DIB Clock (Source Sync)

Inte

rnal

DIB Deserialized Data

DIB RX1 Register

DIB RX2 Register

DIB RX3 Register

DIB RX4 Register

RX DUT Clock

RX Core1

RX Core2

RX Core3

RX Core4

Inte

rnal

First rising edge starts counter


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3.3. Synchronous Mode

Opt for Synchronous mode if you want the DIB to use your own soft TDM logic.

The Synchronous mode includes the following features:

• Use this mode when 1:1, 2:1, or 4:1 TDM multiplexing is required with soft TDMlogic.

• The transfer from the DIB to the soft TDM logic is synchronous

• The DIB clock and system clock have a synchronous relationship.

— The ratio of the DIB clock and system clock is equal to the TDM ratio, withsome exceptional cases (refer to Same Rate Synchronous Mode on page 14).

— There is no requirement for a system/DUT clock or DIB/DUT clock relationship.

• The DIB subsystem TDM multiplexers continue to sample and deliver withouthalting on every dib_clk signal.

• The soft TDM logic maintains data coherency across dies to ensure that all DUTdata is successfully transferred to the other die.

• You can reduce latency by one clock cycle by turning on the Reduce Sync ModeP2C Latency parameter.

Note: You may face difficulty in closing timing when you enable this parameter.

• The RX die generates the system clock for the soft TDM logic on the rem_clk pin.

— rem_clk is a divided version of dib_clk transmitted from the TX side.

— The TDM ratio you select in the parameter editor determines the division. Forexample, TDM ratio 2:1 sets rem_clk to be half of dib_clk.

Figure 9. Synchronous Mode Setup with 4:1 Soft TDM and 2:1 DIB (Hard) TDMThis setup is based on the settings of 4:1 Soft TDM, 2:1 DIB TDM.


200 MHz rem_clk

Demux A’

Demux B’Level 2 Mux B

Level 2 Mux A

MultipleAsynchronousDUT Domain


System Clock200 MHz

400 MHzDIB Clock

DIBData

1 ChannelGranularity

IOPLL

DIB 2:1TDM TX

Block4:1Mux

4:1Mux

1:4Demux

DIB 2:1TDM RX

Block

ClockDivider

1:4Demux

Channel0


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Figure 10. Synchronous Mode with 4:1 Soft TDM and 2:1 DIB (Hard) TDM TimingDiagramThis setup is based on the settings of 4:1 Soft TDM, 2:1 DIB TDM.

B2B1 A4B1-2B4B3

A2A1 A1-2A4A3

B2B1 B1-2B4B3

A2A1 A1-2A4A3

A2A1 A4 A2-2A1-2A3

B2B1 B4 B2-2B1-2B3

A1 B1 A2 B2 A3 B3 A4 B4 A1-2 B1-2 A2-2 B2-2

0 1 0 1 0 1 0 1 0 1 0 1

A2_B2_sel A3_B3_sel A4_B4_selA1_B1_sel A2_B2_sel A2_BA1_B1_sel

B2 B3 B4 B2_2 B3B1_2

A2 A3 A4 A2_2 A3A1_22 clock latency

2 clock latency

System Clock

DIB Clock

Level2 Mux A Output

Level2 Mux B Output

Level2 Mux Select

TDM Input1 TX

TDM Input2 TX

TDM Output1 RX reg

TDM Output2 RX reg

Demux A’ Input

Demux B’ Input

TDM Mux Select

RX DIB Clock(Source Sync)

rem_clk(dib_clk/2)

DIB Data

A1

B1

Figure 11. Synchronous Mode Setup with 4:1 Soft TDM and 4:1 DIB (Hard) TDMThis setup is based on the settings of 4:1 Soft TDM, 4:1 DIB TDM.


100 MHz (Use /4)rem_clk Used as System Clock on RX Side

Demux A’

Demux B’

Demux C’

Demux D’

Level2 Mux C

Level2 Mux B

Level2 Mux A

Level2 Mux D



System Clock100 MHz

400 MHzDIB Clock

DIB Data


IOPLL

DIB 4:1TDM TX

Block

4:1Mux

4:1Mux

4:1Mux

4:1Mux

1:4Demux

DIB 4:1TDM RX

Block

ClockDivider

1:4Demux

1:4Demux

1:4Demux


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Figure 12. Synchronous Mode with 4:1 Soft TDM and 4:1 DIB (Hard) TDM TimingDiagramThis setup is based on the settings of 4:1 Soft TDM, 4:1 DIB TDM, and 1:1 DIB clock.

A4 B4

2 3

B2B1 B4B3

B2B1 B4B3

C2C1 C4C3

D2D1 D4D3

A2A1 A4A3

D2D1 D4D3

C2C1 C4C3

A2A1 A4A3

A2A1 A4 A1-2A3

C2C1 C4 C1-2C3

D2D1

A1 B1

D4 D1-2D3

C1 D1 A2 B2 C2 D2 A3 B3 C3 D3 C4 D4 A1-2 B1-2 C1-2

0 1 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2

A2A1 A4 A1-2A3

B2B1 B4 B1-2B3

C2C1 C4 C1-2C3

D2D1 D4 D1-2D3

System Clock

DIB Clock

Level2 Mux A Output

Level2 Mux B Output

Level2 Mux C Output

Level2 Mux D Output

TDM Input1 TX

TDM Input2 TX

TDM Input3 TX

TDM Input4 TX

TDM Output1 RX reg

TDM Output2 RX reg

TDM Output3 RX reg

TDM Output4 RX reg

Demux A’ Input

Demux B’ Input

Demux C’ Input

Demux D’ Input

TDM Mux Select

RX DIB Clock(Source Sync)

rem_clk(dib_clk/4)

DIB Data

2 clock latency

B2B1 B4 B1-2B3

3 clock latency

4 clock latency

5 clock latency

3.3.1. Same Rate Synchronous Mode

In special cases, the DIB subsystem allows for a 1:1 ratio between the DIB clock andsystem clock, even when you set the hard TDM to ratios of 2:1 or 4:1.

This use case facilitates the addition of pipeline stages in the design of your soft TDMlogic design.

Note: This use case may negatively impact power usage because most portions of the logicrun at 400 MHz. This in turn may congest routing around the interface to the DIB IntelStratix 10 FPGA IP due to the lesser timing budget. You can partially mitigate theseimpacts by running the DIB clock at a slower rate, such as 300 MHz.


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Figure 13. Synchronous Mode Setup with 1:1 DIB Clock and System Clock RatioThis setup is based on the settings of 4:1 soft TDM and 4:1 DIB (hard) TDM.


In A1In A2In A3In A4

In B1...In B4

400 MHz (Use /1)

Demux A’

Demux B’

Demux C’

Demux D’

Level 2 Mux A

Level 2 Mux B

Level 2 Mux C

Level 2 Mux D


MultipleAsynchronousDUT DomainIn C1...

In C4

In D1...In D4

sys_clk400 MHz

400 MHzDIB Clock

DIB Data


IOPLL

DIB 4:1TDM TX

Block

4:1LeveI 2

Mux

4:1LeveI 2

Mux

4:1LeveI 2

Mux

4:1LeveI 2

Mux

Level 21:4

Demux

Level 21:4

Demux

Level 21:4

Demux

Level 21:4

Demux

DIB 4:1TDM RX

Block

ClockDivider

(/1.../16)

Level 2Mux

Level 2Mux 16:1

Figure 14. Synchronous Mode with 1:1 DIB Clock and System Clock Ratio TimingDiagramThis setup is based on the settings of 4:1 soft TDM and 4:1 DIB (hard) TDM.

A2A1 A4 A1-2A3

A2A1 A4 A1-2A3

A2A1 A4 A1-2A3

B2B1 B4 B1-2B3

B2B1 B4 B1-2B3

C2C1 C4 C1-2C3

C2C1 C4 C1-2C3

D2D1 D4D3

D2D1 D4 D1D3

B2B1 B4 B1B3

C2C1 C4C3

D2D1 D4D3

D2D1 D4D3

C2C1 C4C3

B2B1 B4B3

A2A1 A4 A1A3

A4 B4A1 B1 C1 D1 A2 B2 C2 D2 A3 B3 C3 D3 C4 D4 A1-2 B1-2 C1-2 D1-2

0 10 1 2 3 0 1 2 3 0 1 2 3 2 3 0 1 2 3

DIB Clock/System Clock

Level2 Mux A Output

Level2 Mux B Output

Level2 Mux C Output

Level2 Mux D Output

Level2 Mux Select

TDM Input1 TX

TDM Input2 TX

TDM Input3 TX

TDM Input4 TX

TDM Mux Select

DIB Data

RX Clock(Source Sync)

TDM Output1 RX reg

TDM Output2 RX reg

TDM Output3 RX reg

TDM Output4 RX reg

Demux A’ Input

Demux B’ Input

Demux C’ Input

Demux D’ Input

B4_sel C4_selB1_sel C1_sel D1_sel A2_sel B2_sel C2_sel D2_sel A3_sel B3_sel C3_sel D3_sel A4_sel D4_sel A1_sel B1-sel C1-sel D1-sel A2-selA1_sel

2 clock latency

2 clock latency

2 clock latency


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4. Creating and Parameterizing the Intel FPGA IPUse the Intel FPGA IP design flow to get started with the DIB Intel Stratix 10 FPGA IP.

The Intel FPGA IP Library is installed as part of the Intel Quartus Prime installationprocess. You can select and parameterize any Intel FPGA IP from the library. Intelprovides an integrated parameter editor that allows you to customize the DIB IntelStratix 10 FPGA IP to support a wide variety of applications. The parameter editorguides you through the setting of parameter values and selection of optional ports.

4.1. IP Catalog and Parameter Editor

The IP Catalog displays the IP cores available for your project, including Intel FPGA IPand other IP that you add to the IP Catalog search path. Use the following features ofthe IP Catalog to locate and customize an IP core:

• Filter IP Catalog to Show IP for active device family or Show IP for alldevice families. If you have no project open, select the Device Family in IPCatalog.

• Type in the search field to locate any full or partial IP core name in IP Catalog.

• Right-click an IP core name in IP Catalog to display details about supporteddevices, to open the IP core's installation folder, and for links to IP documentation.

• Click Search for Partner IP to access partner IP information on the web.

The parameter editor prompts you to specify an IP variation name, optional ports, andoutput file generation options. The parameter editor generates a top-level IntelQuartus Prime IP file (.ip) for an IP variation in Intel Quartus Prime Pro Editionprojects.

4.2. Creating a New Intel Quartus Prime Project

You can create a new Intel Quartus Prime project with the New Project Wizard.Creating a new project allows you to do the following:

• Specify the working directory for the project.

• Assign the project name.

• Designate the name of the top-level design entity.

1. Launch the Intel Quartus Prime software.

2. On the File menu, click New Project Wizard.

3. In the New Project Wizard: Directory, Name, Top-Level Entity page, specifythe working directory, project name, and top-level design entity name. Click Next.

4. In the New Project Wizard: Add Files page, select the existing design files (ifany) you want to include in the project. Click Next.

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5. In the New Project Wizard: Family & Device Settings page, select the devicefamily and specific device you want to target for compilation. Click Next.

6. In the EDA Tool Settings page, select the EDA tools you want to use with theIntel Quartus Prime software to develop your project.

7. Review the summary of your chosen settings in the New Project Wizard window,then click Finish to complete the Intel Quartus Prime project creation.

4.3. Parameterizing and Generating the IP

Refer to DIB Intel Stratix 10 FPGA IP Parameters on page 31 for the IP parametervalues and description.

1. In the IP Catalog (Tools ➤ IP Catalog ➤ Miscellaneous), locate and double-click the Direct Interface Bus (DIB) Intel Stratix 10 FPGA IP.

2. Specify a top-level name for your custom IP variation. This name identifies the IPvariation files in your project. If prompted, also specify the target Intel FPGAdevice family and output file HDL preference. Click OK.

3. After parameterizing the IP, go to the Example Design tab and click GenerateExample Design to create the simulation testbench. Skip to 5 if you do not wantto generate the design example.

4. Set a name for your <example_design_directory> and click OK to generatesupporting files and scripts.The testbench and scripts are located in the <example_design_directory>/simulation folder.

5. Click Finish or Generate HDL to generate synthesis and other optional filesmatching your IP variation specifications. The parameter editor generates the top-level .ip, .qip or .qsys IP variation file and HDL files for synthesis andsimulation.

The top-level IP variation is added to the current Intel Quartus Prime project. ClickProject ➤ Add/Remove Files in Project to manually add a .qip or .qsys fileto a project. Make appropriate pin assignments to connect ports.

Note: Some parameter options are grayed out if they are not supported in a selectedconfiguration or it is a derived parameter.

4.4. Compiling the DIB Intel Stratix 10 FPGA IP Design

Refer to the Designing with the DIB Intel Stratix 10 FPGA IP on page 19 beforecompiling the DIB Intel Stratix 10 FPGA IP design.

To compile your design, click Start Compilation on the Processing menu in the IntelQuartus Prime software. You can use the generated .ip or .qip file to includerelevant files into your project.

Related Information

Intel Quartus Prime HelpMore information about compilation in Intel Quartus Prime software.

4. Creating and Parameterizing the Intel FPGA IP

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http://quartushelp.altera.com/13.0/master_1.htm


4.5. Programming an FPGA Device

After successfully compiling your design, program the targeted Intel device with theIntel Quartus Prime Programmer and verify the design in hardware. For instructions onprogramming the FPGA device, refer to the Device Programming section in the IntelQuartus Prime Handbook.

Related Information

Device Programming

4. Creating and Parameterizing the Intel FPGA IP

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http://www.altera.com/literature/lit-qts.jsp


5. Designing with the DIB Intel Stratix 10 FPGA IPWhen designing with the DIB Intel Stratix 10 FPGA IP, you need to take into accountcertain considerations to ensure a fully-functioning design. Follow the designguidelines provided.

5.1. Reset Architecture

The DIB subsystem is either in freeze mode or user mode.

Upon power-up, the DIB subsystem enters freeze mode. All the freeze signals fromthe DIB subsystem get asserted when the system asserts the power-on reset signal.During freeze mode, the DIB subsystem is in a safe state and all interface signals tothe core fabric are driven high.

During freeze mode, the DIB I/Os are tri-stated, and the DIB SSM configures theentire DIB subsystem.

For the Intel Stratix 10 GX 10M variant, the external reset is controlled by user logicor your system design.

• You must track all the dib_ready pins from both dies to determine that bothIntel Stratix 10 GX 10M variants are ready for data transactions.

• You should enable the external reset only after all the dib_ready_n pins areasserted.

• Only after enabling the external reset, you enable the cross-die transactions.

5.2. Clocking in Asynchronous and Synchronous Modes

The DIB subsystem requires the fabric clock, sourced from an IOPLL to clock the DIBsubsystem.

The DIB subsystem does not have any PLLs, therefore the clocks come from IOPLLs.

The DIB subsystem sends a source synchronous clock to another DIB subsystem inthe adjacent die (TX or RX). In Synchronous mode, the system clock is synchronous tothe DIB clock.

Both the system clock (if applicable) and the DIB clock should be derived from thesame IOPLL output, and routed to the DCM (core clock multiplexer) nearest to the DIBsubsystem,

• The DCM has a divider that does the division of 1, 2, or 4.

• Sharing the same clock and using the divider within the DCM reduces clockuncertainties.

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Each Intel Stratix 10 GX 10M die contains 24 IOPLLs and you can program each IOPLLto produce nine unique clocks (divided from the PLL's VCO).

On the receiving die, the DIB clock and system clock (if applicable) on the DIB RX coreis derived from the source synchronous clock in the DIB TX core.

• The DIB clock on the RX side runs at the same frequency as the DIB clock on theTX side.

• The DIB clock goes through the clock divider inside the DIB to generate therem_clk port on the RX die.

Each DIB channel has its own independent system clock and associated DIB clock.

• The smallest granularity for the clock domain is per channel.

• The Intel Stratix 10 GX 10M variant parts per die has a total of 72 clock domainsfor the system clock and DIB clock.

Note: Intel recommends that each channel should not have its own unique clock source atthe die level to reduce clock uncertainties.

5.2.1. Clocking Options

Intel recommends two clocking options that you can use as reference for clock routingfrom IOPLLs to DIB instances.

Clocking Option 1

All three DIB subsystems are clocked by a single IOPLL.

The clock network for this option is larger because the network spans across the dieheight.

Advantages of this clock option:

• The divergence point is closer to the DIB subsystem because it is from a singlePLL.

• For timing closure, you need to account for clock uncertainties from thedivergence point to the leaf.

• No clock uncertainties occur when using multiple IOPLLs.

5. Designing with the DIB Intel Stratix 10 FPGA IP

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Figure 15. DIB Clocking Option 1

Divergence

Chip Edge

Chip Edge

DIB Subsytem

DIB Subsytem

DIB Subsytem

PLL

Clocking Option 2

Each DIB subsystem is clocked by its own PLL.

This option is more efficient if the logic clocked by one IOPLL is not required tointeract with the logic clocked by another IOPLL. Cross-PLL interactions incur largerclock uncertainties.

If a DIB subsystem (or even a few channels) is mutually exclusive with the othersections of logic or another DIB subsystem, you can use multiple IOPLLs to clock thelogic driven by those unique clock domains.

• In this case, the clock network span from the divergence point to the leaves isshorter because the network does not need to span across the die height.

• This option also incurs less clock uncertainties.


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Figure 16. DIB Clocking Option 2

Chip Edge

Chip Edge

DIB Subsytem

DIB Subsytem

DIB Subsytem

PLL

PLL

PLL

5.2.2. Clock Synchronization

Intel recommends you to follow the board design guidelines for clock synchronization.

DUT Clock Synchronization between 2 Intel Stratix 10 GX 10M Dies

To synchronize the DUT reference clock, Intel recommends 20 ps.

DIB/System Clock Synchronization between 2 Intel Stratix 10 GX 10M Dies

The DIB clock and the system clock on the DIB RX side derive from the sourcesynchronous clock on the TX side.

• The DIB clock on the DIB RX channel operates at the same frequency as the DIBclock on the DIB TX channel.

• The system clock on the RX dies is a divided clock from the source synchronousDIB clock to match the frequency of the system clock on the TX die. The clockdivider supports division by 1 up to 16.

Note: The duty cycle is 60:40 for the odd divider, and you need to consider thisduty cycle if any negative-edge flops are used.

• The TX version and RX version of the system clock on the same die are notsynchronous because the clocks are from different IOPLLs on different dies.


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Figure 17. Clocking Synchronization Using Different IOPLLs

Channel0



Clock A Clock A (System Clock,Divided Clock from DIB)

DIB 4:1TDM TX

Block

IOPLL


Clock Divider(/1.../16)

DIB 4:1TDM RX

Block

5.3. Timing Closure

You must compile each Intel Stratix 10 GX 10M die instance in the Intel Quartus PrimePro Edition software separately. Separate compilation means that you must configurethe timing closure for each die separately.

Especially in cases when data or clocks are being transferred from one die to another,you may need to use certain budgeting schemes to enable timing closure timing ineach die independently. Only then, the timing closure across the two dies isguaranteed.

Consider the following timing transfers to account for the data transfer from thesystem clock on one die to the system clock on the other die.

• Timing transfer for Bypass mode:

— Core to DIB I/O

— DIB I/O to core

• Timing transfer for TDM Synchronous and Asynchronous modes:

— TX die: Core to DIB or Periphery

— RX die: DIB or Periphery to Core

— Across dies: TDM to TDM


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5.3.1. Timing Transfer for Bypass Mode

In the Bypass mode use case, two different dies, to a respective IOPLL, share a singlereference clock.

Each PLL has the same frequency output clock configuration and the respectivecounters are synchronous in each die. The same frequency allows the data to betransferred synchronously from the clock in one die to the clock in the other die.However, the variations in the dies may affect how well the clocks in each die alignwith each other.

To analyze each die separately, consider these factors:

• The clock uncertainty of one die relative to the clock on the other die must becomputed.

• The available data uncertainty for the transfer across the two dies and the linkmust be computed and budgeted for each die. For example, you may divide theuncertainty up to 40% for each die and 20% for the link.

Given these two factors, you may now create the appropriate SDC constraints for eachdie so that the Intel Quartus Prime Pro Edition software can close timing for each dieindependently.

• For the TX die, create a virtual clock that has the clock uncertainty of the RX die,and then set the appropriate set_output_delay -max andset_output_delay -min constraints relative to the virtual clock thatencompasses the link and data uncertainty in the other die.

• For the RX die, set the appropriate set_input_delay -max andset_input_delay -min constraints.

With these SDC constraints, the Intel Quartus Prime Pro Edition software places androutes the DIB-to-core and core-to-DIB connections to meet the timing requirements.

Note: Intel provides the information to determine the clock and data uncertainties becausethe Timing Analyzer in the Intel Quartus Prime software would not have theinformation.

Figure 18. Timing Closure for Bypass Mode


Clock A

Clock B

Channel1

Channel0

ADependant on

user logicplacement

EDependant on

user logicplacement

BDIB

Latency

DDIB

Latency

CEMIBDelay Clock A

Clock B

IOPLL IOPLL

Set_input_delay max (max A + max B + max C/2)Set_input_delay min (min A + min B + min C/2)

Set_output_delay max (max D + max E + maxC/2)Set_output_delay min (min D + min E + min C/2)


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5.3.2. Timing Transfer for TDM Modes

There are three types of timing transfer in TDM modes.

Figure 19. Timing Closure for TDM Mode

C2

Channel0



Clock A(System Clock) Clock A (System Clock,

Divided Clock from DIB)

DIB 4:1TDM TX

Block

IOPLL


Clock Divider(/1.../16)

DIB 4:1TDM RX

Block

Core-to-Periphery Timing(Intel Prime Quartus) Periphery-to-Core Timing

(Intel Prime Quartus)

Die-to-Die Timing(Closed by Intel)

Table 8. Timing Transfer for TDM Modes

Timing Transfer Description

Core-to-periphery transfer (TX side) A synchronous transfer from the system clock with a flop in the core tothe DIB clock with a flop in the periphery on the same die.The Timing Analyzer in the Intel Quartus Prime software analyzes thispath as a regular path.

Die-to-die transfer Intel determines the timing closure for this path.

Periphery-to-core transfer (RX side) A transfer from the DIB clock from the RX die to the system clock on theRX die.The Timing Analyzer in the Intel Quartus Prime software analyzes thispath as a regular path.

5.4. Setting Bypass, Asynchronous, and Synchronous Modes in OneDIB Instance

You may set each bank, in a channel of four banks, to different DIB modes.

However, be mindful of the following limitations:


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• If you set bank 0 to RX in Bypass mode, and any of the other banks to RX inAsynchronous or Synchronous mode, then pad_0_dib_pad[22] pin cannot betimed, and therefore cannot be used.

• If you set bank 3 to TX in Bypass mode, and any of the other banks to TX inAsynchronous or Synchronous mode, then pad_3_dib_pad[22] pin cannot betimed, and therefore cannot be used.

Note: In these situations, the Intel Quartus Prime software displays a warning message inthe parameter editor and flags a critical warning in the Fitter.


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6. DIB Intel Stratix 10 FPGA IP InterfaceAll the interfaces for each DIB channel are always present. Unused signals are notconnected.

The DIB Intel Stratix 10 FPGA IP has three main interface signals:

• Control

• Data

• DIB Pad

The direction of the DIB pad signals are dynamically generated based on your settingsin the parameter editor.

All standard and AUX channels have the same top-level signals.

Example 1. Top-Level Signals for Each DIB Channel

module my_dib ( output wire [81:0] core_rx_data_0, output wire [81:0] core_rx_data_1, output wire [81:0] core_rx_data_2, output wire [81:0] core_rx_data_3, input wire [81:0] core_tx_data_0, input wire [81:0] core_tx_data_1, input wire [81:0] core_tx_data_2, input wire [81:0] core_tx_data_3, input wire dib_clk, output wire dib_ready_n, input wire iopll_locked, input wire [23:0] dib_pad_0, output wire [23:0] dib_pad_1, input wire [23:0] dib_pad_2, output wire [23:0] dib_pad_3, output wire rem_clk, input wire sys_clk );endmodule

6.1. DIB Intel Stratix 10 FPGA IP Clocks

The DIB Intel Stratix 10 FPGA IP mainly uses four clock signals.

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Table 9. Clocks

Signals Direction

Description Mode

Bypass Asynchronous Synchronous

dib_clk Input Clocks the inter-dielogic.

Tie this signal high(not used).

Tie to the DIB clock(used for TXbanks).

Tie to the DIB clock(used for TXbanks).

sys_clk Input Ratio to the dib_clksignal set to Hard TDMratio. Drives the softTDM interface logic tothe DIB Interface IP.



Tie this signal tothe same PLLsource as the DIBclock ratio set tothe Hard TDM ratio(used for TXbanks).

dut_clk Input Input clock for thestandard DIB channel.


Tie this signal tothe DUT clock(synchronous tothe DIB clock).


Input clock for the AUXDIB channel.

Tie this signal tothe DUT clock(used for TXbanks).

Not applicable. Not applicable.

rem_clk Output Output clock for thestandard DIB channel.

Not used. Not used. Divided version ofthe DIB clockforwarded for theTX die (used assystem clock onthe RX banks).

Output clock for theAUX DIB channel.

DUT clockforwarded from theTX die.

Not applicable. Not applicable.

6.2. DIB Intel Stratix 10 FPGA IP User Interface Signals

The DIB Intel Stratix 10 FPGA IP uses the DIB control, data and DIB pad signals.

Table 10. Control Signals

Signal Width Direction Description

iopll_locked 1 Input When you set the DIB Channel Typeparameter to Standard Channel, this signalconnects to locked IOPLL when using a bankwith TDM.This signal is not applicable if you select AUXChannel.

dib_ready_n 1 Output This signal goes low when the DIB channel isready.

Table 11. DIB Pad Signals


dib_pad_0 24 Input/Output DIB pads for bank 0.The direction of this signal depends on themode of I/O bank 0.

dib_pad_1 24 Input/Output DIB pads for bank 1.

continued...

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The direction of this signal depends on themode of I/O bank 1.



Table 12. DIB RX Data Signals


core_rx_data_0 82 Output Core data RX interface for bank 0.• Bypass: Connect to [21:0]• TDM 1:1: Connect to [21:2], [1:0] reserved• TDM 2:1: Connect to [41:2], [1:0] reserved• TDM 4:1: Connect to [81:2], [1:0] reservedThe direction of this signal depends on themode of I/O bank 0.




Table 13. DIB TX Data Signals


core_rx_data_0 82 Input Core data TX interface for bank 0.• Bypass: Connect to [21:0]• TDM 1:1: Connect to [21:2], [1:0] reserved• TDM 2:1: Connect to [41:2], [1:0] reserved• TDM 4:1: Connect to [81:2], [1:0] reserved

continued...


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The direction of this signal depends on themode of I/O bank 0.

core_rx_data_1 82 Input Core data TX interface for bank 1.• Bypass: Connect to [21:0]• TDM 1:1: Connect to [21:2], [1:0] reserved• TDM 2:1: Connect to [41:2], [1:0] reserved• TDM 4:1: Connect to [81:2], [1:0] reservedThe direction of this signal depends on themode of I/O bank 0.




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7. DIB Intel Stratix 10 FPGA IP ParametersUse the DIB Intel Stratix 10 FPGA IP parameter editor to configure your design.

Table 14. General Tab Parameters

Parameter Value Description

Speed grade – Speed grade of the selected Intel Stratix 10 GX 10M variant (1SG10M). Thesoftware automatically sets the speed grade based on the selected variant.

DIB Channel Type • StandardChannel

• AUX Channel

Select the desired channel.• Standard Channel: Available in all three modes.• AUX Channel: Available in bypass mode.

Enable DIB bank0–3

On, Off Turn on to enable a bank.

SynchronizationMode

• Synchronous• Asynchronous

Select the desired TDM mode.• Synchronous: Select this mode when you want to use soft TDM.• Asynchronous: Select this mode when you want to use hard TDM.

DIB to SystemClock Ratio

1, 2, 4 Available only when you select Synchronous mode.Select the DIB clock to system clock ratio for soft TDM.

Reduce SyncMode P2C Latency

On, Off Available only when you select Synchronous mode.When you turn this parameter, the IP removes the periphery-to-core registerstage (driven by the divided clock), However, the removal of this stage maycause increase in timing closure effort.

DIB to DUT ClockRatio

8, 10, 20, 25, 40,50, 100, 200

Available only when you select Asynchronous mode.Select the DIB clock to DUT clock ratio for hard TDM.

Table 15. Banks 0–3 Tab Parameters


PHY Mode • Bypass (1:1)• TDM 1:1• TDM 2:1• TDM 4:1

Select the PHY mode you want for the selected bank.

Min output delay Variable Available only when you select Bypass (1:1) mode.Set the minimum and maximum delay for the paired output bank in theremote die.Max output delay Variable

I/O Mode • Input• Output

Select the I/O direction mode for the selected bank.• — Input: RX mode

— Output: TX mode

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Table 16. Diagnostics Tab Parameters


DIB ClockFrequency

0.1–400 MHz Set the clock frequency of the DIB subsystem.

System ClockFrequency

0.1–400 MHz Available only when a bank is in Synchronous TDM mode.Set the system clock frequency.

UserecommendedDUT clockfrequency

On, Off • Turn on to allow the IP to automatically calculate the DUT clockfrequency.

• Turn off if you want to specify your own DUT clock frequency.

DUT ClockFrequency

0.1–100 MHz Available only when a bank is in Bypass or Asynchronous TDM mode.Set the DUT clock frequency.

Userecommendedexample designPLL referenceclock frequency

On, Off • Turn on to allow the IP to automatically calculate the PLL reference clockfrequency for optimal performance.

• Turn off if you want to specify your own PLL reference clock frequency.

Reference clockfrequency forexample designPLL

25.0–100 MHz Available only for the design example PLL.Set the PLL reference clock frequency for the PLL that supplies to the DIBclock and system clock.

Table 17. Example Design Tab Parameters


Simulation On, Off Turn on this parameter to generate the necessary design simulation files.

Synthesis On, Off Turn on this parameter to generate the necessary design synthesis files. Usethese files to compile the design in the Intel Quartus Prime ProEditionsoftware for hardware testing.

Generate asecond pairedchannel

On, Off Turn on this parameter to generate a second design example that pairs withselected settings. The paired channel has reversed I/O settings and flippedbank indices.

Simulation HDLformat

• Verilog• VHDL

Select the format of the RTL files generated for simulating the designexample.

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8. Document Revision History for the DIB Intel Stratix 10FPGA IP User Guide

Document Version Intel QuartusPrime Version

Intel FPGA IPVersion

Changes

2020.08.30 20.2 19.3.0 • Edited the bits information for banks 1 and 2 in theAUX Channel Settings and Die-to-Die Mappingsections. Each bank is 16 data bits wide andincludes an additional wire for clock.

2020.06.30 20.2 19.3.0 Initial release.

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A. Die-to-Die MappingThe mapping information provides you the details of the placement of I/O banks,channels and subsystems in the dies.

Table 18. Mapping of DIB Subsystem Indices for A Pair of Dies (Die A to Die B)Rule: I/O Bank X in Die A = I/O Bank (2-X) in Die B

Left Die (A)Subsystem #

Right Die (B)Subsystem #

2 0

1 1

0 2

Table 19. Mapping of DIB Channel Indices Within A Pair of Subsystems from Die A toDie BRule: Channel X in Die A = Channel (23-X) in Die B; AUX channel in Die A = AUX channel in Die B

Left Die (A)Channel #

Right Die (B)Channel #

23 0

22 1

21 2

20 3

19 4

18 5

17 6

16 7

15 8

14 9

13 10

12 11

AUX AUX

11 12

10 13

9 14

8 15

continued...

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Left Die (A)Channel #

Right Die (B)Channel #

7 16

6 17

5 18

4 19

3 20

2 21

1 22

0 23

Table 20. Mapping of DIB I/O Bank Indices Within A Pair of Channels from Die A to DieBRule: I/O Bank X in Die A = I/O Bank (3-X) in Die B

Left Die (A)I/O Bank #

Right Die (B)I/O Bank #

3 0

2 1

1 2

0 3

Table 21. Mapping of Data Bits Within A Pair of I/O Banks from Die A to Die BRule: Bit X in Die A = Bit X in Die B

Note: Non-mapped bits from the 82-bit RX or TX interface are disconnected or tied off.

Bypass Configuration TDM 2:1 Configuration TDM 4:1 Configuration AUX Channel, Bank 2/1Configuration (3)

Left Die (A)Data Bit #

Right Die(B)

Data Bit #


Right Die(B)

Data Bit #


Right Die(B)

Data Bit #


Right Die(B)

Data Bit #

0 0 2 2 2 2 0 0

1 1 3 3 3 3 1 1

2 2 4 4 4 4 2 2

3 3 5 5 5 5 3 3

4 4 6 6 6 6 4 4

5 5 7 7 7 7 5 5

6 6 8 8 8 8 6 6

7 7 9 9 9 9 7 7

continued...

(3) AUX channel bank 1 (TX only) and bank 2 (RX only) are only 16 data bits wide. Each bankalso includes an additional wire for clock.

A. Die-to-Die Mapping

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Right Die(B)

Data Bit #


Right Die(B)

Data Bit #


Right Die(B)

Data Bit #


Right Die(B)

Data Bit #

8 8 10 10 10 10 8 8

9 9 11 11 11 11 9 9

10 10 12 12 12 12 10 10

11 11 13 13 13 13 11 11

12 12 14 14 14 14 12 12

13 13 15 15 15 15 13 13

14 14 16 16 16 16 14 14

15 15 17 17 17 17 15 15

16 16 18 18 18 18

17 17 19 19 19 19

18 18 20 20 20 20

19 19 21 21 21 21

20 20 22 22 22 22

21 21 23 23 23 23

24 24 24 24

25 25 25 25

26 26 26 26

27 27 27 27

28 28 28 28

29 29 29 29

30 30 30 30

31 31 31 31

32 32 32 32

33 33 33 33

34 34 34 34

35 35 35 35

36 36 36 36

37 37 37 37

38 38 38 38

39 39 39 39

40 40 40 40

continued...



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Right Die(B)

Data Bit #


Right Die(B)

Data Bit #


Right Die(B)

Data Bit #


Right Die(B)

Data Bit #

41 41 41 41

42 42

43 43

44 44

45 45

46 46

47 47

48 48

49 49

50 50

51 51

52 52

53 53

54 54

55 55

56 56

57 57

58 58

59 59

60 60

61 61

62 62

63 63

64 64

65 65

66 66

67 67

68 68

69 69

70 70

71 71

continued...



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Right Die(B)

Data Bit #


Right Die(B)

Data Bit #


Right Die(B)

Data Bit #


Right Die(B)

Data Bit #

72 72

73 73

74 74

75 75

76 76

77 77

78 78

79 79

80 80

81 81

Table 22. Full Map

Left Die Right Die

Subsystem Channel I/O Bank I/O Bank Channel Subsystem

2

23

3 0

0

0

2 1

1 2

0 3

22

3 0

12 1

1 2

0 3

21

3 0

22 1

1 2

0 3

20

3 0

32 1

1 2

0 3

193 0

42 1

continued...



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Left Die Right Die


1 2

0 3

18

3 0

52 1

1 2

0 3

17

3 0

62 1

1 2

0 3

16

3 0

72 1

1 2

0 3

15

3 0

82 1

1 2

0 3

14

3 0

92 1

1 2

0 3

13

3 0

102 1

1 2

0 3

12

3 0

112 1

1 2

0 3

AUX

3 3

AUX2 2

1 1

0 0

11 3 0 12

continued...


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39


Left Die Right Die


2 1

1 2

0 3

10

3 0

132 1

1 2

0 3

9

3 0

142 1

1 2

0 3

8

3 0

152 1

1 2

0 3

7

3 0

162 1

1 2

0 3

6

3 0

172 1

1 2

0 3

5

3 0

182 1

1 2

0 3

4

3 0

192 1

1 2

0 3

3

3 0

202 1

1 2

0 3

continued...


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40


Left Die Right Die


2

3 0

212 1

1 2

0 3

1

3 0

222 1

1 2

0 3

0

3 0

232 1

1 2

0 3

1

23

3 0

0

1

2 1

1 2

0 3

22

3 0

12 1

1 2

0 3

21

3 0

22 1

1 2

0 3

20

3 0

32 1

1 2

0 3

19

3 0

42 1

1 2

0 3

18

3 0

52 1

1 2

continued...


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41


Left Die Right Die


0 3

17

3 0

62 1

1 2

0 3

16

3 0

72 1

1 2

0 3

15

3 0

82 1

1 2

0 3

14

3 0

92 1

1 2

0 3

13

3 0

102 1

1 2

0 3

12

3 0

112 1

1 2

0 3

AUX

3 3

AUX2 2

1 1

0 0

11

3 0

122 1

1 2

0 3

103 0

132 1

continued...


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42


Left Die Right Die


1 2

0 3

9

3 0

142 1

1 2

0 3

8

3 0

152 1

1 2

0 3

7

3 0

162 1

1 2

0 3

6

3 0

172 1

1 2

0 3

5

3 0

182 1

1 2

0 3

4

3 0

192 1

1 2

0 3

3

3 0

202 1

1 2

0 3

2

3 0

212 1

1 2

0 3

1 3 0 22

continued...


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43


Left Die Right Die


2 1

1 2

0 3

0

3 0

232 1

1 2

0 3

0

23

3 0

0

2

2 1

1 2

0 3

22

3 0

12 1

1 2

0 3

21

3 0

22 1

1 2

0 3

20

3 0

32 1

1 2

0 3

19

3 0

42 1

1 2

0 3

18

3 0

52 1

1 2

0 3

17

3 0

62 1

1 2

0 3

continued...


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44


Left Die Right Die


16

3 0

72 1

1 2

0 3

15

3 0

82 1

1 2

0 3

14

3 0

92 1

1 2

0 3

13

3 0

102 1

1 2

0 3

12

3 0

112 1

1 2

0 3

AUX

3 3

AUX2 2

1 1

0 0

11

3 0

122 1

1 2

0 3

10

3 0

132 1

1 2

0 3

9

3 0

142 1

1 2

continued...


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45


Left Die Right Die


0 3

8

3 0

152 1

1 2

0 3

7

3 0

162 1

1 2

0 3

6

3 0

172 1

1 2

0 3

5

3 0

182 1

1 2

0 3

4

3 0

192 1

1 2

0 3

3

3 0

202 1

1 2

0 3

2

3 0

212 1

1 2

0 3

1

3 0

222 1

1 2

0 3

0 3 0 23

continued...


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46


Left Die Right Die


2 1

1 2

0 3


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47


B. Example Pin Locations for One DIB ChannelEach DIB instance must have at least one pin location assigned to allow for other pinlocations to be automatically assigned.

Example 2. Pin Locations for One DIB Standard Channel

set_location_assignment PIN_DIB0_CH0_X1Y0 -to pad_0_dib_pad[0]set_location_assignment PIN_DIB1_CH0_X1Y0 -to pad_0_dib_pad[1]set_location_assignment PIN_DIB2_CH0_X1Y0 -to pad_0_dib_pad[2]set_location_assignment PIN_DIB3_CH0_X1Y0 -to pad_0_dib_pad[3]set_location_assignment PIN_DIB4_CH0_X1Y0 -to pad_0_dib_pad[4]set_location_assignment PIN_DIB5_CH0_X1Y0 -to pad_0_dib_pad[5]set_location_assignment PIN_DIB6_CH0_X1Y0 -to pad_0_dib_pad[6]set_location_assignment PIN_DIB7_CH0_X1Y0 -to pad_0_dib_pad[7]set_location_assignment PIN_DIB8_CH0_X1Y0 -to pad_0_dib_pad[8]set_location_assignment PIN_DIB9_CH0_X1Y0 -to pad_0_dib_pad[9]set_location_assignment PIN_DIB10_CH0_X1Y0 -to pad_0_dib_pad[10]set_location_assignment PIN_DIB11_CH0_X1Y0 -to pad_0_dib_pad[11]set_location_assignment PIN_DIB12_CH0_X1Y0 -to pad_0_dib_pad[12]set_location_assignment PIN_DIB13_CH0_X1Y0 -to pad_0_dib_pad[13]set_location_assignment PIN_DIB14_CH0_X1Y0 -to pad_0_dib_pad[14]set_location_assignment PIN_DIB15_CH0_X1Y0 -to pad_0_dib_pad[15]set_location_assignment PIN_DIB16_CH0_X1Y0 -to pad_0_dib_pad[16]set_location_assignment PIN_DIB17_CH0_X1Y0 -to pad_0_dib_pad[17]set_location_assignment PIN_DIB18_CH0_X1Y0 -to pad_0_dib_pad[18]set_location_assignment PIN_DIB19_CH0_X1Y0 -to pad_0_dib_pad[19]set_location_assignment PIN_DIB20_CH0_X1Y0 -to pad_0_dib_pad[20]set_location_assignment PIN_DIB21_CH0_X1Y0 -to pad_0_dib_pad[21]set_location_assignment PIN_DIB22_CH0_X1Y0 -to pad_0_dib_pad[22]set_location_assignment PIN_DIB23_CH0_X1Y0 -to pad_0_dib_pad[23]set_location_assignment PIN_DIB24_CH0_X1Y0 -to pad_1_dib_pad[0]set_location_assignment PIN_DIB25_CH0_X1Y0 -to pad_1_dib_pad[1]set_location_assignment PIN_DIB26_CH0_X1Y0 -to pad_1_dib_pad[2]set_location_assignment PIN_DIB27_CH0_X1Y0 -to pad_1_dib_pad[3]set_location_assignment PIN_DIB28_CH0_X1Y0 -to pad_1_dib_pad[4]set_location_assignment PIN_DIB29_CH0_X1Y0 -to pad_1_dib_pad[5]set_location_assignment PIN_DIB30_CH0_X1Y0 -to pad_1_dib_pad[6]set_location_assignment PIN_DIB31_CH0_X1Y0 -to pad_1_dib_pad[7]set_location_assignment PIN_DIB32_CH0_X1Y0 -to pad_1_dib_pad[8]set_location_assignment PIN_DIB33_CH0_X1Y0 -to pad_1_dib_pad[9]set_location_assignment PIN_DIB34_CH0_X1Y0 -to pad_1_dib_pad[10]set_location_assignment PIN_DIB35_CH0_X1Y0 -to pad_1_dib_pad[11]set_location_assignment PIN_DIB36_CH0_X1Y0 -to pad_1_dib_pad[12]set_location_assignment PIN_DIB37_CH0_X1Y0 -to pad_1_dib_pad[13]set_location_assignment PIN_DIB38_CH0_X1Y0 -to pad_1_dib_pad[14]set_location_assignment PIN_DIB39_CH0_X1Y0 -to pad_1_dib_pad[15]set_location_assignment PIN_DIB40_CH0_X1Y0 -to pad_1_dib_pad[16]set_location_assignment PIN_DIB41_CH0_X1Y0 -to pad_1_dib_pad[17]set_location_assignment PIN_DIB42_CH0_X1Y0 -to pad_1_dib_pad[18]set_location_assignment PIN_DIB43_CH0_X1Y0 -to pad_1_dib_pad[19]set_location_assignment PIN_DIB44_CH0_X1Y0 -to pad_1_dib_pad[20]set_location_assignment PIN_DIB45_CH0_X1Y0 -to pad_1_dib_pad[21]set_location_assignment PIN_DIB46_CH0_X1Y0 -to pad_1_dib_pad[22]set_location_assignment PIN_DIB47_CH0_X1Y0 -to pad_1_dib_pad[23]set_location_assignment PIN_DIB48_CH0_X1Y0 -to pad_2_dib_pad[0]set_location_assignment PIN_DIB49_CH0_X1Y0 -to pad_2_dib_pad[1]set_location_assignment PIN_DIB50_CH0_X1Y0 -to pad_2_dib_pad[2]set_location_assignment PIN_DIB51_CH0_X1Y0 -to pad_2_dib_pad[3]

UG-20288 | 2020.08.30

Send Feedback







set_location_assignment PIN_DIB52_CH0_X1Y0 -to pad_2_dib_pad[4]set_location_assignment PIN_DIB53_CH0_X1Y0 -to pad_2_dib_pad[5]set_location_assignment PIN_DIB54_CH0_X1Y0 -to pad_2_dib_pad[6]set_location_assignment PIN_DIB55_CH0_X1Y0 -to pad_2_dib_pad[7]set_location_assignment PIN_DIB56_CH0_X1Y0 -to pad_2_dib_pad[8]set_location_assignment PIN_DIB57_CH0_X1Y0 -to pad_2_dib_pad[9]set_location_assignment PIN_DIB58_CH0_X1Y0 -to pad_2_dib_pad[10]set_location_assignment PIN_DIB59_CH0_X1Y0 -to pad_2_dib_pad[11]set_location_assignment PIN_DIB60_CH0_X1Y0 -to pad_2_dib_pad[12]set_location_assignment PIN_DIB61_CH0_X1Y0 -to pad_2_dib_pad[13]set_location_assignment PIN_DIB62_CH0_X1Y0 -to pad_2_dib_pad[14]set_location_assignment PIN_DIB63_CH0_X1Y0 -to pad_2_dib_pad[15]set_location_assignment PIN_DIB64_CH0_X1Y0 -to pad_2_dib_pad[16]set_location_assignment PIN_DIB65_CH0_X1Y0 -to pad_2_dib_pad[17]set_location_assignment PIN_DIB66_CH0_X1Y0 -to pad_2_dib_pad[18]set_location_assignment PIN_DIB67_CH0_X1Y0 -to pad_2_dib_pad[19]set_location_assignment PIN_DIB68_CH0_X1Y0 -to pad_2_dib_pad[20]set_location_assignment PIN_DIB69_CH0_X1Y0 -to pad_2_dib_pad[21]set_location_assignment PIN_DIB70_CH0_X1Y0 -to pad_2_dib_pad[22]set_location_assignment PIN_DIB71_CH0_X1Y0 -to pad_2_dib_pad[23]set_location_assignment PIN_DIB72_CH0_X1Y0 -to pad_3_dib_pad[0]set_location_assignment PIN_DIB73_CH0_X1Y0 -to pad_3_dib_pad[1]set_location_assignment PIN_DIB74_CH0_X1Y0 -to pad_3_dib_pad[2]set_location_assignment PIN_DIB75_CH0_X1Y0 -to pad_3_dib_pad[3]set_location_assignment PIN_DIB76_CH0_X1Y0 -to pad_3_dib_pad[4]set_location_assignment PIN_DIB77_CH0_X1Y0 -to pad_3_dib_pad[5]set_location_assignment PIN_DIB78_CH0_X1Y0 -to pad_3_dib_pad[6]set_location_assignment PIN_DIB79_CH0_X1Y0 -to pad_3_dib_pad[7]set_location_assignment PIN_DIB80_CH0_X1Y0 -to pad_3_dib_pad[8]set_location_assignment PIN_DIB81_CH0_X1Y0 -to pad_3_dib_pad[9]set_location_assignment PIN_DIB82_CH0_X1Y0 -to pad_3_dib_pad[10]set_location_assignment PIN_DIB83_CH0_X1Y0 -to pad_3_dib_pad[11]set_location_assignment PIN_DIB84_CH0_X1Y0 -to pad_3_dib_pad[12]set_location_assignment PIN_DIB85_CH0_X1Y0 -to pad_3_dib_pad[13]set_location_assignment PIN_DIB86_CH0_X1Y0 -to pad_3_dib_pad[14]set_location_assignment PIN_DIB87_CH0_X1Y0 -to pad_3_dib_pad[15]set_location_assignment PIN_DIB88_CH0_X1Y0 -to pad_3_dib_pad[16]set_location_assignment PIN_DIB89_CH0_X1Y0 -to pad_3_dib_pad[17]set_location_assignment PIN_DIB90_CH0_X1Y0 -to pad_3_dib_pad[18]set_location_assignment PIN_DIB91_CH0_X1Y0 -to pad_3_dib_pad[19]set_location_assignment PIN_DIB92_CH0_X1Y0 -to pad_3_dib_pad[20]set_location_assignment PIN_DIB93_CH0_X1Y0 -to pad_3_dib_pad[21]set_location_assignment PIN_DIB94_CH0_X1Y0 -to pad_3_dib_pad[22]set_location_assignment PIN_DIB95_CH0_X1Y0 -to pad_3_dib_pad[23]

Example 3. Pin Locations for One DIB AUX Channel

set_location_assignment PIN_DIB_AUX0_X1Y0 -to dib_pad_0[0]set_location_assignment PIN_DIB_AUX1_X1Y0 -to dib_pad_0[1]set_location_assignment PIN_DIB_AUX2_X1Y0 -to dib_pad_0[2]set_location_assignment PIN_DIB_AUX3_X1Y0 -to dib_pad_0[3]set_location_assignment PIN_DIB_AUX4_X1Y0 -to dib_pad_0[4]set_location_assignment PIN_DIB_AUX5_X1Y0 -to dib_pad_0[5]set_location_assignment PIN_DIB_AUX6_X1Y0 -to dib_pad_0[6]set_location_assignment PIN_DIB_AUX7_X1Y0 -to dib_pad_0[7]set_location_assignment PIN_DIB_AUX8_X1Y0 -to dib_pad_0[8]set_location_assignment PIN_DIB_AUX9_X1Y0 -to dib_pad_0[9]set_location_assignment PIN_DIB_AUX10_X1Y0 -to dib_pad_0[10]set_location_assignment PIN_DIB_AUX11_X1Y0 -to dib_pad_0[11]set_location_assignment PIN_DIB_AUX12_X1Y0 -to dib_pad_0[12]set_location_assignment PIN_DIB_AUX13_X1Y0 -to dib_pad_0[13]set_location_assignment PIN_DIB_AUX14_X1Y0 -to dib_pad_0[14]set_location_assignment PIN_DIB_AUX15_X1Y0 -to dib_pad_0[15]set_location_assignment PIN_DIB_AUX16_X1Y0 -to dib_pad_0[16]set_location_assignment PIN_DIB_AUX17_X1Y0 -to dib_pad_0[17]set_location_assignment PIN_DIB_AUX18_X1Y0 -to dib_pad_0[18]set_location_assignment PIN_DIB_AUX19_X1Y0 -to dib_pad_0[19]set_location_assignment PIN_DIB_AUX20_X1Y0 -to dib_pad_0[20]set_location_assignment PIN_DIB_AUX21_X1Y0 -to dib_pad_0[21]set_location_assignment PIN_DIB_AUX22_X1Y0 -to dib_pad_0[22]

B. Example Pin Locations for One DIB Channel

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49


set_location_assignment PIN_DIB_AUX23_X1Y0 -to dib_pad_0[23]set_location_assignment PIN_DIB_AUX24_X1Y0 -to dib_pad_1[0]set_location_assignment PIN_DIB_AUX25_X1Y0 -to dib_pad_1[1]set_location_assignment PIN_DIB_AUX26_X1Y0 -to dib_pad_1[2]set_location_assignment PIN_DIB_AUX27_X1Y0 -to dib_pad_1[3]set_location_assignment PIN_DIB_AUX28_X1Y0 -to dib_pad_1[4]set_location_assignment PIN_DIB_AUX29_X1Y0 -to dib_pad_1[5]set_location_assignment PIN_DIB_AUX30_X1Y0 -to dib_pad_1[6]set_location_assignment PIN_DIB_AUX31_X1Y0 -to dib_pad_1[7]set_location_assignment PIN_DIB_AUX32_X1Y0 -to dib_pad_1[8]set_location_assignment PIN_DIB_AUX33_X1Y0 -to dib_pad_1[9]set_location_assignment PIN_DIB_AUX34_X1Y0 -to dib_pad_1[10]set_location_assignment PIN_DIB_AUX35_X1Y0 -to dib_pad_1[11]set_location_assignment PIN_DIB_AUX36_X1Y0 -to dib_pad_1[12]set_location_assignment PIN_DIB_AUX37_X1Y0 -to dib_pad_1[13]set_location_assignment PIN_DIB_AUX38_X1Y0 -to dib_pad_1[14]set_location_assignment PIN_DIB_AUX39_X1Y0 -to dib_pad_1[15]set_location_assignment PIN_DIB_AUX40_X1Y0 -to dib_pad_1[16]set_location_assignment PIN_DIB_AUX41_X1Y0 -to dib_pad_1[17]set_location_assignment PIN_DIB_AUX42_X1Y0 -to dib_pad_1[18]set_location_assignment PIN_DIB_AUX43_X1Y0 -to dib_pad_1[19]set_location_assignment PIN_DIB_AUX44_X1Y0 -to dib_pad_1[20]set_location_assignment PIN_DIB_AUX45_X1Y0 -to dib_pad_1[21]set_location_assignment PIN_DIB_AUX46_X1Y0 -to dib_pad_1[22]set_location_assignment PIN_DIB_AUX47_X1Y0 -to dib_pad_1[23]set_location_assignment PIN_DIB_AUX48_X1Y0 -to dib_pad_2[0]set_location_assignment PIN_DIB_AUX49_X1Y0 -to dib_pad_2[1]set_location_assignment PIN_DIB_AUX50_X1Y0 -to dib_pad_2[2]set_location_assignment PIN_DIB_AUX51_X1Y0 -to dib_pad_2[3]set_location_assignment PIN_DIB_AUX52_X1Y0 -to dib_pad_2[4]set_location_assignment PIN_DIB_AUX53_X1Y0 -to dib_pad_2[5]set_location_assignment PIN_DIB_AUX54_X1Y0 -to dib_pad_2[6]set_location_assignment PIN_DIB_AUX55_X1Y0 -to dib_pad_2[7]set_location_assignment PIN_DIB_AUX56_X1Y0 -to dib_pad_2[8]set_location_assignment PIN_DIB_AUX57_X1Y0 -to dib_pad_2[9]set_location_assignment PIN_DIB_AUX58_X1Y0 -to dib_pad_2[10]set_location_assignment PIN_DIB_AUX59_X1Y0 -to dib_pad_2[11]set_location_assignment PIN_DIB_AUX60_X1Y0 -to dib_pad_2[12]set_location_assignment PIN_DIB_AUX61_X1Y0 -to dib_pad_2[13]set_location_assignment PIN_DIB_AUX62_X1Y0 -to dib_pad_2[14]set_location_assignment PIN_DIB_AUX63_X1Y0 -to dib_pad_2[15]set_location_assignment PIN_DIB_AUX64_X1Y0 -to dib_pad_2[16]set_location_assignment PIN_DIB_AUX65_X1Y0 -to dib_pad_2[17]set_location_assignment PIN_DIB_AUX66_X1Y0 -to dib_pad_2[18]set_location_assignment PIN_DIB_AUX67_X1Y0 -to dib_pad_2[19]set_location_assignment PIN_DIB_AUX68_X1Y0 -to dib_pad_2[20]set_location_assignment PIN_DIB_AUX69_X1Y0 -to dib_pad_2[21]set_location_assignment PIN_DIB_AUX70_X1Y0 -to dib_pad_2[22]set_location_assignment PIN_DIB_AUX71_X1Y0 -to dib_pad_2[23]set_location_assignment PIN_DIB_AUX72_X1Y0 -to dib_pad_3[0]set_location_assignment PIN_DIB_AUX73_X1Y0 -to dib_pad_3[1]set_location_assignment PIN_DIB_AUX74_X1Y0 -to dib_pad_3[2]set_location_assignment PIN_DIB_AUX75_X1Y0 -to dib_pad_3[3]set_location_assignment PIN_DIB_AUX76_X1Y0 -to dib_pad_3[4]set_location_assignment PIN_DIB_AUX77_X1Y0 -to dib_pad_3[5]set_location_assignment PIN_DIB_AUX78_X1Y0 -to dib_pad_3[6]set_location_assignment PIN_DIB_AUX79_X1Y0 -to dib_pad_3[7]set_location_assignment PIN_DIB_AUX80_X1Y0 -to dib_pad_3[8]set_location_assignment PIN_DIB_AUX81_X1Y0 -to dib_pad_3[9]set_location_assignment PIN_DIB_AUX82_X1Y0 -to dib_pad_3[10]set_location_assignment PIN_DIB_AUX83_X1Y0 -to dib_pad_3[11]set_location_assignment PIN_DIB_AUX84_X1Y0 -to dib_pad_3[12]set_location_assignment PIN_DIB_AUX85_X1Y0 -to dib_pad_3[13]set_location_assignment PIN_DIB_AUX86_X1Y0 -to dib_pad_3[14]set_location_assignment PIN_DIB_AUX87_X1Y0 -to dib_pad_3[15]set_location_assignment PIN_DIB_AUX88_X1Y0 -to dib_pad_3[16]set_location_assignment PIN_DIB_AUX89_X1Y0 -to dib_pad_3[17]set_location_assignment PIN_DIB_AUX90_X1Y0 -to dib_pad_3[18]set_location_assignment PIN_DIB_AUX91_X1Y0 -to dib_pad_3[19]set_location_assignment PIN_DIB_AUX92_X1Y0 -to dib_pad_3[20]


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set_location_assignment PIN_DIB_AUX93_X1Y0 -to dib_pad_3[21]set_location_assignment PIN_DIB_AUX94_X1Y0 -to dib_pad_3[22]set_location_assignment PIN_DIB_AUX95_X1Y0 -to dib_pad_3[23]


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51
