distinctive characteristics · am7990 local area network controller for ethernet (lance) am79c90...

Publication# 18219 Rev. B Amendment /0

Issue Date: May 1994This document contains information on a product under development at Advanced Micro Devices, Inc. The information isintended to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposedproduct without notice.

AdvancedMicro

Devices

Am79C965PCnetTM-32 Single-Chip 32-Bit Ethernet Controller

PRELIMINARY

DISTINCTIVE CHARACTERISTICS Single-chip Ethernet controller for 486 and

Video Electronics Standards Association(VESA) local buses

Supports ISO 8802-3 (IEEE/ANSI 802.3) andEthernet standards

Direct interface to the 486 local bus or VESAVL-Bus

Enhanced burst mode with support forAm486TM burst read/write operations

Software compatible with AMD’s Am7990LANCE, Am79C90 C-LANCE, Am79C960PCnet-ISA, Am79C961 PCnet-ISA +, Am79C970PCnet-PCI, and Am79C900 ILACC TM registerand descriptor architecture

Compatible with Am2100/Am1500T and Novell ‚

NE2100/NE1500driversoftware

High performance Bus Master architecture withintegrated DMA Buffer Management Unit forlow CPU and bus utilization

Built-in byte-swap logic supports both Big andLittle Endian byte alignment

Microwire TM EEPROM interface supportsjumperless design

Single +5 V power supply operation

Low power, CMOS design with sleep modesallows reduced power consumption for criticalbattery powered applications and Green PCs

Look-Ahead Packet Processing (LAPP) allowsprotocol analysis to begin before end ofreceive frame

Integrated Manchester Encoder/Decoder

Individual 136-byte transmit and 128-bytereceive FIFOs provide frame buffering forincreased system latency tolerance andsupport the following features:

— Automatic retransmission with no FIFO reload

— Automatic receive stripping and transmit pad-ding (individually programmable)

— Automatic runt packet rejection

— Automatic deletion of received collision frames

JTAG Boundary Scan (IEEE 1149.1) test accessport interface for board level production test

Provides integrated Attachment Unit Interface(AUI) and 10BASE-T transceiver with automaticport selection

Automatic Twisted Pair receive polaritydetection and automatic correction of thereceive polarity

Optional byte padding to long-word boundaryon receive

Dynamic transmit FCS generationprogrammable on a frame-by-frame basis

Internal/external loopback capabilities

Supports the following types of networkinterfaces:

— AUI to external 10BASE2, 10BASE5,10BASE-T or 10BASE-F MAU

— Internal 10BASE-T transceiver with SmartSquelch to Twisted Pair medium

Supports LANCE/C-LANCE/PCnet-ISA GeneralPurpose Serial Interface (GPSI)

160-pin PQFP package

GENERAL DESCRIPTIONThe PCnet-32 single-chip 32-bit Ethernet controller is ahighly integrated Ethernet system solution designed toaddress high-performance system application require-ments. It is a flexible bus-mastering device that can beused in any networking application, including network-ready PCs, printers, fax modems, and bridge/router de-signs. The bus-master architecture provides high datathroughput in the system and low CPU and bus utiliza-tion. The PCnet-32 controller is fabricated with AMD’s

advanced low-power CMOS process to provide lowoperating and standby current for power sensitiveapplications.

The PCnet-32 controller is a complete Ethernet nodeintegrated into a single VLSI device. It contains a businterface unit, a DMA buffer management unit, an ISO8802-3 (IEEE/ANSI 802.3) defined Media Access Con-trol (MAC) function, individual 136-byte transmit and

AMD P R E L I M I N A R Y

2 Am79C965

128-byte receive FIFOs, an ISO 8802-3 (IEEE/ANSI802.3) defined Attachment Unit Interface (AUI) andTwisted-Pair Transceiver Media Attachment Unit(10BASE-T MAU), and a microwire EEPROM interface.The PCnet-32 controller is also register compatiblewith the LANCE (Am7990) Ethernet controller, theC-LANCE (Am79C90) Ethernet controller, the ILACC(Am79C900) Ethernet controller, and all Ethernet con-trollers in the PCnet Family, including the PCnet-ISAcontroller (Am79C960), the PCnet-ISA+ controller(Am79C961), and the PCnet-PCI controller(Am79C970). The buffer management unit supports theLANCE, ILACC, and PCnet descriptor software models.The PCnet-32 controller is software compatible withNovell NE2100 and NE1500 Ethernet adapter card ar-chitectures. In addition, a Sleep function has been incor-porated to provide low standby current which isessential for notebooks and Green PCs.

The 32-bit demultiplexed bus interface unit provides adirect interface to the VESA VL-Bus and 486 seriesmicroprocessors, simplifying the design of an Ethernetnode in a PC system. With its built-in support for bothlittle and big endian byte alignment, this controller alsoaddresses proprietary non-PC applications.

Key PCnet-32 configuration parameters, including theunique IEEE physical address, can be read from anexternal non-volatile memory (serial EEPROM) imme-diately following system reset. In addition, the I/O loca-tion at which the internal registers are accessed may bestored in the EEPROM, allowing the software model ofthe device to be located appropriately in system I/Ospace during system initialization.

The controller has the capability to automatically selecteither the AUI port or the Twisted-Pair transceiver. Onlyone interface is active at any one time. The individualtransmit and receive FIFOs reduce system overhead,providing sufficient latency during frame transmissionand reception, and minimizing intervention during nor-mal network error recovery. The integrated Manchesterencoder/decoder (MENDEC) eliminates the need for anexternal Serial Interface Adapter (SIA) in the node sys-tem. The built-in General Purpose Serial Interface(GPSI) allows the MENDEC to be by-passed. In addi-tion, the device provides programmable on-chip LEDdrivers for transmit, receive, collision, receive polarity,link integrity, or jabber status. The PCnet-32 controlleralso provides an External Address Detection Interface(EADI) to allow external hardware address filtering ininternetworking applications.

RELATED PRODUCTS

Part No Description

Am79C98 Twisted Pair Ethernet Transceiver (TPEX)

Am79C100 Twisted Pair Ethernet Transceiver Plus (TPEX+)

Am7996 IEEE 802.3/Ethernet/Cheapernet Tap Transceiver

Am79C981 Integrated Multiport Repeater Plus (IMR+)

Am79C987 Hardware Implemented Management Information Base (HIMIB)

Am79C940 Media Access Controller for Ethernet (MACE)

Am7990 Local Area Network Controller for Ethernet (LANCE)

Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE)

Am79C900 Integrated Local Area Communications Controller (ILACC)

Am79C960 PCnet-ISA Single-Chip Ethernet Controller (for ISA bus)

Am79C961 PCnet-ISA+ Single-Chip Ethernet Controller (with Microsoft Plug n’ Play support)

Am79C970 PCnet-PCI Single-Chip Ethernet Controller (for PCI bus)

Am79C974 PCnet-SCSI Combination Ethernet and SCSI Controller for PCI Systems

P R E L I M I N A R Y AMD

3Am79C965

ORDERING INFORMATIONStandard ProductsAMD standard products are available in several packages and operating ranges. The order number (Valid Combination) isformed by a combination of:

TEMPERATURE RANGEC = Commercial (0°C to +70°C)

PACKAGE TYPE(per Prod. Nomenclature/16-038)K = Plastic Quad Flat Pack (PQR160)

SPEED Not Applicable

DEVICE NUMBER/DESCRIPTIONAm79C965PCnet-32 Single-Chip 32-Bit Ethernet Controller

AM79C965

Valid Combinations

KC, KC\W

Valid Combinations

OPTIONAL PROCESSINGBlank = Standard Processing

AM79C965 K C

Valid Combinations list configurations planned to besupported in volume for this device. Consult the localAMD sales office to confirm availability of specificvalid combinations and to check on newly releasedcombinations.

\W

ALTERNATIVE PACKAGE OPTION \W = Trimmed and Formed in a Tray (PQJ 160)


4 Am79C965

TABLE OF CONTENTS

DISTINCTIVE CHARACTERISTICS 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GENERAL DESCRIPTION 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RELATED PRODUCTS 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ORDERING INFORMATION 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BLOCK DIAGRAM: VESA VL-BUS MODE 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CONNECTION DIAGRAM: VESA VL-BUS MODE 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PIN DESIGNATIONS: VESA VL-BUS MODE 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LISTED BY PIN NUMBER 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LISTED BY PIN NAME 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LISTED BY GROUP 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DRIVER TYPE 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PIN DESCRIPTION: VESA VL-BUS MODE 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CONFIGURATION PINS 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CONFIGURATION PIN SETTINGS SUMMARY 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PIN CONNECTIONS TO VDD OR VSS 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VESA VL-BUS INTERFACE 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BOARD INTERFACE 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MICROWIRE EEPROM INTERFACE 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ATTACHMENT UNIT INTERFACE 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TWISTED PAIR INTERFACE 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

EXTERNAL ADDRESS DETECTION INTERFACE 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GENERAL PURPOSE SERIAL INTERFACE 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IEEE 1149.1 TEST ACCESS PORT INTERFACE 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

POWER SUPPLY PINS 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VESA VL-BUS/LOCAL BUS PIN CROSS-REFERENCE 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BLOCK DIAGRAM: 486 LOCAL BUS MODE 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CONNECTION DIAGRAM: 486 LOCAL BUS MODE 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PIN DESIGNATIONS: 486 LOCAL BUS MODE 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LISTED BY PIN NUMBER 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LISTED BY PIN NAME 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LISTED BY GROUP 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DRIVER TYPE 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PIN DESCRIPTION: 486 LOCAL BUS MODE 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CONFIGURATION PINS 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CONFIGURATION PIN SETTINGS SUMMARY 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PIN CONNECTIONS TO VDD OR VSS 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LOCAL BUS INTERFACE 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BOARD INTERFACE 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


5Am79C965

MICROWIRE EEPROM INTERFACE 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ATTACHMENT UNIT INTERFACE 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TWISTED PAIR INTERFACE 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

EXTERNAL ADDRESS DETECTION INTERFACE 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GENERAL PURPOSE SERIAL INTERFACE 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


POWER SUPPLY PINS 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BASIC FUNCTIONS 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SYSTEM BUS INTERFACE FUNCTION 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SOFTWARE INTERFACE 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NETWORK INTERFACES 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DETAILED FUNCTIONS 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BUS INTERFACE UNIT 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bus Acquisition 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bus Master DMA Transfers 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Initialization Block DMA Transfers 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Descriptor DMA Transfers 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

FIFO DMA Transfers 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Linear Burst DMA Transfers 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Slave Timing 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VESA VL-Bus Mode Timing 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bus Master and Bus Slave Data Byte Placement 84. . . . . . . . . . . . . . . . . . . . . . . . . . . .

BUFFER MANAGEMENT UNIT 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Initialization 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Re-initialization 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Buffer Management 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Descriptor Rings 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Descriptor Ring Access Mechanism 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Polling 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transmit Descriptor Table Entry (TDTE) 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receive Descriptor Table Entry (RDTE) 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MEDIA ACCESS CONTROL 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transmit and Receive Message Data Encapsulation 91. . . . . . . . . . . . . . . . . . . . . . . . .

Media Access Management 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MANCHESTER ENCODER/DECODER (MENDEC) 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

External Crystal Characteristics 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

External Clock Drive Characteristics 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MENDEC Transmit Path 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transmitter Timing and Operation 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receiver Path 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Signal Conditioning 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clock Acquisition 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PLL Tracking 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


6 Am79C965

Carrier Tracking and End of Message 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Data Decoding 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Jitter Tolerance Definition 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ATTACHMENT UNIT INTERFACE (AUI) 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Differential Input Terminations 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Collision Detection 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TWISTED-PAIR TRANSCEIVER (T-MAU) 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Twisted Pair Transmit Function 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Twisted Pair Receive Function 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Link Test Function 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Polarity Detection and Reversal 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Twisted Pair Interface Status 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Collision Detect Function 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signal Quality Error (SQE) Test (Heartbeat) Function 98. . . . . . . . . . . . . . . . . . . . . . . .

Jabber Function 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Down 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10BASE-T Interface Connection 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


Boundary Scan Circuit 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TAP FSM 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supported Instructions 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Instruction Register and Decoding Logic 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Boundary Scan Register (BSR) 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Other Data Register 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

EADI (EXTERNAL ADDRESS DETECTION INTERFACE) 100. . . . . . . . . . . . . . . . . . . . . . .

GENERAL PURPOSE SERIAL INTERFACE (GPSI) 101. . . . . . . . . . . . . . . . . . . . . . . . . . . .

POWER SAVINGS MODES 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SOFTWARE ACCESS 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O Resources 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O Register Access 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

HARDWARE ACCESS 109. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PCnet-32 Controller Master Accesses 109. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Slave Access to I/O Resources 110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

EEPROM Microwire Access 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TRANSMIT OPERATION 116. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transmit Function Programming 116. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Automatic Pad Generation 116. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transmit FCS Generation 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transmit Exception Conditions 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RECEIVE OPERATION 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receive Function Programming 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Automatic Pad Stripping 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receive FCS Checking 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receive Exception Conditions 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


7Am79C965

LOOPBACK OPERATION 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LED SUPPORT 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

H_RESET, S_RESET AND STOP 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

H_RESET 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

S_RESET 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

STOP 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

USER ACCESSIBLE REGISTERS 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SETUP REGISTERS 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RUNNING REGISTERS 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RAP REGISTER 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CONTROL AND STATUS REGISTERS 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR0: PCnet-32 Controller Status 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR1: IADR[15:0] 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR2: IADR[31:16] 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR3: Interrupt Masks and Deferral Control 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR4: Test and Features Control 128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR6: RX/TX Descriptor Table Length 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR8: Logical Address Filter, LADRF[15:0] 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR9: Logical Address Filter, LADRF[31:16] 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR10: Logical Address Filter, LADRF[47:32] 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR11: Logical Address Filter, LADRF[63:48] 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR12: Physical Address Register, PADR[15:0] 131. . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR13: Physical Address Register, PADR[31:16] 131. . . . . . . . . . . . . . . . . . . . . . . . . .

CSR14: Physical Address Register, PADR[47:32] 131. . . . . . . . . . . . . . . . . . . . . . . . . .

CSR15: Mode Register 131. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR16: Initialization Block Address Lower 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR17: Initialization Block Address Upper 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR18: Current Receive Buffer Address Lower 133. . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR19: Current Receive Buffer Address Upper 134. . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR20: Current Transmit Buffer Address Lower 134. . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR21: Current Transmit Buffer Address Upper 134. . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR22: Next Receive Buffer Address Lower 134. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR23: Next Receive Buffer Address Upper 134. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR24: Base Address of Receive Ring Lower 134. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR25: Base Address of Receive Ring Upper 134. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR26: Next Receive Descriptor Address Lower 134. . . . . . . . . . . . . . . . . . . . . . . . . .

CSR27: Next Receive Descriptor Address Upper 134. . . . . . . . . . . . . . . . . . . . . . . . . .

CSR28: Current Receive Descriptor Address Lower 135. . . . . . . . . . . . . . . . . . . . . . . .

CSR29: Current Receive Descriptor Address Upper 135. . . . . . . . . . . . . . . . . . . . . . . .

CSR30: Base Address of Transmit Ring Lower 135. . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR31: Base Address of Transmit Ring Upper 135. . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR32: Next Transmit Descriptor Address Lower 135. . . . . . . . . . . . . . . . . . . . . . . . . .

CSR33: Next Transmit Descriptor Address Upper 135. . . . . . . . . . . . . . . . . . . . . . . . . .

CSR34: Current Transmit Descriptor Address Lower 135. . . . . . . . . . . . . . . . . . . . . . . .

CSR35: Current Transmit Descriptor Address Upper 135. . . . . . . . . . . . . . . . . . . . . . . .


8 Am79C965

CSR36: Next Next Receive Descriptor Address Lower 136. . . . . . . . . . . . . . . . . . . . . .

CSR37: Next Next Receive Descriptor Address Upper 136. . . . . . . . . . . . . . . . . . . . . .

CSR38: Next Next Transmit Descriptor Address Lower 136. . . . . . . . . . . . . . . . . . . . . .

CSR39: Next Next Transmit Descriptor Address Upper 136. . . . . . . . . . . . . . . . . . . . . .

CSR40: Current Receive Status and Byte Count Lower 136. . . . . . . . . . . . . . . . . . . . .

CSR41: Current Receive Status and Byte Count Upper 136. . . . . . . . . . . . . . . . . . . . .

CSR42: Current Transmit Status and Byte Count Lower 136. . . . . . . . . . . . . . . . . . . . .

CSR43: Current Transmit Status and Byte Count Upper 137. . . . . . . . . . . . . . . . . . . . .

CSR44: Next Receive Status and Byte Count Lower 137. . . . . . . . . . . . . . . . . . . . . . . .

CSR45: Next Receive Status and Byte Count Upper 137. . . . . . . . . . . . . . . . . . . . . . . .

CSR46: Poll Time Counter 137. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR47: Polling Interval 137. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR48: Temporary Storage 2 Lower 138. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR49: Temporary Storage 2 Upper 138. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .









CSR58: Software Style 139. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR59: IR Register 140. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR60: Previous Transmit Descriptor Address Lower 140. . . . . . . . . . . . . . . . . . . . . . .

CSR61: Previous Transmit Descriptor Address Upper 140. . . . . . . . . . . . . . . . . . . . . . .

CSR62: Previous Transmit Status and Byte Count Lower 140. . . . . . . . . . . . . . . . . . . .

CSR63: Previous Transmit Status and Byte Count Upper 140. . . . . . . . . . . . . . . . . . . .

CSR64: Next Transmit Buffer Address Lower 141. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR65: Next Transmit Buffer Address Upper 141. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR66: Next Transmit Status and Byte Count Lower 141. . . . . . . . . . . . . . . . . . . . . . .

CSR67: Next Transmit Status and Byte Count Upper 141. . . . . . . . . . . . . . . . . . . . . . .

CSR68: Transmit Status Temporary Storage Lower 141. . . . . . . . . . . . . . . . . . . . . . . .

CSR69: Transmit Status Temporary Storage Upper 141. . . . . . . . . . . . . . . . . . . . . . . .

CSR70: Temporary Storage Lower 141. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR71: Temporary Storage Upper 141. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR72: Receive Ring Counter 141. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR74: Transmit Ring Counter 142. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR76: Receive Ring Length 142. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR78: Transmit Ring Length 142. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR80: Burst and FIFO Threshold Control 142. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR82: Bus Activity Timer 144. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR84: DMA Address Lower 144. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR85: DMA Address Upper 145. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR86: Buffer Byte Counter 145. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


9Am79C965

CSR88: Chip ID Lower 145. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR89: Chip ID Upper 145. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR92: Ring Length Conversion 145. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR94: Transmit Time Domain Reflectometry Count 146. . . . . . . . . . . . . . . . . . . . . . .

CSR96: Bus Interface Scratch Register 0 Lower 146. . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR97: Bus Interface Scratch Register 0 Upper 146. . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR98: Bus Interface Scratch Register 1 Lower 146. . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR99: Bus Interface Scratch Register 1 Upper 146. . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR100: Bus Time-out 146. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR104: SWAP Register Lower 147. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR105: SWAP Register Upper 147. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR108: Buffer Management Scratch Lower 147. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR109: Buffer Management Scratch Upper 147. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR112: Missed Frame Count 147. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR114: Receive Collision Count 148. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR122: Receive Frame Alignment Control 148. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSR124: Buffer Management Test 148. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BUS CONFIGURATION REGISTERS 150. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BCR0: Master Mode Read Active 150. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BCR1: Master Mode Write Active 151. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BCR2: Miscellaneous Configuration 151. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BCR4: Link Status LED (LNKST) 152. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BCR5: LED1 Status 153. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BCR6: LED2 Status 155. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BRC7:LED3 Status 156. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BCR16: I/O Base Address Lower 157. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BCR17: I/O Base Address Upper 158. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BCR18: Burst Size and Bus Control 158. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BCR19: EEPROM Control and Status 163. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BCR20: Software Style 166. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BCR21: Interrupt Control 167. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

INITIALIZATION BLOCK 168. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RLEN and TLEN 169. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RDRA and TDRA 169. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LADRF 169. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PADR 170. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MODE 170. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RECEIVE DESCRIPTORS 170. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RMD0 171. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RMD1 171. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RMD2 172. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RMD3 172. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TRANSMIT DESCRIPTORS 173. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TMD0 173. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TMD1 173. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


10 Am79C965

TMD2 174. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TMD3 175. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

REGISTER SUMMARY 176. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CSRs — Control and Status Registers 176. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BCRs — Bus Configuration Registers 180. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ABSOLUTE MAXIMUM RATINGS 181. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OPERATING RANGES 181. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DC CHARACTERISTICS 181. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SWITCHING CHARACTERISTICS 184. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BUS INTERFACE 184. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10BASE-T INTERFACE 186. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ATTACHMENT UNIT INTERFACE 186. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GENERAL PURPOSE SERIAL INTERFACE 187. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

EXTERNAL ADDRESS DETECTION INTERFACE 189. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

KEY TO SWITCHING WAVEFORMS 190. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SWITCHING TEST CIRCUITS 190. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ESTIMATED OUTPUT VALID DELAY VS. LOAD CAPACITANCE 192. . . . . . . . . . . . . . . . . . . .

SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE 192. . . . . . . . . . . . . . . . . . . . . . . . . .

SYSTEM BUS INTERFACE 193. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10BASE-T INTERFACE 198. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ATTACHMENT UNIT INTERFACE 200. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GENERAL PURPOSE SERIAL INTERFACE 203. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

EXTERNAL ADDRESS DETECTION INTERFACE 204. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DATA SHEET REVISION SUMMARY 207. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

APPENDIX A: PCNET-32 COMPATIBLE MEDIA INTERFACE MODULES A-1. . . . . . . . . . . . . .

APPENDIX B: RECOMMENDATION FOR POWER AND GROUND DECOUPLING B-1. . . . . . .

APPENDIX C: ALTERNATIVE METHOD FOR INITIALIZATION C-1. . . . . . . . . . . . . . . . . . . . . .

APPENDIX D: INTRODUCTION OF THE LOOK-AHEAD PACKET PROCESSING

CONCEPT D-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


11Am79C965

BLOCK DIAGRAM: VESA VL-BUS MODE

18219B-1

BufferManagement

Unit

FIFOControl

Microwire,LED,and

JTAGControl

VESAVL-Bus

InterfaceUnit

VLBENLB/VESA

ADSBRDY

BE0-BE3LCLK

WBACKBLAST

RDYRTNM/IOD/CW/R

INTR1-INTR4LREQLREQILGNT

LGNTOSLEEP

LDEVLEADSLBS16

LRDY

ADR2-ADR31DAT0-DAT31

RESET

EEDI

802.3MAC Core

ManchesterEncoder/Decoder(PLS) &AUI Port

10BASE-TMAU

LNKST

XTAL1

DO+/-

CI+/-

DI+/-

RXD+/-

TXD+/-

TXP+/-

XTAL2

EECSEESK

SHFBUSY

TCKTDITMSTDO

EEDO

LED1-LED3

RcvFIFO

XmtFIFO


12 Am79C965

CONNECTION DIAGRAM: VESA VL-BUS MODE

NC

160

159

SH

FB

US

Y

EE

CS

158

157

EE

SK

/LE

D1/

SF

BD

EE

DI/L

NK

ST

156

155

EE

DO

/LE

DP

RE

3/S

RD

154

153

INT

R1

AD

R18

152

151

AD

R19

AD

R20

150

149

DV

SS

N14

AD

R21

148

147

AD

R22

AD

R23

146

145

AD

R24

DV

DD

O5

144

143

AD

R25

AD

R26

142

141

DV

SS

N13

AD

R27

140

139

AD

R28

AD

R29

138

137

AD

R30

AD

R31

136

135

DV

SS

4

LB/V

ES

A

134

133

SLE

EP

DV

DD

3

AV

DD

213

113

0C

I+C

I-12

912

8D

I+D

I-12

712

6A

VD

D1

DO

+12

512

4D

O-

AV

SS

112

312

2N

CN

C12

1

132

NC120119 NC

XTAL2118117 AVSS2

XTAL1116115 AVDD3

TXD+114113 TXP+

TXD-112111 TXP-

AVDD4110109 RXD+

RXD-108107 DVSS3

JTAGSEL106105 INTR2/EAR

INTR3/TDI104103

LGNTO/TCKINTR4/TMS102

101LREQI/TDODAT0

10099

DAT1DVSSN11

9897

DAT2

DAT3

9695

DAT4DAT5

9493

DVDDO4DAT6DVSSN10

9190

DAT7DAT8

8988

DAT9

DVDD2

8786

DAT10DAT11

8584

DVSSN9DAT12

8382

NC81

92

41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 70 71 72 73 74 75 76 77 78 79 8069

NC

RD

YR

TN

LRD

YW

/RA

DS

M/IO BE

3D

/CR

ES

ET

BE

2D

VS

SN

5B

E1

BE

0W

BA

CK

DA

T31

DA

T30

DA

T29

DA

T28

DV

SS

N6

DA

T27

DA

T26

DA

T25

DA

T24

DA

T23

DV

DD

O3

DA

T22

DV

SS

N7

DA

T21

DA

T20

DA

T19

DV

SS

2

DA

T18

DA

T17

DV

SS

N8

DA

T16

DA

T15

DA

T14

DA

T13 NC

NC

NC 12LED2/SRDCLK

DVSSN1 34ADR17

ADR16 56ADR15

ADR14 78DVDDO1

ADR13 910ADR12

DVSSN2 1112ADR11

ADR10 1314ADR9

ADR8 1516ADR7

DVSSN3 1718ADR6

ADR5 1920DVSSPAD

ADR4 2122ADR3

DVSSN4 2324ADR2

LBS16 2526

LEADSDVSSCLK

2728

LCLKDVDDCLK

VLBEN3031

BLASTLGNT

3233

BRDYDVDDO2

3435

LREQDVSS1

3637

LDEV

DVDD1

3839NC

NC 40

29

DVSSN12

DV

SS

N15

18219B-2


13Am79C965

PIN DESIGNATIONS: VESA VL-BUS MODEListed by Pin Number

Pin # Name

1 NC

2 LED2/SRDCLK

3 DVSSN1

4 ADR17

5 ADR16

6 ADR15

7 ADR14

8 DVDDO1

9 ADR13

10 ADR12

11 DVSSN2

12 ADR11

13 ADR10

14 ADR9

15 ADR8

16 ADR7

17 DVSSN3

18 ADR6

19 ADR5

20 DVSSPAD

21 ADR4

22 ADR3

23 DVSSN4

24 ADR2

25 LBS16

26 DVDD1

27 LEADS

28 DVSSCLK

29 LCLK

30 DVDDCLK

31 VLBEN

32 BLAST

33 LGNT

34 BRDY

35 DVDDO2

36 LREQ

37 DVSS1

38 LDEV

39 NC

40 NC

Pin # Name

41 NC

42 RDYRTN

43 LRDY

44 W/R

45 ADS

46 M/IO

47 BE3

48 D/C

49 RESET

50 BE2

51 DVSSN5

52 BE1

53 BE0

54 WBACK

55 DAT31

56 DAT30

57 DAT29

58 DAT28

59 DVSSN6

60 DAT27

61 DAT26

62 DAT25

63 DAT24

64 DAT23

65 DVDDO3

66 DAT22

67 DVSSN7

68 DAT21

69 DVSS2

70 DAT20

71 DAT19

72 DAT18

73 DAT17

74 DVSSN8

75 DAT16

76 DAT15

77 DAT14

78 DAT13

79 NC

80 NC

Pin # Name

121 NC

122 NC

123 AVSS1

124 DO-

125 DO+

126 AVDD1

127 DI-

128 DI+

129 CI-

130 CI+

131 AVDD2

132 ADR31

133 ADR30

134 ADR29

135 DVDD3

136 DVSS4

137 ADR28

138 ADR27

139 DVSSN13

140 ADR26

141 ADR25

142 DVDDO5

143 ADR24

144 ADR23

145 ADR22

146 ADR21

147 DVSSN14

148 ADR20

149 ADR19

150 ADR18

151 INTR1

152 EEDO/LEDPRE3/SRD

153 LB/VESA

154 EEDI/LNKST

155 EESK/LED1/SFBD

156 SLEEP

157 EECS

158 DVSSN15

159 SHFBUSY

160 NC

Pin # Name

81 NC

82 DAT12

83 DVSSN9

84 DAT11

85 DAT10

86 DAT9

87 DAT8

88 DAT7

89 DVSSN10

90 DAT6

91 DVDDO4

92 DAT5

93 DAT4

94 DAT3

95 DVDD2

96 DAT2

97 DVSSN11

98 DAT1

99 DAT0

100 LREQI/TDO

101 LGNTO/TCK

102 INTR4/TMS

103 DVSSN12

104 INTR3/TDI

105 INTR2/EAR

106 JTAGSEL

107 DVSS3

108 RXD-

109 RXD+

110 AVDD4

111 TXP-

112 TXD-

113 TXP+

114 TXD+

115 AVDD3

116 XTAL1

117 AVSS2

118 XTAL2

119 NC

120 NC


14 Am79C965

PIN DESIGNATIONS: VESA VL-BUS MODEListed by Pin Name

Pin Name #

ADR2 24

ADR3 22

ADR4 21

ADR5 19

ADR6 18

ADR7 16

ADR8 15

ADR9 14

ADR10 13

ADR11 12

ADR12 10

ADR13 9

ADR14 7

ADR15 6

ADR16 5

ADR17 4

ADR18 150

ADR19 149

ADR20 148

ADR21 146

ADR22 145

ADR23 144

ADR24 143

ADR25 141

ADR26 140

ADR27 138

ADR28 137

ADR29 134

ADR30 133

ADR31 132

ADS 45

AVDD1 126

AVDD2 131

AVDD3 115

AVDD4 110

AVSS1 123

AVSS2 117

BE0 53

BE1 52

BE2 50

Pin Name #

BE3 47

BLAST 32

BRDY 34

CI+ 130

CI- 129

D/C 48

DAT0 99

DAT1 98

DAT2 96

DAT3 94

DAT4 93

DAT5 92

DAT6 90

DAT7 88

DAT8 87

DAT9 86

DAT10 85

DAT11 84

DAT12 82

DAT13 78

DAT14 77

DAT15 76

DAT16 75

DAT17 73

DAT18 72

DAT19 71

DAT20 70

DAT21 68

DAT22 66

DAT23 64

DAT24 63

DAT25 62

DAT26 61

DAT27 60

DAT28 58

DAT29 57

DAT30 56

DAT31 55

DI+ 128

DI- 127

Pin Name #

DO+ 125

DO- 124

DVDD1 26

DVDD2 95

DVDD3 135

DVDDCLK 30

DVDDO1 8

DVDDO2 35

DVDDO3 65

DVDDO4 91

DVDDO5 142

DVSS1 37

DVSS2 69

DVSS3 107

DVSS4 136

DVSSCLK 28

DVSSN1 3

DVSSN2 11

DVSSN3 17

DVSSN4 23

DVSSN5 51

DVSSN6 59

DVSSN7 67

DVSSN8 74

DVSSN9 83

DVSSN10 89

DVSSN11 97

DVSSN12 103

DVSSN13 139

DVSSN14 147

DVSSN15 158

DVSSPAD 20

EECS 157

EEDI/LNKST 154

EEDO/LEDPRE3/SRD 152

EESK/LED1/SFBD 155

INTR1 151

INTR2/EAR 105

INTR3/TDI 104

INTR4/TMS 102

Pin Name #

JTAGSEL 106

LB/VESA 153

LBS16 25

LCLK 29

LDEV 38

LEADS 27

LED2/SRDCLK 2

LGNT 33

LGNTO/TCK 101

LRDY 43

LREQ 36

LREQI/TDO 100

M/IO 46

NC 1

NC 39

NC 40

NC 41

NC 79

NC 80

NC 81

NC 119

NC 120

NC 121

NC 122

NC 160

RDYRTN 42

RESET 49

RXD+ 109

RXD- 108

SHFBUSY 159

SLEEP 156

TXD+ 114

TXD- 112

TXP+ 113

TXP- 111

VLBEN 31

W/R 44

WBACK 54

XTAL1 116

XTAL2 118


15Am79C965

PIN DESIGNATIONS: VESA VL-BUS MODEListed by Group

No. ofPin Name Pin Function Type Driver Pins

VESA VL-Bus Interface

ADR2–ADR31 Address Bus IO TS 30

ADS Address Status I/O TS 1

BE0–BE3 Byte Enable I/O TS 4

BLAST Burst Last O TS 1

BRDY Burst Ready I/O TS 1

D/C Data/Control Select I/O TS 1

DAT0–DAT31 Data Bus I/O TS 32

INTR1 Interrupt Number 1 O TS 1

INTR2 Interrupt Number 2 I/O TS 1



JTAGSEL JTAG Select I 1

LB/VESA Local Bus/VESA VL-Bus Select pin I 1

LBS16 Local Bus Size 16 I 1

LCLK Local Clock I 1

LDEV Local Device O O4 1

LEADS Local External Address Strobe O TS 1

LGNT Local Bus Grant I 1

LGNTO Local Grant Out I/O TS 1

LRDY Local Ready O TS 1

LREQ Local Bus Request O O8 1

LREQI Local Bus Request In I/O TS 1

M/IO Memory/I/O Select I/O TS 1

RDYRTN Ready Return I 1

RESET Reset I 1

VLBEN Burst Enable I 1

W/R Write/Read Select I/O TS 1

WBACK Write Back I 1

Board Interface

EECS Microwire Serial EEPROM Chip Select O O8 1

EEDI/LNKST Microwire Serial EEPROM Data In/Link Status O LED 1

EEDO/LEDPRE3 Microwire Address EEPROM Data Out/LED3 predriver I/O LED 1

EESK/LED1 Microwire Serial EEPROM Clock/LED1 O LED 1

LED2 LED Output Number 2 O LED 1

SHFBUSY Shift Busy (for external EEPROM-programmable logic) O O8 1

SLEEP Sleep Mode I 1

XTAL1 Crystal Input I 1

XTAL2 Crystal Output O 1


16 Am79C965

PIN DESIGNATIONS: VESA VL-BUS MODE (continued)Listed by Group


Attachment Unit Interface (AUI)

CI+/CI- AUI Collision Differential Pair I 2

DI+/DI- AUI Data In Differential Pair I 2

DO+/DO- AUI Data Out Differential Pair O DO 2

Twisted Pair Transceiver Interface (10BASE-T)

RXD+/RXD- Receive Differential Pair I 2

TXD+/TXD- Transmit Differential Pair O TDO 2

TXP+/TXP- Transmit Pre-Distortion Differential Pair O TPO 2

LNKST/EEDI Link Status/Microwire Serial EEPROM Data In O LED 1

IEEE 1149.1 Test Access Port Interface (JTAG)

TCK Test Clock I/O TS 1

TDI Test Data In I/O TS 1

TDO Test Data Out I/O TS 1

TMS Test Mode Select I/O TS 1

External Address Detection Interface (EADI)

EAR External Address Reject Low I/O TS 1

SRD Serial Receive Data I/O TS 1

SRDCLK Serial Receive Data Clock I/O TS 1

SFBD Start Frame-Byte Delimiter O LED 1

Power Supplies

AVDD Analog Power P 4

AVSS Analog Ground P 2

DVDD Digital Power P 3

DVDDCLK Digital Power Clock P 1

DVDDO I/O Buffer Digital Power P 5

DVSS Digital Ground P 4

DVSSCLK Digital Ground Clock P 1

DVSSN I/O Buffer Digital Ground P 15

DVSSPAD Digital Ground Pad P 1


17Am79C965

PIN DESIGNATIONS: VESA VL-BUS MODEDriver Type

IOL IOH Name Type (mA) (mA) pF

TS Tri-State 8 –0.4 50

O8 Totem Pole 8 –0.4 50


OD Open Drain 8 50

LED LED 12 –0.4 50

Table 1. Output Driver Types

Table 2. Pins with Pull-Ups

Signal Pull-up

TDI ≥ 10 KΩ

TMS ≥ 10 KΩ

TCK ≥ 10 KΩ


18 Am79C965

PIN DESCRIPTION: VESA VL-BUS MODEConfiguration PinsJTAGSELJTAG Function Select InputThe value of this pin will asynchronously select betweenJTAG Mode and Multi-Interrupt Mode.

The value of this pin will asynchronously affect the func-tion of the JTAG–INTR–Daisy chain arbitration pins,regardless of the state of the RESET pin and regardlessof the state of the LCLK pin. If the value is a “1”, then thePCnet-32 controller will be programmed for JTAGmode. If the value is a “0”, then the PCnet-32 controllerwill be programmed for Multi-Interrupt Mode.

When programmed for JTAG mode, four pins of thePCnet-32 controller will be configured as a JTAG(IEEE 1149.1) Test Access Port. When programmedfor Multi-Interrupt Mode, two of the JTAG pins willbecome interrupts and two JTAG pins will be used fordaisy chain arbitration support. Table 3 below outlinesthe pin changes that will occur by programming theJTAGSEL pin.

Table 3. JTAG Pin Changes

JTAGSEL=1 JTAGSEL=0Pin JTAG mode Multi-Interrupt Mode

LGNT0/TCK TCK LGNTO

LGNT1/TDO TDO LREQI

LGNT2/TDI TDI INTR3

LGNT3/TMS TMS INTR4

The JTAGSEL pin may be tied directly to VDD or VSS. Aseries resistor may be used but is not necessary.

LB/VESALocal Bus/VESA VL-Bus Select InputThe value of this pin will asynchronously determine theoperating mode of the PCnet-32 controller, regardlessof the state of the RESET pin and regardless of the stateof the LCLK pin. If the LB/VESA pin is a tied to VDD, thenthe PCnet-32 controller will be programmed for LocalBus Mode. If the LB/VESA pin is tied to VSS, then the

PCnet-32 controller will be programmed for VESA-VLBus Mode.

Note that the setting of LB/VESA determines thefunctionality of the following pins (names in parenthesesare pins in 486 local bus mode): VLBEN (Am486),RESET (RESET), LBS16 (AHOLD), LREQ (HOLD),LGNT (HLDA), LREQI (HOLDI) and LGNTO (HLDAO).

VLBENBurst Enable InputThis pin is used to determine whether or not bursting issupported by the PCnet-32 device in VESA VL-Busmode. The VLBEN pin is sampled at every rising edge ofLCLK while the RESET pin is asserted.

In VESA-VL mode (the LB/VESA pin is tied to VSS), if thesampled value of VLBEN is low, then the BREADE andBWRITE bits in BCR18 will be forced low, and thePCnet-32 controller will never attempt to perform linearburst reads or writes. If the sampled value of VLBEN ishigh, linear burst accesses are permitted, consistentwith the values programmed into BREADE andBWRITE.

Because of byte-duplication conventions within a 32-bitAm386 system, the PCnet-32 controller will always pro-duce the correct bytes in the correct byte lanes in accor-dance with the Am386DX data sheet. This byteduplication will automatically occur, regardless of theoperating mode selected by the LB/VESA pin.

The VLBEN pin may be tied directly to VDD or VSS. Aseries resistor may be used but is not necessary.

The VLBEN pin need only be valid when the RESET pinis active (regardless of the connection of the LB/VESApin) and may be tied to ID(3) in a VESA VL-Bus version1.0 system, or to the logical AND of ID(4), ID(3), ID(1),and ID(0) in a VESA-VL-Bus version 1.1 or 2.0 system.

Note: This pin needs to be tied low when the LB/VESApin has been tied to VDD. See the pin description for theAm486 pin in the Local Bus Mode section.

Configuration Pin Settings SummaryTable 4 below shows the possible pin configurationsthat may be invoked with the PCnet-32 controller con-figuration pins.

Table 4. Configuration Pin Settings

LB/VESA VLBEN JTAGSEL Mode Selected

0 X* 0 VL Bus mode with 4 interrupts and daisy chain arbitration

0 X* 1 VL Bus mode with 2 interrupts and JTAG

1 0 0 Am486 mode with 4 interrupts and daisy chain arbitration

1 0 1 Am486 mode with 2 interrupts and JTAG

1 1 X Reserved

*X = Don’t care


19Am79C965

Pin Connections to V DD or VSS

Several pins may be connected to VDD or VSS for variousapplication options. Some pins are required to be con-nected to VDD or VSS in order to set the controller into aparticular mode of operation, while other pins might beconnected to VDD or VSS if that pin’s function is not imple-mented in a specific application. Table 5 shows whichpins require a connection to VDD or VSS, and which pinsmay optionally be connected to VDD or VSS because theapplication does not support that pin’s function. Thetable also shows whether or not the connections need tobe resistive.

VESA VL-Bus Interface

ADR2–ADR31Address Bus Input/OutputAddress information which is stable during a bus opera-tion, regardless of the source. When the PCnet-32 con-troller is Current Master, A2–A31 will be driven. Whenthe PCnet-32 controller is not Current Master, theA2–A31 lines are continuously monitored to determine ifan address match exists for I/O slave transfers.

ADSAddress Status Input/OutputWhen driven LOW, this signal indicates that a valid buscycle definition and address are available on the M/IO,D/C, W/R and A2–A31 pins of the local bus interface. Atthat time, the PCnet-32 controller will examine the com-bination of M/IO, D/C, W/R, and the A2–A31 pins to

determine if the current access is directed toward thePCnet-32 controller.

ADS will be driven LOW when the PCnet-32 controllerperforms a bus master access on the local bus.

BE0–BE3Byte Enable Input/OutputThese signals indicate which bytes on the data bus areactive during read and write cycles. When BE3 is active,the byte on DAT31–DAT24 is valid. BE2–BE0 activeindicate valid data on pins DAT23–DAT16, DAT15–DAT8, DAT7–DAT0, respectively. The byte enable sig-nals are outputs for bus master and inputs for bus slaveoperations.

BLASTBurst Last OutputWhen the BLAST signal is asserted, then the next timethat BRDY or RDYRTN is asserted, the burst cycle iscomplete.

BRDYBurst Ready Input/OutputBRDY functions as an input to the PCnet-32 controllerduring bus master cycles. When BRDY is asserted dur-ing a master cycle, it indicates to the PCnet-32 controllerthat the target device is accepting burst transfers. It alsoserves the same function as RDYRTN does for non-burst accesses. That is, it indicates that the target de-vice has accepted the data on a master write cycle, orthat the target device has presented valid data onto thebus during master read cycles.

Table 5. Pin Connections to Power/Ground

ResistiveSupply Connection Recommended

Pin Name Pin No Strapping to Supply Resistor Size

LED2/SRDCLK 2 Required Required 324 Ω in series with LED, or 10 KΩ without LED

LBS16 25 Optional Required 10 KΩ

VLBEN 31 Required Optional NA

WBACK 54 Optional Required 10 KΩ

LREQI/TDO 100 Optional Required 10 KΩ

JTAGSEL 106 Required Optional NA

EEDO/LEDPRE3/SRD 152 Optional Required 10 KΩ

LB/VESA 153 Required Optional NA

EEDI/LNKST 154 Optional Required 324 Ω in series with LED, or 10 KΩ without LED

EESK/LED1/SFBD 155 Required Required 324 Ω in series with LED, or 10 KΩ without LED

SLEEP 156 Optional Required 10 KΩ

All Other Pins — Optional Required 10 KΩ


20 Am79C965

If BRDY and RDYRTN are sampled active in the samecycle, then RDYRTN takes precedence, causing thenext transfer cycle to begin with a T1 cycle.

BRDY functions as an output during PCnet-32 controllerslave cycles and is always driven inactive (HIGH).

BRDY is floated if the PCnet-32 controller is not beingaccessed as the current slave device on the local bus.

D/CData/Control Select Input/OutputDuring slave accesses to the PCnet-32 controller, theD/C pin, along with M/IO and W/R, indicates the type ofcycle that is being performed. PCnet-32 controller willonly respond to local bus accesses in which D/C isdriven HIGH by the local bus master.

During PCnet-32 controller bus master accesses, theD/C pin is an output and will always be driven HIGH.

D/C is floated if the PCnet-32 controller is not the currentmaster on the local bus.

DAT0–DAT31Data Bus Input/OutputUsed to transfer data to and from the PCnet-32 control-ler to system resources via the local bus. DAT31–DAT0are driven by the PCnet-32 controller when performingbus master writes and slave read operations. Data onDAT31–DAT0 is latched by the PCnet-32 controllerwhen performing bus master reads and slave writeoperations.

The PCnet-32 controller will always follow Am386DXbyte lane conventions. This means that for word andbyte accesses in which PCnet-32 controller drives thedata bus (i.e. master write operations and slave readoperations), the PCnet-32 controller will produce dupli-cates of the active bytes on the unused half of the 32-bitdata bus. Table 6 illustrates the cases in which duplicatebytes are created.

Table 6. Byte Duplication on Data Bus

BE3– DAT DAT DAT DATBE0 [31:24] [23:16] [15:8] [7:0]

1110 Undef Undef Undef A

1101 Undef Undef A Undef

1011 Undef A Undef Copy A

0111 A Undef Copy A Undef

1100 Undef Undef B A

1001 Undef C B Undef

0011 D C Copy D Copy C

1000 Undef C B A

0001 D C B Undef

0000 D C B A

INTR1–INTR4Interrupt Request OutputAn attention signal which indicates that one or more ofthe following status flags is set: BABL, MISS, MERR,RINT, IDON, MFCO, RCVCCO, TXSTRT, or JAB. Eachof these status flags has a mask bit which allows forsuppression of INTR assertion. These flags have themeaning shown in Table 7.

Table 7. Status Flags

BABL Babble (CSR0, bit 14)

MISS Missed Frame (CSR0, bit 12)

MERR Memory Error (CSR0, bit 11)

RINT Receive Interrupt (CSR0, bit 10)

IDON Initialization Done (CSR0, bit 8)

MFCO Missed Packet Count Overflow (CSR4, bit 9)

RCVCCO Receive Collision Count Overflow (CSR4, bit 5)

TXSTRT Transmit Start (CSR4, bit 3)

JAB Jabber (CSR4, bit 1)

Note that there are four possible interrupt pins, depend-ing upon the mode that has been selected with theJTAGSEL pin. Only one interrupt pin may be used atone time. The active interrupt pin is selected by pro-gramming the interrupt select register (BCR21). Thedefault setting of BCR121will select interrupt INTR1 asthe active interrupt. Note that BCR21 is EEPROM-pro-grammable. Inactive interrupt pins are floated.

The polarity of the interrupt signal is determined by theINTLEVEL bit of BCR2. The interrupt pins may beprogrammed for level-sensitive or edge-sensitiveoperation.

PCnet-32 controller interrupt pins will be floated atH_RESET and will remain floated until either theEEPROM has been successfully read, or, following anEEPROM read failure, a Software Relocatable Modesequence has been successfully executed.

LBS16Local Bus Size 16 InputLBS16 is sampled during PCnet-32 controller bus mas-tering activity to determine if the target device on theVL-Bus is 32 or 16 bits in width. If the LBS16 signal issampled active at least one clock period before the as-sertion of LRDY during a PCnet-32 controller bus mas-ter transfer, then the PCnet-32 controller will convert asingle 32-bit transfer into two 16-bit transfers. Not all32-bit transfers need to be split into two 16-bit transfers.Table 8 shows the sequence of transfers that will beexecuted for each possible 32-bit bus transfer that en-counters a proper assertion of the LBS16 signal.


21Am79C965

Table 8. Data Transfer Sequence from 32-Bit Wide to 16-Bit Wide

BE3 BE2 BE1 BE0 BE3 BE2 BE1 BE0

1 1 1 0 NR

1 1 0 0 NR

1 0 0 0 1 0 1 1

0 0 0 0 0 0 1 1

1 1 0 1 NR

1 0 0 1 1 0 1 1

0 0 0 1 0 0 1 1

1 0 1 1 NR

0 0 1 1 NR

0 1 1 1 NR

Next with LBS16Current Access

NR = No second access Required for these cases

During accesses in which PCnet-32 controller is actingas the VL-Bus target device, the LBS16 signal will not bedriven. In this case, it is expected that the VL-Busrequired pull-up device will bring the LBS16 signal to aninactive level and the PCnet-32 controller will be seen bythe VL-Bus master as a 32-bit peripheral.

LCLKLocal Clock InputLCLK is a 1x clock that follows the same phase as a486-type CPU clock. LCLK is always driven by the sys-tem logic or the VL-Bus controller to all VL-Bus mastersand targets. The rising edge of the clock signifies thechange of CPU states, and hence, the change ofPCnet-32 controller states.

LDEVLocal Device OutputLDEV is driven by the PCnet-32 controller when it recog-nizes an access to PCnet-32 controller I/O space. Suchrecognition is dependent upon a valid sampled ADSstrobe plus valid M/IO, D/C and ADR31–ADR5 values.

LEADSLocal External Address Strobe OutputDuring VL-Bus master write and read accesses theLEADS pin will be asserted on every T1 cycle as isspecified in the VESA VL-Bus specification, regardlessof the settings of the GCIC bit of BCR18 and the CLL bitsof BCR18.

LGNTLocal Bus Grant InputWhen LGNT is asserted and LREQ is being asserted bythe PCnet-32 controller, the PCnet-32 controller as-sumes ownership of the VL bus.

Note that this pin changes polarity when Local Busmode has been selected (see pin description of HLDA in486 Local Bus Interface section).

LGNTOLocal Grant Out OutputThis signal is multiplexed with the TCK pin, and is avail-able only when the Multi-Interrupt mode has been se-lected with the JTAGSEL pin.

An additional local bus master may daisy-chain itsLGNT signal through the PCnet-32 controller LGNTOpin. The PCnet-32 controller will deliver a LGNTO signalto the additional local bus master whenever thePCnet-32 controller receives a LGNT from the arbitra-tion logic, but is not simultaneously requesting the businternally. The second local bus master must connect itsLREQ output to the LREQI input of the PCnet-32 con-troller in order to complete the local bus daisy-chainarbitration control.

When SLEEP is not asserted, daisy chain arbitrationsignals that pass through the PCnet-32 controller willexperience a one-clock delay from input to output (i.e.LREQI to LREQ and LGNT to LGNTO).

While SLEEP is asserted (either in snooze mode orcoma mode), if the PCnet-32 controller is configured fora daisy chain (LREQI and LGNTO signals have beenselected with the JTAGSEL pin), then the system arbi-tration signal LGNT will be passed directly to the daisy-chain signal LGNTO without experiencing a one-clockdelay. However, some combinatorial delay will be intro-duced in this path.

Note that this pin changes polarity when Local Busmode has been selected (see pin description of HLDAOin 486 Local Bus Interface section).

LRDYLocal Ready OutputLRDY functions as an output from the PCnet-32 control-ler during PCnet-32 controller slave cycles. DuringPCnet-32 controller slave read cycles, LRDY is as-serted to indicate that valid data has been presented on


22 Am79C965

the data bus. During PCnet-32 controller slave writecycles, LRDY is asserted to indicate that the data on thedata bus has been internally latched. LRDY will be as-serted low for one clock period when the PCnet-32controller wishes to terminate the cycle. LRDY is thendriven high for one-half of one clock period before beingreleased.

LRDY is floated if the PCnet-32 controller is not thecurrent slave on the local bus.

LREQLocal Bus Request OutputLREQ is used by the PCnet-32 controller to gain controlof the VL-Bus and become the active VL Bus Master.LREQ is active low. Once asserted, LREQ remains ac-tive until LGNT has become active, independent of sub-sequent assertion of SLEEP or setting of the STOP bit oraccess to the S_RESET port (offset 14h).

Note that this pin changes polarity when Local Busmode has been selected (see pin description of HOLD in486 Local Bus Interface section).

LREQILocal Bus Request In InputThis signal is multiplexed with the TDO pin, and is avail-able only when the Multi-Interrupt mode has been se-lected with the JTAGSEL pin.

An additional local bus master may daisy-chain its bushold request signal through the PCnet-32 controllerLREQI pin. The PCnet-32 controller will convey theLREQI request to the arbitration logic via the PCnet-32controller LREQ output. The second local bus mastermust connect its LGNT input to the LGNTO output of thePCnet-32 controller in order to complete the local busdaisy-chain arbitration control.

When SLEEP is not asserted, daisy chain arbitrationsignals that pass through the PCnet-32 controller willexperience a one-clock delay from input to output (i.e.LREQI to LREQ and LGNT to LGNTO).

While SLEEP is asserted (either in snooze mode orcoma mode), if the PCnet-32 controller is configured fora daisy chain (LREQI and LGNTO signals have beenselected with the JTAGSEL pin), then the daisy-chainsignal LREQI will be passed directly to the system arbi-tration signal LREQ without experiencing a one-clockdelay. However, some combinatorial delay will be intro-duced in this path.

If Multi-Interrupt mode has been selected and the daisy-chain arbitration feature is not used, then the LREQIinput should be tied to VDD.

Note that this pin changes polarity when Local Busmode has been selected (see pin description of HOLDIin 486 Local Bus Interface section).

M/IOMemory I/O Select Input/OutputDuring slave accesses to the PCnet-32 controller, theM/IO pin, along with D/C and W/R, indicates the type ofcycle that is being performed. PCnet-32 controller willonly respond to local bus accesses in which M/IO issampled as a zero by the PCnet-32 controller.

During PCnet-32 controller bus master accesses, theM/IO pin is an output and will always be driven high.

M/IO is floated if the PCnet-32 controller is not the cur-rent master on the local bus.

RDYRTNReady Return InputRDYRTN functions as an input to the PCnet-32 control-ler. RDYRTN is used to terminate all master accessesperformed by the PCnet-32 controller, except that linearburst transfers may also be terminated with the BRDYsignal. RDYRTN is used to terminate slave readaccesses to PCnet-32 controller I/O space.

When asserted during slave read accesses to PCnet-32controller I/O space, RDYRTN indicates that the busmastering device has seen the LRDY that was gener-ated by the PCnet-32 controller and has accepted thePCnet-32 controller slave read data. Therefore,PCnet-32 controller will hold slave read data on the busuntil it synchronously samples the RDYRTN input asactive low. The PCnet-32 controller will not hold LRDYvalid asserted during this time. The duration of theLRDY pulse generated by the PCnet-32 controller willalways be a single LCLK cycle.

RDYRTN is ignored during slave write accesses toPCnet-32 controller I/O space. Slave write accesses toPCnet-32 controller I/O space are considered termi-nated by the PCnet-32 controller at the end of the cycleduring which the PCnet-32 controller issues an activeRDY.

In systems where both a LRDY and RDYRTN (orequivalent) signals are provided, then LRDY must notbe tied to RDYRTN. Most systems now provide for alocal device ready input to the memory controller that isseparate from the CPU READY signal. This secondREADY signal is usually labeled as READYIN. Thissignal should be connected to the PCnet-32 controllerLRDY signal. The CPU READY signal should be con-nected to the PCnet-32 controller RDYRTN pin.

In systems where only one READY signal is provided,then the PCnet-32 controller LRDY output may be tied tothe PCnet-32 controller RDYRTN input.


23Am79C965

RESETSystem Reset InputWhen RESET is asserted low and the LB/VESA pin hasbeen tied to VSS, then the PCnet-32 controller performsan internal system reset of the H_RESET type (HARD-WARE_RESET). The RESET pin must be held for aminimum of 30 LCLK periods when VL mode has beenselected. While in the H_RESET state, the PCnet-32controller will float or deassert all outputs.

W/RWrite/Read Select Input/OutputDuring slave accesses to the PCnet-32 controller, theW/R pin, along with D/C and M/IO, indicates the type ofcycle that is being performed.

During PCnet-32 controller bus master accesses, theW/R pin is an output.

W/R is floated if the PCnet-32 controller is not the cur-rent master on the local bus.

WBACKWrite Back InputWBACK is monitored as in input during VL-Bus MasterAccesses. When PCnet-32 controller is current VL-Busmaster, the PCnet-32 controller will float all appropriatebus mastering signals within 1 clock period of the asser-tion of WBACK. When WBACK is deasserted, PCnet-32controller will re-execute any accesses that were sus-pended due to the assertion of WBACK and then willproceed with other scheduled accesses, if any.

Register access cannot be performed to the PCnet-32device while WBACK is asserted.

Board Interface

LED1LED1 OutputThis pin is shared with the EESK function. When operat-ing as LED1, the function and polarity on this pin areprogrammable through BCR5. The LED1 output fromthe PCnet-32 controller is capable of sinking the neces-sary 12 mA of current to drive an LED directly.

The LED1 pin is also used during EEPROM Auto-detec-tion to determine whether or not an EEPROM is presentat the PCnet-32 controller microwire interface. At thetrailing edge of RESET, this pin is sampled to determinethe value of the EEDET bit in BCR19. A sampled HIGHvalue means that an EEPROM is present, and EEDETwill be set to ONE. A sampled LOW value means that anEEPROM is not present, and EEDET will be set toZERO. See the “EEPROM Auto-detection” section formore details.

If no LED circuit is to be attached to this pin, then apull-up or pull-down resistor must be attached instead,in order to resolve the EEDET setting.

LED2LED2 OutputThis pin is shared with the SRDCLK function. Whenoperating as LED2, the function and polarity on this pinare programmable through BCR6. The LED2 outputfrom the PCnet-32 controller is capable of sinking thenecessary 12 mA of current to drive an LED directly.

This pin also selects address width for SoftwareRelocatable Mode. When this pin is HIGH during Soft-ware Relocatable Mode, then the device will be pro-grammed to use 32 bits of addressing while snoopingaccesses on the bus during Software RelocatableMode. When this pin is LOW during SoftwareRelocatable Mode, then the device will be programmedto use 24 bits of addressing while snooping accesses onthe bus during Software Relocatable Mode. The upper 8bits of address will be assumed to match during thesnooping operation when LED2 is LOW. The 24-bit ad-dressing mode is intended for use in systems that em-ploy the GPSI signals. For more information on theGPSI function see section General Purpose SerialInterface.

If no LED circuit is to be attached to this pin, then a pullup or pull down resistor must be attached instead, inorder to resolve the Software Relocatable Mode ad-dress width setting.

LEDPRE3LEDPRE3 OutputThis pin is shared with the EEDO function. When operat-ing as LEDPRE3, the function and polarity on this pinare programmable through BCR7. This signal is labeledas LED “PRE” 3 because of the multi-function nature ofthis pin. If an LED circuit were directly attached to thispin, it would create an IOL requirement that could not bemet by the serial EEPROM that would also be attachedto this pin. Therefore, if this pin is to be used as anadditional LED output while an EEPROM is used in thesystem, then buffering is required between theLEDPRE3 pin and the LED circuit. If no EEPROM isincluded in the system design, then the LEDPRE3 sig-nal may be directly connected to an LED without buffer-ing. The LEDPRE3 output from the PCnet-32 controlleris capable of sinking the necessary 12 mA of current todrive an LED in this case. For more details regardingLED connection, see the section on LEDs.

LNKSTLink Status OutputThis pin provides 12 mA for driving an LED. It indicatesan active link connection on the 10BASE-T interface.The function and polarity are programmable throughBCR4. Note that this pin is multiplexed with the EEDIfunction.

This pin remains active in snooze mode.


24 Am79C965

SHFBUSYShift Busy OutputThe function of the SHFBUSY signal is to indicate whenthe last byte of the EEPROM contents has been shiftedout of the EEPROM on the EEDO signal line. This infor-mation is useful for external EEPROM-programmableregisters that do not use the microwire protocol, as isdescribed herein: When the PCnet-32 controller isperforming a serial read of the EEPROM through themicrowire interface, the SHFBUSY signal will be drivenHIGH. SHFBUSY can serve as a serial shift enable toallow the EEPROM data to be serially shifted into anexternal device or series of devices. The SHFBUSYsignal will remain actively driven HIGH until the end ofthe EEPROM read operation. If the EEPROM check-sum was verified, then the SHFBUSY signal will bedriven LOW at the end of the EEPROM read operation.If the EEPROM checksum verification failed, then theSHFBUSY signal will remain HIGH. This function effec-tively demarcates the end of a successful EEPROMread operation and therefore is useful as a programma-ble-logic low-active output enable signal. For more de-tails on external EEPROM-programmable registers,see the EEPROM Microwire Access section underHardware Access.

This pin can be controlled by the host system by writingto BCR19, bit 3 (EBUSY).

SLEEPSleep InputWhen SLEEP input is asserted (active LOW), thePCnet-32 controller performs an internal system reset ofthe S_RESET type and then proceeds into a powersavings mode. (The reset operation caused by SLEEPassertion will not affect BCR registers.) All outputs willbe placed in their normal S_RESET condition. Duringsleep mode, all PCnet-32 controller inputs will be ig-nored except for the SLEEP pin itself. De-assertion ofSLEEP results in wake-up. The system must refrainfrom starting the network operations of the PCnet-32controller for 0.5 seconds following the deassertion ofthe SLEEP signal in order to allow internal analog cir-cuits to stabilize.

Both LCLK and XTAL1 inputs must have valid clocksignals present in order for the SLEEP command to takeeffect.

If SLEEP is asserted while LREQ is asserted, then thePCnet-32 controller will perform an internal systemS_RESET and then wait for the assertion of LGNT.When LGNT is asserted, the LREQ signal will be deas-serted and then the PCnet-32 controller will proceed tothe power savings mode. Note that the internal systemS_RESET will not cause the LREQ signal to bedeasserted.

The SLEEP pin should not be asserted during powersupply ramp-up. If it is desired that SLEEP be assertedat power up time, then the system must delay the

assertion of SLEEP until three LCLK cycles after thecompletion of a valid pin RESET operation.

XTAL1–XTAL2Crystal Oscillator Inputs Input/OutputThe crystal frequency determines the network data rate.The PCnet-32 controller supports the use of quartzcrystals to generate a 20 MHz frequency compatiblewith the ISO 8802-3 (IEEE/ANSI 802.3) network fre-quency tolerance and jitter specifications. See the sec-tion External Crystal Characteristics (in sectionManchester Encoder/Decoder) for more detail.

The network data rate is one-half of the crystal fre-quency. XTAL1 may alternatively be driven using anexternal CMOS level source, in which case XTAL2 mustbe left unconnected. Note that when teh PCnet-32 con-troller is in coma mode, there is an internal 22 KΩ resis-tor from XTAL1 to ground. If an external source drivesXTAL1, some power will be consumed driving this resis-tor. If XTAL1 is driven LOW at this time power consump-tion will be minimized. In this case, XTAL1 must remainactive for at least 30 cycles after the assertion of SLEEPand deassertion of LREQ.

Microwire EEPROM Interface

EESKEEPROM Serial Clock OutputThe EESK signal is used to access the external ISO8802-3 (IEEE/ANSI 802.3) address PROM. This pin isdesigned to directly interface to a serial EEPROM thatuses the microwire interface protocol. EESK is con-nected to the microwire EEPROM’s Clock pin. It is con-trolled by either the PCnet-32 controller directly during aread of the entire EEPROM, or indirectly by the hostsystem by writing to BCR19, bit 1.

EESK can be used during programming of externalEEPROM-programmable registers that do not use themicrowire protocol as follows:

When the PCnet-32 controller is performing a serialread of the IEEE Address EEPROM through themicrowire interface, the SHFBUSY signal will serve as aserial shift enable to allow the EEPROM data to beserially shifted into an external device or series of de-vices. This same signal can be used to gate the output ofthe programmed logic to avoid the problem of releasingintermediate values to the rest of the system board logic.The EESK signal can serve as the clock, and EEDO willserve as the input data stream to the programmableshift register.

EEDOEEPROM Data Out InputThe EEDO signal is used to access the external ISO8802-3 (IEEE/ANSI 802.3) address PROM. This pin isdesigned to directly interface to a serial EEPROM thatuses the microwire interface protocol. EEDO is con-nected to the microwire EEPROM’s Data Output pin. It


25Am79C965

is controlled by the EEPROM during reads. It may beread by the host system by reading BCR19, bit 0.

EEDO can be used during programming of externalEEPROM-programmable registers that do not use themicrowire protocol as follows:


EECSEEPROM Chip Select OutputThe function of the EECS signal is to indicate to themicrowire EEPROM device that it is being accessed.The EECS signal is active high. It is controlled by eitherthe PCnet-32 controller during a read of the entireEEPROM, or indirectly by the host system by writing toBCR19, bit 2.

EEDIEEPROM Data In OutputThe EEDI signal is used to access the external ISO8802-3 (IEEE/ANSI 802.3) address PROM. EEDI func-tions as an output. This pin is designed to directly inter-face to a serial EEPROM that uses the microwireinterface protocol. EEDI is connected to the microwireEEPROM’s Data Input pin. It is controlled by either thePCnet-32 controller during command portions of a readof the entire EEPROM, or indirectly by the host systemby writing to BCR19, bit 0.

Attachment Unit Interface

CI±Collision In InputA differential input pair signaling the PCnet-32 controllerthat a collision has been detected on the network media,indicated by the CI± inputs being driven with a 10 MHzpattern of sufficient amplitude and pulse width to meetISO 8802-3 (IEEE/ANSI 802.3) standards. Operates atpseudo ECL levels.

DI±Data In InputA differential input pair to the PCnet-32 controller carry-ing Manchester encoded data from the network. Oper-ates at pseudo ECL levels.

DO±Data Out OutputA differential output pair from the PCnet-32 controller fortransmitting Manchester encoded data to the network.Operates at pseudo ECL levels.

Twisted Pair Interface

RXD±10-BASE-T Receive Data Input10BASE-T port differential receivers.

TXD±10BASE-T Transmit Data Output10BASE-T port differential drivers.

TXP±10BASE-T Pre-distortion Control OutputThese outputs provide transmit predistortion control inconjunction with the 10BASE-T port differential drivers.

External Address Detection Interface

The EADI interface is enabled through bit 3 ofBCR2 (EADISEL).

EARExternal Address Reject Low InputAn EADI input signal. The incoming frame will bechecked against the internally active address detectionmechanisms and the result of this check will be OR’dwith the value on the EAR pin. The EAR pin is defined asREJECT.

See the EADI section for details regarding the functionand timing of this signal.

Note that this pin is multiplexed with the INTR2 pin.

SFBDStart Frame–Byte Delimiter OutputStart Frame–Byte Delimiter Enable. EADI output signal.An initial rising edge on this signal indicates that a startof frame delimiter has been detected. The serial bitstream will follow on the SRD signal, commencing withthe destination address field. SFBD will go high for 4 bittimes (400 ns) after detecting the second “1” in the SFD(Start of Frame Delimiter) of a received frame. SFBD willsubsequently toggle every 400 ns (1.25 MHz frequency)with each rising edge indicating the first bit of each sub-sequent byte of the received serial bit stream. SFBD willbe inactive during frame transmission.

Note that this pin is multiplexed with the LED1 pin.


26 Am79C965

SRDSerial Receive Data OutputAn EADI output signal. SRD is the decoded NRZ datafrom the network. This signal can be used for externaladdress detection. Note that when the 10BASE-Tport is selected, transitions on SRD will only occur dur-ing receive activity. When the AUI port is selected, tran-sitions on SRD will occur during both transmit andreceive activity.

Note that this pin is multiplexed with the LEDPRE3 pin.

SRDCLKSerial Receive Data Clock OutputAn EADI output signal. Serial Receive Data is synchro-nous with reference to SRDCLK. Note that when the10BASE-T port is selected, transitions on SRDCLK willonly occur during receive activity. When the AUI port isselected, transitions on SRDCLK will occur during bothtransmit and receive activity.


General Purpose Serial Interface

The GPSI interface is selected through the PORTSELbits of the Mode register (CSR15) and enabled throughthe TSTSHDW[1] bit (BCR18) or the CORETESTbit (CSR124).

Note that when GPSI test mode is invoked, slave ad-dress decoding must be restricted to the lower 24 bits ofthe address bus by setting the IOAW24 bit in BCR2 andby pulling LED2 LOW during Software RelocatableMode. The upper 8 bits of the address bus will always beconsidered matched when examining incoming I/O ad-dresses. During master accesses while in GPSI mode,the PCnet-32 controller will not drive the upper 8 bits ofthe address bus with address information. See the GPSIsection for more detail.

TXDATTransmit Data Input/OutputTXDAT is an output, providing the serial bit stream fortransmission, including preamble, SFD data and FCSfield, if applicable.

Note that the TxDAT pin is multiplexed with the A31 pin.

TXENTransmit Enable Input/OutputTXEN is an output, providing an enable signal for trans-mission. Data on the TXDAT pin is not valid unless theTXEN signal is HIGH.

Note that the TXEN pin is multiplexed with the A30 pin.

STDCLKSerial Transmit Data Clock InputSTDCLK is an input, providing a clock signal for MACactivity, both transmit and receive. Rising edges of theSTDCLK can be used to validate TXDAT output data.

The STDCLK pin is multiplexed with the A29 pin.

Note that this signal must meet the frequency stabilityrequirement of the ISO 8802-3 (IEEE/ANSI 802.3)specification for the crystal.

CLSNCollision Input/OutputCLSN is an input, indicating to the core logic that acollision has occurred on the network.

Note that the CLSN pin is multiplexed with the A28 pin.

RXCRSReceive Carrier Sense Input/OutputRXCRS is an input. When this signal is HIGH, it indi-cates to the core logic that the data on the RXDAT inputpin is valid.

Note that the RXCRS pin is multiplexed with the A27 pin.

SRDCLKSerial Receive Data Clock Input/OutputSRDCLK is an input. Rising edges of the SRDCLK sig-nal are used to sample the data on the RXDAT inputwhenever the RXCRS input is HIGH.

Note that the SRDCLK pin is multiplexed with theA26 pin.

RXDATReceive Data Input/OutputRXDAT is an input. Rising edges of the SRDCLK signalare used to sample the data on the RXDAT input when-ever the RXCRS input is HIGH.

Note that the RXDAT pin is multiplexed with the A25 pin.

IEEE 1149.1 Test Access Port Interface

TCKTest Clock InputThe clock input for the boundary scan test mode opera-tion. TCK can operate up to 10 MHz. If left unconnected,this pin has a default value of HIGH.

TDITest Data Input InputThe test data input path to the PCnet-32 controller. If leftunconnected, this pin has a default value of HIGH.

TDOTest Data Output OutputThe test data output path from the PCnet-32 controller.TDO is floated when the JTAG port is inactive.

TMSTest Mode Select InputA serial input bit stream is used to define the specificboundary scan test to be executed. If left unconnected,this pin has a default value of HIGH.


27Am79C965

Power Supply Pins

AVDDAnalog Power (4 Pins) PowerThere are four analog +5 Volt supply pins. Special atten-tion should be paid to the printed circuit board layout toavoid excessive noise on these lines. Refer to Appen-dix B and the PCnet Family Technical Manual (PID#18216A) for details.

AVSSAnalog Ground (2 Pins) PowerThere are two analog ground pins. Special attentionshould be paid to the printed circuit board layout to avoidexcessive noise on these lines. Refer to Appendix B andthe PCnet Family Technical Manual for details.

DVDDDigital Power (3 Pins) PowerThere are 3 digital power supply pins (DVDD1, DVDD 2,and DVDD3) used by the internal digital circuitry.

DVDDCLKDigital Power Clock (1 Pin) PowerThis pin is used to supply power to the clock bufferingcircuitry.

DVDDOI/O Buffer Digital Power (5 Pins) PowerThere are 5 digital power supply pins (DVDDO1–DVDDO5) used by Input/Output buffer drivers.

DVSSDigital Ground (4 Pins) GroundThere are 4 digital ground pins (DVSS1–DVSS4) usedby the internal digital circuitry.

DVSSCLKDigital Ground Clock (1 Pin) GroundThis pin is used to supply a ground to the clock bufferingcircuitry.

DVSSNI/O Buffer Digital Ground (15 Pins) GroundThese 15 ground pins (DVSSN1–DVSSN15) are usedby the Input/Output buffer drivers.

DVSSPADDigital Ground Pad (1 Pin) GroundThis pin is used by the Input/Output logic circuits.


28 Am79C965

VESA VL-BUS / LOCAL BUS PIN CROSS-REFERENCEListed by Pin Number

Pin VESA VL-Bus Mode Local Bus Mode # Pin Name Pin Name

1 NC NC

2 LED2/SRDCLK LED2/SRDCLK

3 DVSSN1 DVSSN1

4 ADR17 A17

5 ADR16 A16

6 ADR15 A15

7 ADR14 A14

8 DVDDO1 DVDDO1

9 ADR13 A13

10 ADR12 A12

11 DVSSN2 DVSSN2

12 ADR11 A11

13 ADR10 A10

14 ADR9 A9

15 ADR8 A8

16 ADR7 A7

17 DVSSN3 DVSSN3

18 ADR6 A6

19 ADR5 A5

20 DVSSPAD DVSSPAD

21 ADR4 A4

22 ADR3 A3

23 DVSSN4 DVSSN4

24 ADR2 A2

25 LBS16 AHOLD

26 DVDD1 DVDD1

27 LEADS EADS

28 DVSSCLK DVSSCLK

29 LCLK BCLK

30 DVDDCLK DVDDCLK

31 VLBEN Am486

32 BLAST BLAST

33 LGNT HLDA

34 BRDY BRDY

35 DVDDO2 DVDDO2

36 LREQ HOLD

37 DVSS1 DVSS1

38 LDEV LDEV

39 NC NC

40 NC NC


41 NC NC

42 RDYRTN RDYRTN

43 LRDY RDY

44 W/R W/R

45 ADS ADS

46 M/IO M/IO

47 BE3 BE3

48 D/C D/C

49 RESET RESET

50 BE2 BE2

51 DVSSN5 DVSSN5

52 BE1 BE1

53 BE0 BE0

54 WBACK BOFF

55 DAT31 D31

56 DAT30 D30

57 DAT29 D29

58 DAT28 D28

59 DVSSN6 DVSSN6

60 DAT27 D27

61 DAT26 D26

62 DAT25 D25

63 DAT24 D24

64 DAT23 D23

65 DVDDO3 DVDDO3

66 DAT22 D22

67 DVSSN7 DVSSN7

68 DAT21 D21

69 DVSS2 DVSS2

70 DAT20 D20

71 DAT19 D19

72 DAT18 D18

73 DAT17 D17

74 DVSSN8 DVSSN8

75 DAT16 D16

76 DAT15 D15

77 DAT14 D14

78 DAT13 D13

79 NC NC

80 NC NC


29Am79C965

VESA VL-BUS/LOCAL BUS PIN CROSS-REFERENCE (continued)Listed by Pin Number


81 NC NC

82 DAT12 D12

83 DVSSN9 DVSSN9

84 DAT11 D11

85 DAT10 D10

86 DAT9 D9

87 DAT8 D8

88 DAT7 D7

89 DVSSN10 DVSSN10

90 DAT6 D6

91 DVDDO4 DVDDO4

92 DAT5 D5

93 DAT4 D4

94 DAT3 D3

95 DVDD2 DVDD2

96 DAT2 D2

97 DVSSN11 DVSSN11

98 DAT1 D1

99 DAT0 D0

100 LREQI/TDO HOLDI/TDO

101 LGNTO/TCK HLDAO/TCK

102 INTR4/TMS INTR4/TMS

103 DVSSN12 DVSSN12

104 INTR3/TDI INTR3/TDI

105 INTR2/EAR INTR2/EAR

106 JTAGSEL JTAGSEL

107 DVSS3 DVSS3

108 RXD- RXD-

109 RXD+ RXD+

110 AVDD4 AVDD4

111 TXP- TXP-

112 TXD- TXD-

113 TXP+ TXP+

114 TXD+ TXD+

115 AVDD3 AVDD3

116 XTAL1 XTAL1

117 AVSS2 AVSS2

118 XTAL2 XTAL2

119 NC NC

120 NC NC


121 NC NC

122 NC NC

123 AVSS1 AVSS1

124 DO- DO-

125 DO+ DO+

126 AVDD1 AVDD1

127 DI- DI-

128 DI+ DI+

129 CI- CI-

130 CI+ CI+

131 AVDD2 AVDD2

132 ADR31 A31

133 ADR30 A30

134 ADR29 A29

135 DVDD3 DVDD3

136 DVSS4 DVSS4

137 ADR28 A28

138 ADR27 A27

139 DVSSN13 DVSSN13

140 ADR26 A26

141 ADR25 A25

142 DVDDO5 DVDDO5

143 ADR24 A24

144 ADR23 A23

145 ADR22 A22

146 ADR21 A21

147 DVSSN14 DVSSN14

148 ADR20 A20

149 ADR19 A19

150 ADR18 A18

151 INTR1 INTR1

152 EEDO/LEDPRE3/SRD EEDO/LEDPRE3/SRD

153 LB/VESA LB/VESA

154 EEDI/LNKST EEDI/LNKST

155 EESK/LED1/SFBD EESK/LED1/SFBD

156 SLEEP SLEEP

157 EECS EECS

158 DVSSN15 DVSSN15

159 SHFBUSY SHFBUSY

160 NC NC


30 Am79C965

BLOCK DIAGRAM: 486 LOCAL BUS MODE

18219B-3

BufferManagement

Unit

FIFOControl

Microwire,LED,and

JTAGControl

486Local BusInterface

Unit

Am486LB/VESA

ADSBRDY

BE0-BE3BCLK

BOFFBLAST

RDYRTNM/IOD/CW/R

INTR1-INTR4HOLD

HOLDIHLDA

HLDAOSLEEP

LDEVEADS

AHOLD

RDY

A2-A31D0-D31

RESET

EEDI

802.3MAC Core

ManchesterEncoder/Decoder(PLS) &AUI Port

10BASE-TMAU

LNKST

XTAL1

DO+/-

CI+/-

DI+/-

RXD+/-

TXD+/-

TXP+/-

XTAL2

EECSEESK

SHFBUSY

TCKTDITMSTDO

EEDO

LED1-LED3

RcvFIFO

XmtFIFO


31Am79C965

CONNECTION DIAGRAM: 486 LOCAL BUS MODE

18219B-4

NC

160

159

SH

FB

US

Y

EE

CS

158

157

EE

SK

/LE

D1/

SF

BD

EE

DI/L

NK

ST

156

155

EE

DO

/LE

DP

RE

3/S

RD

154

153

INT

R1

A18

152

151

A19

A20

150

149

DV

SS

N14

A21

148

147

A22

A23

146

145

A24

DV

DD

O5

144

143

A25

A26

142

141

DV

SS

N13

A27

140

139

A28

A29

138

137

A30

A31

136

135

DV

SS

4

LB/V

ES

A

134

133

SLE

EP

DV

DD

3

AV

DD

213

113

0C

I+C

I-12

912

8D

I+D

I-12

712

6A

VD

D1

DO

+12

512

4D

O-

AV

SS

112

312

2N

CN

C12

1

132

NC120119 NC

XTAL2118117 AVSS2

XTAL1116115 AVDD3

TXD+114113 TXP+

TXD-112111 TXP-

AVDD4110109 RXD+

RXD-108107 DVSS3

JTAGSEL106105 INTR2/EAR

INTR3/TDI104103

HLDAO/TCKINTR4/TMS102

101HOLDI/TDOD0

10099

D1DVSSN11

9897

D2

D3

9695

D4D5

9493

DVDDO4D6DVSSN10

9190

D7D8

8988

D9

DVDD2

8786

D10D11

8584

DVSSN9D12

8382

NC81

92

41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 70 71 72 73 74 75 76 77 78 79 8069

NC

RD

YR

TN

RD

YW

/RA

DS

M/IO BE

3D

/CR

ES

ET

BE

2D

VS

SN

5B

E1

BE

0B

OF

FD

31D

30D

29D

28D

VS

SN

6D

27D

26D

25D

24D

23D

VD

DO

3D

22D

VS

SN

7D

21

D20

D19

DV

SS

2

D18

D17

DV

SS

N8

D16

D15

D14

D13 NC

NC

NC 12LED2/SRDCLK

DVSSN1 34A17

A16 56A15

A14 78DVDD01

A13 910A12

DVSSN2 1112A11

A10 1314A9

A8 1516A7

DVSSN3 1718A6

A5 1920DVSSPAD

A4 2122A3

DVSSN4 2324A2

AHOLD 2526

EADSDVSSCLK

2728

BCLKDVDDCLK

Am4863031

BLASTHLDA

3233

BRDYDVDDO2

3435

HOLDDVSS1

3637

LDEV

DVDD1

3839NC

NC 40

29

DVSSN12

DV

SS

N15


32 Am79C965

PIN DESIGNATIONS: 486 LOCAL BUS MODEListed by Pin Number

Pin # Name

1 NC

2 LED2/SRDCLK

3 DVSSN1

4 A17

5 A16

6 A15

7 A14

8 DVDDO1

9 A13

10 A12

11 DVSSN2

12 A11

13 A10

14 A9

15 A8

16 A7

17 DVSSN3

18 A6

19 A5

20 DVSSPAD

21 A4

22 A3

23 DVSSN4

24 A2

25 AHOLD

26 DVDD1

27 EADS

28 DVSSCLK

29 BCLK

30 DVDDCLK

31 Am486

32 BLAST

33 HLDA

34 BRDY

35 DVDDO2

36 HOLD

37 DVSS1

38 LDEV

39 NC

40 NC

Pin # Name

41 NC

42 RDYRTN

43 RDY

44 W/R

45 ADS

46 M/IO

47 BE3

48 D/C

49 RESET

50 BE2

51 DVSSN5

52 BE1

53 BE0

54 BOFF

55 D31

56 D30

57 D29

58 D28

59 DVSSN6

60 D27

61 D26

62 D25

63 D24

64 D23

65 DVDDO3

66 D22

67 DVSSN7

68 D21

69 DVSS2

70 D20

71 D19

72 D18

73 D17

74 DVSSN8

75 D16

76 D15

77 D14

78 D13

79 NC

80 NC

Pin # Name

121 NC

122 NC

123 AVSS1

124 DO-

125 DO+

126 AVDD1

127 DI-

128 DI+

129 CI-

130 CI+

131 AVDD2

132 A31

133 A30

134 A29

135 DVDD3

136 DVSS4

137 A28

138 A27

139 DVSSN13

140 A26

141 A25

142 DVDDO5

143 A24

144 A23

145 A22

146 A21

147 DVSSN14

148 A20

149 A19

150 A18

151 INTR1

152 EEDO/LEDPRE3/SRD

153 LB/VESA

154 EEDI/LNKST

155 EESK/LED1/SFBD

156 SLEEP

157 EECS

158 DVSSN15

159 SHFBUSY

160 NC

Pin # Name

81 NC

82 D12

83 DVSSN9

84 D11

85 D10

86 D9

87 D8

88 D7

89 DVSSN10

90 D6

91 DVDDO4

92 D5

93 D4

94 D3

95 DVDD2

96 D2

97 DVSSN11

98 D1

99 D0

100 HOLDI/TDO

101 HLDAO/TCK

102 INTR4/TMS

103 DVSSN12

104 INTR3/TDI

105 INTR2/EAR

106 JTAGSEL

107 DVSS3

108 RXD-

109 RXD+

110 AVDD4

111 TXP-

112 TXD-

113 TXP+

114 TXD+

115 AVDD3

116 XTAL1

117 AVSS2

118 XTAL2

119 NC

120 NC


33Am79C965

PIN DESIGNATIONS: 486 LOCAL BUS MODEListed by Pin Name

Pin Name #

A2 24

A3 22

A4 21

A5 19

A6 18

A7 16

A8 15

A9 14

A10 13

A11 12

A12 10

A13 9

A14 7

A15 6

A16 5

A17 4

A18 150

A19 149

A20 148

A21 146

A22 145

A23 144

A24 143

A25 141

A26 140

A27 138

A28 137

A29 134

A30 133

A31 132

ADS 45

AHOLD 25

Am486 31

AVDD1 126

AVDD2 131

AVDD3 115

AVDD4 110

AVSS1 123

AVSS2 117

BCLK 29

Pin Name #

BE0 53

BE1 52

BE2 50

BE3 47

BLAST 32

BOFF 54

BRDY 34

CI+ 130

CI- 129

D/C 48

D0 99

D1 98

D2 96

D3 94

D4 93

D5 92

D6 90

D7 88

D8 87

D9 86

D10 85

D11 84

D12 82

D13 78

D14 77

D15 76

D16 75

D17 73

D18 72

D19 71

D20 70

D21 68

D22 66

D23 64

D24 63

D25 62

D26 61

D27 60

D28 58

D29 57

Pin Name #

D30 56

D31 55

DI+ 128

DI- 127

DO+ 125

DO- 124

DVDD1 26

DVDD2 95

DVDD3 135

DVDDCLK 30

DVDDO1 8

DVDDO2 35

DVDDO3 65

DVDDO4 91

DVDDO5 142

DVSS1 37

DVSS2 69

DVSS3 107

DVSS4 136

DVSSCLK 28

DVSSN1 3

DVSSN2 11

DVSSN3 17

DVSSN4 23

DVSSN5 51

DVSSN6 59

DVSSN7 67

DVSSN8 74

DVSSN9 83

DVSSN10 89

DVSSN11 97

DVSSN12 103

DVSSN13 139

DVSSN14 147

DVSSN15 158

DVSSPAD 20

EADS 27

EECS 157

EEDI/LNKST 154

EEDO/LEDPRE3/SRD 152

Pin Name #

EESK/LED1/SFBD 155

HLDA 33

HLDAO/TCK 101

HOLD 36

HOLDI/TDO 100

INTR1 151

INTR2/EAR 105

INTR3/TDI 104

INTR4/TMS 102

JTAGSEL 106

LB/VESA 153

LDEV 38

LED2/SRDCLK 2

M/IO 46

NC 1

NC 39

NC 40

NC 41

NC 79

NC 80

NC 81

NC 119

NC 120

NC 121

NC 122

NC 160

RDY 43

RDYRTN 42

RESET 49

RXD+ 109

RXD- 108

SHFBUSY 159

SLEEP 156

TXD+ 114

TXD- 112

TXP+ 113

TXP- 111

W/R 44

XTAL1 116

XTAL2 118


34 Am79C965

PIN DESIGNATIONS: 486 LOCAL BUS MODEListed by Group


486/386DX Local Bus Interface

A2–A31 Address Bus IO TS 30

ADS Address Status I/O TS 1

AHOLD Address Hold I 1

Am486 Am486 Mode Select I 1

BCLK Bus Clock I 1

BE0–BE3 Byte Enable I/O TS 4

BLAST Burst Last O TS 1

BOFF Backoff I 1

BRDY Burst Ready I/O TS 1

D/C Data/Control Select I/O TS 1

D0–D31 Data Bus I/O TS 32

EADS External Address Strobe O TS 1

HLDA Hold Acknowledge I 1

HLDAO Hold Acknowledge Out I/O TS 1

HOLD Hold Request O O8 1

HOLDI Hold Request In I/O TS 1

INTR1 Interrupt Number 1 O TS 1




JTAGSEL JTAG Select I 1

LB/VESA Local Bus/VESA VL-Bus Select pin I 1

LDEV Local Device O O4 1

M/IO Memory/I/O Select I/O TS 1

RDY Ready O TS 1

RDYRTN Ready Return I 1

W/R Write/Read Select I/O TS 1

Board Interface

EECS Microwire Serial PROM Chip Select O O8 1

EEDI/LNKST Microwire Serial EEPROM Data In/Link Status O LED 1

EEDO/LEDPRE3 Microwire Address PROM Data Out/LED3 predriver I/O LED 1

EESK/LED1 Microwire Serial PROM Clock/LED1 O LED 1

LED2 LED output number 2 O LED 1

RESET Reset I 1

SHFBUSY Shift Busy (for external EEPROM-programmable logic) O O8 1

SLEEP Sleep Mode I 1

XTAL1 Crystal Input I 1

XTAL2 Crystal Output O 1


35Am79C965

PIN DESIGNATIONS: 486 LOCAL BUS MODEListed by Group


Attachment Unit Interface (AUI)

CI+/CI- AUI Collision Differential Pair I 2

DI+/DI- AUI Data In Differential Pair I 2

DO+/DO- AUI Data Out Differential Pair O DO 2

Twisted Pair Transceiver Interface (10BASE-T)

RXD+/RXD- Receive Differential Pair I 2

TXD+/TXD- Transmit Differential Pair O TDO 2

TXP+/TXP- Transmit Pre-distortion Differential Pair O TPO 2

LNKST/EEDI Link Status/microwire Serial EEPROM Data In O LED 1

IEEE 1149.1 Test Access Port Interface (JTAG)

TCK Test Clock I/O TS 1

TDI Test Data In I/O TS 1

TDO Test Data Out I/O TS 1

TMS Test Mode Select I/O TS 1

External Address Detection Interface (EADI)

EAR External Address Reject Low I/O TS 1

SRD Serial Receive Data I/O TS 1

SRDCLK Serial Receive Data Clock I/O TS 1

SFBD Start Frame - Byte Delimiter O LED 1

Power Supplies

AVDD Analog Power P 4

AVSS Analog Ground P 2

DVDD Digital Power P 3

DVDDCLK Digital Power Clock P 1

DVDDO I/O Buffer Digital Power P 5

DVSS Digital Ground P 4

DVSSCLK Digital Ground Clock P 1

DVSSN I/O Buffer Digital Ground P 15

DVSSPAD Digital Ground Pad P 1


36 Am79C965

PIN DESIGNATIONS: 486 LOCAL BUS MODEDriver Type

IOL IOH Name Type (mA) (mA) pF

TS Tri-State 8 –0.4 50



OD Open Drain 8 50

LED LED 12 –0.4 50

Table 9. Output Driver Types

Table 10. Pins with Pull-Ups

Signal Pull-up

TDI ≥ 10 KΩ

TMS ≥ 10 KΩ

TCK ≥ 10 KΩ


37Am79C965

PIN DESCRIPTION: 486 LOCAL BUS MODEConfiguration PinsJTAGSELJTAG Function Select InputThe value of this pin will asynchronously select betweenJTAG Mode and Multi-Interrupt Mode.

The value of this pin will asynchronously affect the func-tion of the JTAG–INTR–Daisy chain arbitration pins,regardless of the state of the RESET pin and regardlessof the state of the BCLK pin. If the value is a “1”, then thePCnet-32 controller will be programmed for JTAGmode. If the value is a “0”, then the PCnet-32 controllerwill be programmed for Multi-Interrupt Mode.

When programmed for JTAG mode, four pins of thePCnet-32 controller will be configured as a JTAG(IEEE 1149.1) Test Access Port. When programmed forMulti-Interrupt Mode, two of the JTAG pins will becomeinterrupts and two JTAG pins will be used for daisy chainarbitration support. Table 11 below outlines the pinchanges that will occur by programming theJTAGSEL pin.

Table 11. JTAG Pin Changes

JTAGSEL=1 JTAGSEL=0Pin JTAG mode Multi-Interrupt Mode

HLDAO/TCK TCK HLDAO

HOLDI/TDO TDO HOLDI

INTR3/TDI TDI INTR3

INTR4/TMS TMS INTR4

The JTAGSEL pin may be tied directly to VDD or VSS.A series resistor may be used but is not necessary.

LB/VESALocal Bus/VESA VL-Bus Select InputThe value of this pin will asynchronously determine theoperating mode of the PCnet-32 controller, regardlessof the state of RESET and regardless of the state of theBCLK pin. If the LB/VESA pin is tied to VDD, then thePCnet-32 controller will be programmed for Local BusMode. If the LB/VESA pin is tied to VSS, then thePCnet-32 controller will be programmed for VESA VL-Bus Mode.

Note that the setting of LB/VESA determines the func-tionality of the following pins (names in parentheses arepins in the VESA VL-Bus Mode): Am486 (VLBEN),RESET (RESET), AHOLD (LBS16), HOLD (LREQ),HLDA(LGNT), HOLDI (LREQI), and HLDAO (LGNTO).

Am486Am486 Mode Select InputThe Am486 pin should be tied directly to VSS. A seriesresistor may be used but is not necessary.

Note: This pin is used to enable bursing in the VESA VL-Bus mode when the LB/VESA pin has been tied to VSS.See the pin description for the VLBEN pin in the VESAVL-Bus Mode section.

Configuration Pin Settings SummaryTable 12 shows the possible pin configurations that maybe invoked with the PCnet-32 controller configurationpins.

Table 12. Configuration Pin Settings

LB/VESA Am486/Am386 JTAGSEL Mode Selected

0 X* 0 VL Bus mode with 4 interrupts and daisy chain arbitration

0 X* 1 VL Bus mode with 2 interrupts and JTAG

1 0 0 Am486 mode with 4 interrupts and daisy chain arbitration

1 0 1 Am486 mode with 2 interrupts and JTAG

1 1 X Reserved

*X = Don’t care


38 Am79C965

Table 13. Pin Connections to Power/Ground

ResistiveSupply Connection Recommended

Pin Name Pin No Strapping to Supply Resistor Size

LED2/SRDCLK 2 Required Required 324 Ω in series with LED, or 10 KΩwithout LED

AHOLD 25 Optional Required 10 KΩ

Am486 31 Required Optional NA

BOFF 54 Optional Required 10 KΩ

HOLDI/TDO 100 Optional Required 10 KΩ

JTAGSEL 106 Required Optional NA

EEDO/LEDPRE3/SRD 152 Optional Required 10 KΩ

LB/VESA 153 Required Optional NA

EEDI/LNKST 154 Optional Required 324 Ω in series with LED, or 10 KΩ without LED

EESK/LED1/SFBD 155 Required Required 324 Ω in series with LED, or 10 KΩ without LED

SLEEP 156 Optional Required 10 KΩ

All Other Pins — Optional Required 10 KΩ

Pin Connections to V DD or VSS

Several pins may be connected to VDD or VSS for variousapplication options. Some pins are required to be con-nected to VDD or VSS in order to set the controller into aparticular mode of operation, while other pins might beconnected to VDD or VSS if that pin’s function is not imple-mented in a specific application. Table 13 shows whichpins require a connection to VDD or VSS, and which pinsmay optionally be connected to VDD or VSS because theapplication does not support that pin’s function. Thetable also shows whether or not the connections need tobe resistive.

Local Bus Interface

A2–A31Address Bus Input/OutputAddress information which is stable during a bus opera-tion, regardless of the source. When the PCnet-32 con-troller is Current Master, A1–A31 will be driven. Whenthe PCnet-32 controller is not Current Master, theA2–A31 lines are continuously monitored to determine ifan address match exists for I/O slave transfers.

Some portion of the Address Bus will be floated at thetime of an address hold operation, which is signaled withthe AHOLD pin. The number of Address Bus pins to befloated will be determined by the value of the Cache LineLength register (BCR18, bits 15-11).

ADSAddress Status Input/OutputWhen driven LOW, this signal indicates that a valid buscycle definition and address are available on the M/IO,D/C, W/R and A2–A31 pins of the local bus interface. Atthat time, the PCnet-32 controller will examine the com-bination of M/IO, D/C, W/R, and the A2–A31 pins todetermine if the current access is directed toward thePCnet-32 controller.

ADS will be driven LOW when the PCnet-32 controllerperforms a bus master access on the local bus.

AHOLDAddress Hold InputThis pin is always an input. The PCnet-32 controller willput some portion of the address bus into a high imped-ance state whenever this signal is asserted. AHOLDmay be asserted by an external cache controller when acache invalidation cycle is being performed. AHOLDmay be asserted at any time, including times when thePCnet-32 controller is the active bus master. Note thatthis pin is multiplexed with a VESA VL function: LBS16.

Some portion of the Address Bus will be floated at thetime of an address hold operation, which is signaled withthe AHOLD pin. The number of Address Bus pins to befloated will be determined by the value of the Cache LineLength (CLL) register (BCR18, bits 15-11) as shown inTable 14.


39Am79C965

Table 14. CLL Value and Floating Address Pins

Floated Portion of Address Bus During AHOLD

00000 None

00001 A31–A2

00010 A31–A3

00011 Reserved CLL Value

00100 A31–A4

00101–00111 Reserved CLL Values

01000 A31–A5


10000 A31–A6


CLL Value

BCLKBus Clock InputClock input that provides timing edges for all interfacesignals. This clock is used to drive the system bus inter-face and the internal buffer management unit. This clockis NOT used to drive the network functions.

BE0–BE3Byte Enable Input/OutputThese signals indicate which bytes on the data bus areactive during read and write cycles. When BE3 is active,the byte on D31–D24 is valid. BE2–BE0 active indicatevalid data on pins D23–D16, D15–D8, D7–D0, respec-tively. The byte enable signals are outputs for bus mas-ter and inputs for bus slave operations.

BLASTBurst Last OutputWhen the BLAST signal is asserted, then the next timethat BRDY or RDYRTN is asserted, the burst cycleis complete.

BOFFBackoff InputBOFF is monitored as an input during Bus Master ac-cesses. When PCnet-32 controller is current local busmaster, it will float all appropriate bus mastering signalswithin 1 clock period of the assertion of BOFF. WhenBOFF is deasserted, PCnet-32 controller will restart anyaccesses that were suspended due to the assertion ofBOFF and then will proceed with other scheduled ac-cesses, if any. Register access cannot be performed tothe PCnet-32 device while BOFF is asserted.

BRDYBurst Ready Input/OutputBRDY functions as an input to the PCnet-32 controllerduring bus master cycles. When BRDY is asserted dur-ing a master cycle, it indicates to the PCnet-32 controllerthat the target device is accepting burst transfers. It alsoserves the same function as RDYRTN does for non-burst accesses. That is, it indicates that the target de-vice has accepted the data on a master write cycle, or

that the target device has presented valid data onto thebus during master read cycles.

If BRDY and RDYRTN are sampled active in the samecycle, then RDYRTN takes precedence, causing thenext transfer cycle to begin with a T1 cycle.

BRDY functions as an output during PCnet-32 controllerslave cycles and is always driven inactive (HIGH).

BRDY is floated if the PCnet-32 controller is not beingaccessed as the current slave device on the local bus.

D/CData/Control Select Input/OutputDuring slave accesses to the PCnet-32 controller, theD/C pin, along with M/IO and W/R, indicates the type ofcycle that is being performed. PCnet-32 controller willonly respond to local bus accesses in which D/C isdriven HIGH by the local bus master.

During PCnet-32 controller bus master accesses, theD/C pin is an output and will always be driven HIGH.

D/C is floated if the PCnet-32 controller is not the currentmaster on the local bus.

D0–D31Data Bus Input/OutputUsed to transfer data to and from the PCnet-32 control-ler to system resources via the local bus. D31–D0 aredriven by the PCnet-32 controller when performing busmaster writes and slave read operations. Data onD31–D0 is latched by the PCnet-32 controller whenperforming bus master reads and slave writeoperations.

The PCnet-32 controller will always follow Am386DXbyte lane conventions. This means that for word andbyte accesses in which PCnet-32 controller drives thedata bus (i.e. master write operations and slave readoperations) the PCnet-32 controller will produce dupli-cates of the active bytes on the unused half of the 32-bitdata bus. Table 15 illustrates the cases in which dupli-cate bytes are created.


40 Am79C965

Table 15. Byte Duplication on Data Bus

BE3– DAT DAT DAT DATBE0 [31:24] [23:16] [15:8] [7:0]

1110 Undef Undef Undef A

1101 Undef Undef A Undef

1011 Undef A Undef Copy A

0111 A Undef Copy A Undef

1100 Undef Undef B A

1001 Undef C B Undef

0011 D C Copy D Copy C

1000 Undef C B A

0001 D C B Undef

0000 D C B A

EADSExternal Address Strobe OutputDuring master write accesses in which Generate CacheInvalidation Cycles mode has been selected, the EADSpin will be asserted as part of the PCnet-32 controllercache invalidation cycle. Cache invalidation cycles willoccur as often as a new cache line is reached. Thecache line size can be set with the cache line length bitsof BCR18 (bits [15:11]).

HLDABus Hold Acknowledge InputPCnet-32 controller examines the HLDA signal to deter-mine when it has been granted ownership of the bus.HLDA is active HIGH.

When HLDA is asserted and HOLD is being asserted bythe PCnet-32 controller, the PCnet-32 controller as-sumes ownership of the local bus. However, if thePCnet-32 controller is asserting HOLD because HOLDIis asserted (as in a daisy chain arbitration), thenPCnet-32 controller will assert HLDAO and will not as-sume ownership of the local bus.

Note that it changes polarity when the VL mode is se-lected (see pin description of LGNT in VESA VL-Bus In-terface section).

HLDAOBus Hold Acknowledge Out OutputThis signal is multiplexed with the TCK pin, and is avail-able only when the Multi-Interrupt mode has been se-lected with the JTAGSEL pin.

An additional local bus master may daisy-chain itsHLDA signal through the PCnet-32 controller HLDAOpin. The PCnet-32 controller will deliver a HLDAO signalto the additional local bus master whenever thePCnet-32 controller receives a HLDA from the CPU, butis not simultaneously requesting the bus internally. Thesecond local bus master must connect its HOLD output

to the HOLDI input of the PCnet-32 controller in order tocomplete the local bus daisy-chain arbitration control.

When SLEEP is not asserted, daisy chain arbitrationsignals that pass through the PCnet-32 controller willexperience a one-clock delay from input to output (i.e.HOLDI to HOLD and HLDA to HLDAO).

While SLEEP is asserted (either in snooze mode orcoma mode), if the PCnet-32 controller is configured fora daisy chain (HOLDI and HLDAO signals have beenselected with the JTAGSEL pin), then the system arbi-tration signal HLDA will be passed directly to the daisy-chain signal HLDAO without experiencing a one-clockdelay. However, some combinatorial delay will be intro-duced in this path.

Note that this pin changes polarity when VL mode hasbeen selected (see pin description of LGNTO in VESAVL-Bus Interface section).

HOLDBus Hold Request OutputPCnet-32 controller asserts the HOLD pin as a signalthat it wishes to become the local bus master. HOLD isactive high. Once asserted, HOLD remains active untilHLDA has become active, independent of subsequentassertion of SLEEP or setting of the STOP bit or accessto the S_RESET port (offset 14h).

Note that this pin changes polarity when the VL mode isselected (see pin description of LREQ in VESA VL-BusInterface section).

HOLDIBus Hold Request In InputThis signal is multiplexed with the TDO pin, and is avail-able only when the Multi-Interrupt mode has been se-lected with the JTAGSEL pin.

An additional local bus master may daisy-chain its bushold request signal through the PCnet-32 controllerHOLDI pin. The PCnet-32 controller will convey theHOLDI request to the CPU via the PCnet-32 controllerHOLD output. The second local bus master must con-nect its HLDA input to the HLDAO output of thePCnet-32 controller in order to complete the local busdaisy-chain arbitration control.

When SLEEP is not asserted, daisy chain arbitrationsignals that pass through the PCnet-32 controller willexperience a one-clock delay from input to output (i.e.HOLDI to HOLD and HLDA to HLDAO).

While SLEEP is asserted (either in snooze mode orcoma mode), if the PCnet-32 controller is configured fora daisy chain (HOLDI and HLDAO signals have beenselected with the JTAGSEL pin), then the daisy-chainsignal HOLDI will be passed directly to the system arbi-tration signal HOLD without experiencing a one-clockdelay. However, some combinatorial delay will be intro-duced in this path.


41Am79C965

If Multi-Interrupt mode has been selected and the daisy-chain arbitration feature is not used, then the HOLDIinput should be tied to VSS through a resistor.

Note that this pin changes polarity when VL mode hasbeen selected (see pin description of LREQI in VESAVL-Bus Interface section).

INTR1–INTR4Interrupt Request OutputAn attention signal which indicates that one or more ofthe following status flags is set: BABL, MISS, MERR,RINT, IDON, MFCO, RCVCCO, TXSTRT, or JAB. Eachof these status flags has a mask bit which allows forsuppression of INTR assertion. These flags have themeaning shown in Table 16.

Table 16. Status Flags

BABL Babble (CSR0, bit 14)

MISS Missed Frame (CSR0, bit 12)

MERR Memory Error (CSR0, bit 11)

RINT Receive Interrupt (CSR0, bit 10)

IDON Initialization Done (CSR0, bit 8)

MFCO Missed Packet Count Overflow (CSR4, bit 9)

RCVCCO Receive Collision Count Overflow (CSR4, bit 5)

TXSTRT Transmit Start (CSR4, bit 3)

JAB Jabber (CSR4, bit 1)

Note that there are four possible interrupt pins, depend-ing upon the mode that has been selected with theJTAGSEL pin. Only one interrupt pin may be used atone time. The active interrupt pin is selected by pro-gramming the interrupt select register (BCR21). The de-fault setting of BCR121will select interrupt INTR1 as theactive interrupt. Note that BCR21 is EEPROM-program-mable. Inactive interrupt pins are floated.

The polarity of the interrupt signal is determined by theINTLEVEL bit of BCR2. The interrupt pins may beprogrammed for level-sensitive or edge-sensitiveoperation.

PCnet-32 controller interrupt pins will be floated atH_RESET and will remain floated until either theEEPROM has been successfully read, or, following anEEPROM read failure, a Software Relocatable Modesequence has been successfully executed.

LDEVLocal Device OutputLDEV is driven by the PCnet-32 controller when it recog-nizes an access to PCnet-32 controller I/O space. Suchrecognition is dependent upon a valid sampled ADSstrobe plus valid M/IO, D/C and A31–A5 values.

M/IOMemory I/O Select Input/OutputDuring slave accesses to the PCnet-32 controller, theM/IO pin, along with D/C and W/R, indicates the type ofcycle that is being performed. PCnet-32 controller willonly respond to local bus accesses in which M/IO issampled as a zero by the PCnet-32 controller.

During PCnet-32 controller bus master accesses, theM/IO pin is an output and will always be driven high.

M/IO is floated if the PCnet-32 controller is not the cur-rent master on the local bus.

RESETSystem Reset InputWhen RESET is asserted high and the LB/VESA pin hasbeen tied to VDD, then the PCnet-32 controller performsan internal system reset of the type H_RESET (HARD-WARE_RESET). The RESET pin must be held for aminimum of 30 BCLK periods. While in the H_RESETstate, the PCnet-32 controller will float or deassert alloutputs.

Note that this pin changes polarity when VL mode hasbeen selected (see pin description of RESET in VESAVL-Bus Interface section).

RDYReady OutputRDY functions as an output from the PCnet-32 control-ler during PCnet-32 controller slave cycles. DuringPCnet-32 controller slave read cycles, RDY is assertedto indicate that valid data has been presented on thedata bus. During PCnet-32 controller slave write cycles,RDY is asserted to indicate that the data on the data bushas been internally latched. RDY is asserted for oneBCLK period. RDY is then driven high for one-half of oneclock period before being released.

RDY is floated if the PCnet-32 controller is not the cur-rent slave on the local bus.

In systems where both RDY and RDYRTN (or equiva-lent) signals are provided, RDY must NOT be tied toRDYRTN. Most systems now provide for a local deviceready input to the memory controller that is separatefrom the CPU READY signal. This second READY sig-nal is usually labeled as READYIN. This signal shouldbe connected to the PCnet-32 controller RDY signal.The CPU READY signal should be connected to thePCnet-32 controller RDYRTN pin.

In systems where only one READY signal is provided,then RDY may be tied to RDYRTN.

RDYRTNReady Return InputRDYRTN functions as an input to the PCnet-32 control-ler. RDYRTN is used to terminate all master accesses


42 Am79C965

performed by the PCnet-32 controller, except that linearburst transfers may also be terminated with the BRDYsignal. RDYRTN is used to terminate slave read ac-cesses to PCnet-32 controller I/O space.

When asserted during slave read accesses to PCnet-32controller I/O space, RDYRTN indicates that the busmastering device has seen the RDY that was generatedby the PCnet-32 controller and has accepted thePCnet-32 controller slave read data. Therefore,PCnet-32 controller will hold slave read data on the busuntil it synchronously samples the RDYRTN input asactive low. The PCnet-32 controller will not hold RDYvalid asserted during this time. The duration of the RDYpulse generated by the PCnet-32 controller will alwaysbe a single BCLK cycle.

RDYRTN is ignored during slave write accesses toPCnet-32 controller I/O space. Slave write accesses toPCnet-32 controller I/O space are considered termi-nated by the PCnet-32 controller at the end of the cycleduring which the PCnet-32 controller issues anactive RDY.

In systems where both a RDY and RDYRTN (or equiva-lent) signals are provided, then RDY must not be tied toRDYRTN. Most systems now provide for a local deviceready input to the memory controller that is separatefrom the CPU READY signal. This second READY sig-nal is usually labeled as READYIN. This signal shouldbe connected to the PCnet-32 controller RDY signal.The CPU READY signal should be connected to thePCnet-32 controller RDYRTN pin.

In systems where only one READY signal is provided,then the PCnet-32 controller RDY output may be tied tothe PCnet-32 controller RDYRTN input.

W/RWrite/Read Select Input/OutputDuring slave accesses to the PCnet-32 controller, theW/R pin, along with D/C and M/IO, indicates the type ofcycle that is being performed.

During PCnet-32 controller bus master accesses, theW/R pin is an output.

W/R is floated if the PCnet-32 controller is not the cur-rent master on the local bus.

Board Interface

LED1LED1 OutputThis pin is shared with the EESK function. When operat-ing as LED1, the function and polarity on this pin areprogrammable through BCR5. The LED1 output fromthe PCnet-32 controller is capable of sinking the neces-sary 12 mA of current to drive an LED directly.

The LED1 pin is also used during EEPROM Auto-detec-tion to determine whether or not an EEPROM is presentat the PCnet-32 controller microwire interface. At the

trailing edge of RESET, this pin is sampled to determinethe value of the EEDET bit in BCR19. A sampled HIGHvalue means that an EEPROM is present, and EEDETwill be set to ONE. A sampled LOW value means that anEEPROM is not present, and EEDET will be set toZERO. See the “EEPROM Auto-detection” section formore details.

If no LED circuit is to be attached to this pin, then apull-up or pull-down resistor must be attached instead,in order to resolve the EEDET setting.

LED2LED2 OutputThis pin is shared with the SRDCLK function. Whenoperating as LED2, the function and polarity on this pinare programmable through BCR6. The LED2 outputfrom the PCnet-32 controller is capable of sinking thenecessary 12 mA of current to drive an LED directly.

This pin also selects address width for SoftwareRelocatable Mode. When this pin is HIGH during Soft-ware Relocatable Mode, then the device will be pro-grammed to use 32 bits of addressing while snoopingaccesses on the bus during Software RelocatableMode. When this pin is LOW during SoftwareRelocatable Mode, then the device will be programmedto use 24 bits of addressing while snooping accesses onthe bus during Software Relocatable Mode. The upper8 bits of address will be assumed to match during thesnooping operation when LED2 is LOW. The 24-bit ad-dressing mode is intended for use in systems that em-ploy the GPSI signals. For more information on theGPSI function see section General Purpose SerialInterface.

If no LED circuit is to be attached to this pin, then a pullup or pull down resistor must be attached instead, inorder to resolve the Software Relocatable Mode ad-dress setting.

LEDPRE3LEDPRE3 OutputThis pin is shared with the EEDO function. When operat-ing as LEDPRE3, the function and polarity on this pinare programmable through BCR7. This signal is labeledas LED “PRE” 3 because of the multi-function nature ofthis pin. If an LED circuit were directly attached to thispin, it would create an IOL requirement that could not bemet by the serial EEPROM that would also be attachedto this pin. Therefore, if this pin is to be used as anadditional LED output while an EEPROM is used in thesystem, then buffering is required between theLEDPRE3 pin and the LED circuit. If no EEPROM isincluded in the system design, then the LEDPRE3 sig-nal may be directly connected to an LED without buffer-ing. The LEDPRE3 output from the PCnet-32 controlleris capable of sinking the necessary 12 mA of current todrive an LED in this case. For more details regardingLED connection, see the section on LEDs.


43Am79C965

LNKSTLINK Status OutputThis pin provides 12 mA for driving an LED. It indicatesan active link connection on the 10BASE-T interface.The signal is programmable through BCR4. Note thatthis pin is multiplexed with the EEDI function.

This pin remains active in snooze mode.

SHFBUSYShift Busy OutputThe function of the SHFBUSY signal is to indicate whenthe last byte of the EEPROM contents has been shiftedout of the EEPROM on the EEDO signal line. This infor-mation is useful for external EEPROM-programmableregisters that do not use the microwire protocol, as isdescribed herein: When the PCnet-32 controller is per-forming a serial read of the EEPROM through themicrowire interface, the SHFBUSY signal will be drivenHIGH. SHFBUSY can serve as a serial shift enable toallow the EEPROM data to be serially shifted into anexternal device or series of devices. The SHFBUSYsignal will remain actively driven HIGH until the end ofthe EEPROM read operation. If the EEPROM check-sum was verified, then the SHFBUSY signal will bedriven LOW at the end of the EEPROM read operation.If the EEPROM checksum verification failed, then theSHFBUSY signal will remain HIGH. This function effec-tively demarcates the end of a successful EEPROMread operation and therefore is useful as a programma-ble-logic low-active output enable signal. For more de-tails on external EEPROM-programmable registers,see the EEPROM. Microwire Access section underHardware Access.

This pin can be controlled by the host system by writingto BCR19, bit 3 (EBUSY).

SLEEPSleep InputWhen SLEEP input is asserted (active LOW), thePCnet-32 controller performs an internal system resetand then proceeds into a power savings mode. (Thereset operation caused by SLEEP assertion will not af-fect BCR registers.) All outputs will be placed in theirnormal reset condition. During sleep mode, all PCnet-32controller inputs will be ignored except for the SLEEPpin itself. De-assertion of SLEEP results in wake-up.The system must refrain from starting the network op-erations of the PCnet-32 controller for 0.5 secondsfollowing the deassertion of the SLEEP signal in order toallow internal analog circuits to stabilize.

Both BCLK and XTAL1 inputs must have valid clocksignals present in order for the SLEEP command totake effect.

If SLEEP is asserted while LREQ/HOLD is asserted,then the PCnet-32 controller will perform an internalsystem reset and then wait for the assertion of LGNT/HLDA. When LGNT/HLDA is asserted, the LREQ/

HOLD signal will be deasserted and then the PCnet-32controller will proceed to the power savings mode. Notethat the internal system reset will not cause theHOLD/LREQ signal to be deasserted.

The SLEEP pin should not be asserted during powersupply ramp-up. If it is desired that SLEEP be assertedat power up time, then the system must delay the asser-tion of SLEEP until three BCLK cycles after the comple-tion of a valid pin RESET operation.

XTAL1–XTAL2Crystal Oscillator Inputs Input/OutputThe crystal frequency determines the network data rate.The PCnet-32 controller supports the use of quartz crys-tals to generate a 20 MHz frequency compatible with theISO 8802-3 (IEEE/ANSI 802.3) network frequency toler-ance and jitter specifications. See the section ExternalCrystal Characteristics (in section Manchester Encoder/Decoder) for more detail.

The network data rate is one-half of the crystal fre-quency. XTAL1 may alternatively be driven using anexternal CMOS level source, in which case XTAL2 mustbe left unconnected. Note that when the PCnet-32 con-troller is in coma mode, there is an internal 22 KΩ resis-tor from XTAL1 to ground. If an external source drivesXTAL1, some power will be consumed driving this resis-tor. If XTAL1 is driven LOW at this time power consump-tion will be minimized. In this case, XTAL1 must remainactive for at least 30 cycles after the assertion of SLEEPand deassertion of HOLD.

Microwire EEPROM Interface

EESKEEPROM Serial Clock OutputThe EESK signal is used to access the external ISO8802-3 (IEEE/ANSI 802.3) address PROM. This pin isdesigned to directly interface to a serial EEPROM thatuses the microwire interface protocol. EESK is con-nected to the microwire EEPROM’s Clock pin. It is con-trolled by either the PCnet-32 controller directly during aread of the entire EEPROM, or indirectly by the hostsystem by writing to BCR19, bit 1.

EESK can be used during programming of externalEEPROM-programmable registers that do not use themicrowire protocol as follows:



44 Am79C965

EEDOEEPROM Data Out InputThe EEDO signal is used to access the external ISO8802-3 (IEEE/ANSI 802.3) address PROM. This pin isdesigned to directly interface to a serial EEPROM thatuses the microwire interface protocol. EEDO is con-nected to the microwire EEPROM’s Data Output pin. Itis controlled by the EEPROM during reads. It may beread by the host system by reading BCR19, bit 0.

EEDO can be used during programming of externalEEPROM-programmable registers that do not use themicrowire protocol as follows:


EECSEEPROM Chip Select OutputThe function of the EECS signal is to indicate to themicrowire EEPROM device that it is being accessed.The EECS signal is active high. It is controlled by eitherthe PCnet-32 controller during a read of the entireEEPROM, or indirectly by the host system by writing toBCR19, bit 2.

EEDIEEPROM Data In OutputThe EEDI signal is used to access the external ISO8802-3 (IEEE/ANSI 802.3) address PROM. EEDI func-tions as an output. This pin is designed to directly inter-face to a serial EEPROM that uses the microwireinterface protocol. EEDI is connected to the microwireEEPROM’s Data Input pin. It is controlled by either thePCnet-32 controller during command portions of a readof the entire EEPROM, or indirectly by the host systemby writing to BCR19, bit 0.


CI±Collision In InputA differential input pair signaling the PCnet-32 controllerthat a collision has been detected on the network media,indicated by the CI± inputs being driven with a 10 MHzpattern of sufficient amplitude and pulse width to meetISO 8802-3 (IEEE/ANSI 802.3) standards. Operates atpseudo ECL levels.

DI±Data In InputA differential input pair to the PCnet-32 controller carry-ing Manchester encoded data from the network. Oper-ates at pseudo ECL levels.

DO±Data Out OutputA differential output pair from the PCnet-32 controller fortransmitting Manchester encoded data to the network.Operates at pseudo ECL levels.


RXD±10-BASE-T Receive Data Input10BASE-T port differential receivers.

TXD±10BASE-T Transmit Data Output10BASE-T port differential drivers.

TXP±10BASE-T Pre-distortion Control OutputThese outputs provide transmit predistortion control inconjunction with the 10BASE-T port differential drivers.

External Address Detection Interface

The EADI interface is enabled through BCR2, bit 3(EADISEL).

EARExternal Address Reject Low InputAn EADI input signal. The incoming frame will bechecked against the internally active address detectionmechanisms and the result of this check will be OR’dwith the value on the EAR pin. The EAR pin is definedas REJECT.

See the EADI section for details regarding the functionand timing of this signal.

Note that this pin is multiplexed with the INTR2 pin.

SFBDStart Frame–Byte Delimiter OutputStart Frame–Byte Delimiter Enable. EADI output signal.An initial rising edge on this signal indicates that a startof frame delimiter has been detected. The serial bitstream will follow on the SRD signal, commencing withthe destination address field. SFBD will go high for 4 bittimes (400 ns) after detecting the second “1” in the SFD(Start of Frame Delimiter) of a received frame. SFBD willsubsequently toggle every 400 ns (1.25 MHz frequency)with each rising edge indicating the first bit of each sub-sequent byte of the received serial bit stream. SFBD willbe inactive during frame transmission.


45Am79C965


SRDSerial Receive Data OutputAn EADI output signal. SRD is the decoded NRZ datafrom the network. This signal can be used for externaladdress detection. Note that when the 10BASE-T port isselected, transitions on SRD will only occur duringreceive activity. When the AUI port is selected, transi-tions on SRD will occur during both transmit and re-ceive activity.

Note that this pin is multiplexed with the LEDPRE3 pin.

SRDCLKSerial Receive Data Clock OutputAn EADI output signal. Serial Receive Data is synchro-nous with reference to SRDCLK. Note that when the10BASE-T port is selected, transitions on SRDCLK willonly occur during receive activity. When the AUI port isselected, transitions on SRDCLK will occur during bothtransmit and receive activity.


General Purpose Serial Interface

The GPSI interface is selected through the PORTSELbits of the Mode register (CSR15) and enabled throughthe TSTSHDW[1] bit (BCR18) or the GPSIEN bit(CSR124).

Note that when GPSI test mode is invoked, slave ad-dress decoding must be restricted to the lower 24 bits ofthe address bus by setting the IOAW24 bit in BCR2 andby pulling LED2 LOW during Software ReloactableMode. The upper 8 bits of the address bus will always beconsidered matched when examining incoming I/O ad-dresses. During master accesses while in GPSI mode,the PCnet-32 controller will not drive the upper 8 bits ofthe address bus with address information. See the GPSIsection for more detail.

TXDATTransmit Data Input/OutputTXDAT is an output, providing the serial bit stream fortransmission, including preamble, SFD data and FCSfield, if applicable.

Note that the TxDAT pin is multiplexed with the A31 pin.

TXENTransmit Enable Input/OutputTXEN is an output, providing an enable signal for trans-mission. Data on the TXDAT pin is not valid unless theTXEN signal is HIGH.

Note that the TXEN pin is multiplexed with the A30 pin.

STDCLKSerial Transmit Data Clock InputSTDCLK is an input, providing a clock signal for MACactivity, both transmit and receive. Rising edges of theSTDCLK can be used to validate TXDAT output data.

The STDCLK pin is multiplexed with the A29 pin.

Note that this signal must meet the frequency stabilityrequirement of the ISO 8802-3 (IEEE/ANSI 802.3)specification for the crystal.

CLSNCollision Input/OutputCLSN is an input, indicating to the core logic that acollision has occurred on the network.

Note that the CLSN pin is multiplexed with the A28 pin.

RXCRSReceive Carrier Sense Input/OutputRXCRS is an input. When this signal is HIGH, it indi-cates to the core logic that the data on the RXDAT inputpin is valid.

Note that the RXCRS pin is multiplexed with the A27 pin.

SRDCLKSerial Receive Data Clock Input/OutputSRDCLK is an input. Rising edges of the SRDCLK sig-nal are used to sample the data on the RXDAT inputwhenever the RXCRS input is HIGH.

Note that the SRDCLK pin is multiplexed with theA26 pin.

RXDATReceive Data Input/OutputRXDAT is an input. Rising edges of the SRDCLK signalare used to sample the data on the RXDAT input when-ever the RXCRS input is HIGH.

Note that the RXDAT pin is multiplexed with the A25 pin.


46 Am79C965

IEEE 1149.1 Test Access Port InterfaceTCKTest Clock InputThe clock input for the boundary scan test mode opera-tion. TCK can operate up to 10 MHz. If left unconnectedthis pin has a default value of HIGH.

TDITest Data Input InputThe test data input path to the PCnet-32 controller. If leftunconnected, this pin has a default value of HIGH.

TDOTest Data Output OutputThe test data output path from the PCnet-32 controller.TDO is floated when the JTAG port is inactive.

TMSTest Mode Select InputA serial input bit stream is used to define the specificboundary scan test to be executed. If left unconnected,this pin has a default value of HIGH.

Power Supply PinsAVDDAnalog Power (4 Pins) PowerThere are four analog +5 V supply pins. Special atten-tion should be paid to the printed circuit board layout toavoid excessive noise on these lines. Refer toAppendix B and the PCnet Family Technical Manual(PID# 18216A) for details.

AVSSAnalog Ground (2 Pins) PowerThere are two analog ground pins. Special attentionshould be paid to the printed circuit board layout to avoidexcessive noise on these lines. Refer to Appendix B andthe PCnet Family Technical Manual for details.

DVDDDigital Power (3 Pins) PowerThere are 3 digital power supply pins. (DVDD1, DVDD2,and DVDD3) used by the internal circuitry.

DVDDCLKDigital Power Clock (1 Pin) PowerThis pin is used to supply power to the clock bufferingcircuitry.

DVDDOI/O Buffer Digital Power (5 Pins) PowerThere are 5 digital power supply pins (DVDD01–DVDD05) used by Input/Output buffer drivers.

DVSSDigital Ground (4 Pins) GroundThere are 4 digital ground pins (DVSS1–DVSS4) usedby the internal digital circuitry.

DVSSCLKDigital Ground Clock (1 Pin) GroundThis pin is used to supply a ground to the clock bufferingcircuitry.

DVSSNI/O Buffer Digital Ground (15 Pins) GroundThese 15 ground pins (DVSSN1–DVSSN15) are usedby the Input/Output buffer drivers.

DVSSPADDigital Ground Pad (1 Pin) GroundThis pin is used by the Input/Output logic circuits.


47Am79C965

BASIC FUNCTIONSSystem Bus Interface FunctionThe PCnet-32 controller is designed to operate as a BusMaster during normal operations. Some slave accessesto the PCnet-32 controller are required in normal opera-tions as well. Initialization of the PCnet-32 controller isachieved through a combination of Bus Slave accesses,Bus Master accesses and an optional read of a serialEEPROM that is performed by the PCnet-32 controller.The EEPROM read operation is performed through themicrowire interface. The ISO 8802-3 (IEEE/ANSI 802.3)Ethernet Address may reside within the serialEEPROM. Some PCnet-32 controller configuration reg-isters may also be programmed by the EEPROM readoperation.

The address PROM, on-chip board-configuration regis-ters, and the Ethernet controller registers occupy 32bytes of I/O space which can be located by modifyingthe I/O base address register. The default base addresscan be written to the EEPROM. The PCnet-32 controllerwill automatically read the I/O Base Address from theEEPROM after H_RESET, or at any time that the soft-ware requests that the EEPROM should be read. Whenno EEPROM is attached to the serial microwire inter-face, the PCnet-32 controller detects the condition, andenters Software Relocatable Mode. While in SoftwareRelocatable Mode, the PCnet-32 controller will not re-spond to any bus accesses, but will snoop the bus foraccesses to I/O address 378h. When a successfullyexecuted and uninterrupted sequence of write opera-tions is seen at this location, the PCnet-32 controller willaccept the next sequence of accesses as carrying I/OBase Address relocation and interrupt pin programminginformation. After this point, the PCnet-32 controllerwill begin to respond directly to accesses directed to-ward offsets from the newly loaded I/O Base Address.This scheme allows for jumperless relocatable I/Oimplementations.

Software InterfaceThe software interface to the PCnet-32 controller is di-vided into two parts. One part is the direct access to theI/O resources of the PCnet-32 controller. The PCnet-32

controller occupies 32 bytes of I/O space that must be-gin on a 32-byte block boundary. The I/O Base Addresscan be changed to any 32-bit quantity that begins on a32-byte block boundary through the function of the Soft-ware Relocatable Mode. It can also be changed to any32-bit value that begins on a 32-byte block boundarythrough the automatic EEPROM read operation that oc-curs immediately after the H_RESET function has com-pleted. This read operation automatically alters the I/OBase Address of the PCnet-32 controller.

The 32-byte I/O space is used by the software to pro-gram the PCnet-32 controller operating mode, to enableand disable various features, to monitor operatingstatus and to request particular functions to be executedby the PCnet-32 controller.

The other portion of the software interface is the descrip-tor and buffer areas that are shared between the soft-ware and the PCnet-32 controller during normal networkoperations. The descriptor area boundaries are set bythe software and do not change during normal networkoperations. There is one descriptor area for receive ac-tivity and there is a separate area for transmit activity.The descriptor space contains relocatable pointers tothe network packet data and it is used to transfer packetstatus from the PCnet-32 controller to the software. Thebuffer areas are locations that hold packet data fortransmission or that accept packet data that hasbeen received.

Network InterfacesThe PCnet-32 controller can be connected to an 802.3network via one of two network interfaces. The Attach-ment Unit Interface (AUI) provides an ISO 8802-3(IEEE/ANSI 802.3) compliant differential interface to aremote MAU or an on-board transceiver. The10BASE-T interface provides a twisted-pair Ethernetport. While in auto-selection mode, the interface in useis determined by an auto-sensing mechanism whichchecks the link status on the 10BASE-T port. If there isno active link status, then the device assumes anAUI connection.

DETAILED FUNCTIONS

Bus Interface UnitThe bus interface unit is built of several state machinesthat run synchronously to BCLK. One bus interface unitstate machine handles accesses where the PCnet-32controller is the bus slave, and another handles ac-cesses where the PCnet-32 controller is the bus master.All inputs are synchronously sampled except ADS,M/IO, D/C, W/R and the A[31:5] bus when this bus is aninput to the PCnet-32 controller. All outputs are synchro-nously generated on the rising edge of BCLK with thefollowing exceptions:

LDEV is generated asynchronously.

RDY is driven/floated on falling edges of BCLK but willchange state on rising edges of BCLK.

The following sections describe the various bus masterand bus slave operations that will be performed by thePCnet-32 controller. The timing diagrams that are in-cluded in these sections (Bus Acquisition sectionthrough Slave Timing section) show the signals and tim-ings of the Am486 32-bit mode of operation. The sec-tions from Bus Acquisition through Linear Burst DMATransfers show bus master operations. The Slave Tim-ing section shows bus slave operations. Note that thePCnet-32 controller operation in Am486 32-bit moderepresents a merger of the requirements of the VESAVL-Bus specification and Am486 bus specification,


48 Am79C965

whichever is more stringent. The concepts discussed inthe following sections and the basic nature of the timingsshown is applicable in a general sense to PCnet-32 con-troller operational modes. For specific differences intiming between modes and for examples of timing dia-grams showing basic transfers in each of the modes,please consult the following sections:

Am486 32-bit mode: Bus Acquisition sectionthrough Slave Timing section

VESA VL-Bus mode: VESA VL-Bus Mode Timingsection

For selection of each mode, consult the section on Con-figuration Pins in the Pin Description section.

Note that all timing diagrams in this document havebeen drawn showing reference to two groups of addresspins: namely, A4–A31 and A2–A3, BE0–BE3. In theAHOLD timing diagrams, the two groups are shownseparately, because the upper address pins becomefloated, while the lower address pins do not. The point ofdivision between the two groups of address pins will de-pend upon the value of CLL in BCR18. In the case of Lin-ear Burst operations, the upper address pins are shownseparately because that group does not change itsvalue through a single linear burst, while the lower ad-dress pins do change value. In this case, the point of di-vision between the two groups of address pins willdepend upon the value of LINBC in BCR18. In all othertiming diagrams, the two groups are shown separatelyjust to maintain consistency with the AHOLD and Linear

Burst timing diagrams. For more details, see theAHOLD and Linear Burst Count sections.

Bus AcquisitionThe PCnet-32 controller microcode (in the buffer man-agement section) will determine when a DMA transfershould be initiated. The first step in any PCnet-32 con-troller bus master transfer is to acquire ownership of thebus. This task is handled by synchronous logic withinthe BIU. Bus ownership is requested with the HOLD sig-nal and ownership is granted by the CPU (or an arbiter)through the HLDA signal. The PCnet-32 controller addi-tionally supplies HOLDI and HLDAO signals to allowdaisy chaining of devices through the PCnet-32 control-ler. Priority of the HOLDI input versus the PCnet-32 con-troller’s own internal request for bus mastership can beset using the PRPCNET bit of BCR17. Simple bus arbi-tration (HOLD, HLDA only) is shown in Figure 1.

Note that assertion of the STOP bit will not cause adeassertion of the HOLD signal. Note also that a read ofthe S_RESET register (I/O resource at offset 14h fromthe PCnet-32 controller base I/O address) will not causea deassertion of the HOLD signal. Either of these ac-tions will cause the internal master state machine logicto cease operations, but the HOLD signal will remain ac-tive until the HLDA signal is synchronously sampled asasserted. Following either of the above actions, on thenext clock cycle after the HLDA signal is synchronouslysampled as asserted, the PCnet-32 controller will deas-sert the HOLD signal. No bus master accesses will havebeen performed during this brief bus ownership period.


49Am79C965

18219B-5

ADS

Tt

BCLK

T1 T2 T2

A4–A31,M/IO, D/C

A2–A3,BE0–BE3

RDYRTN

W/R

BRDY

BLAST

D0–D31

HOLD

HLDA

FromPCnet-32

TiTiTiTi

Figure 1. Bus Acquisition

Assertion of a minimum-width pulse on the RESET pinwill cause the HOLD signal to deassert within six clockcycles following the assertion of the RESET pin. In thiscase, the PCnet-32 controller will not wait for the asser-tion of the HLDA signal before deasserting theHOLD signal.

This description of behavior is identical for the VESAVL-Bus mode of operation, except that the HOLD,HLDA and RESET signals are replaced by the inverted

sense signals LREQ, LGNT, and RESET, respectively;the BCLK, BOFF, EADS, and RDY signals are replacedby LCLK, WBACK, LEADS, and LRDY, respectively.

Bus Master DMA TransfersThere are three primary types of DMA transfers. AllDMA transfers will have wait states inserted until eitherRDYRTN or BRDY is asserted. Figure 2 and Figure 3show the basic bus transfers of read and write withoutready wait states and then with ready wait states.


50 Am79C965

18219B-6

ADS

Ti

BCLK

T1 T2 T1 T2 T1 T2

A4–A31,M/IO, D/C

A2–A3,BE0–BE3

RDYRTN

W/R

BRDY

BLAST

D0–D31

T2 T2 Ti

ToPCnet-32

HOLD

HLDA

ToPCnet-32

ToPCnet-32

Ti Ti

Figure 2. Basic Read Cycles without and with Wait States


51Am79C965

18219B-7

ADS

Ti

BCLK

T1 T2 T1 T2 T1 T2

A4–A31,M/IO, D/C

A2–A3,BE0–BE3

RDYRTN

W/R

BRDY

BLAST

D0–D31

T2 T2 Ti Ti

HOLD

HLDA

FromPCnet-32

FromPCnet-32

FromPCnet-32

Ti Ti

Figure 3. Basic Write Cycles without and with Wait States


52 Am79C965

Effect of BOFFAssertion of BOFF during bus master transfers willcause the PCnet-32 controller to float all of its bus sig-nals beginning at the next clock cycle. Any access whichhas been interrupted by BOFF will be restarted when the

BOFF signal is deasserted. Simultaneous assertion ofRDYRTN (or BRDY) and BOFF is resolved in favor ofBOFF. The RDYRTN (or BRDY) is ignored for such acycle, and when BOFF is deasserted, the cycle isrestarted. See Figure 4 for detail.

ADS

Ti

BCLK

T1 T2 T2 Tb Tb T1b

A4-A31,M/IO,

D/C

A2-A3,BE0-BE3

RDYRTN

W/R

BRDY

BLAST

D0-D31

T2 T2 Ti

ToPCnet-32

BOFF

HOLD

ToPCnet-32

HLDA

100 100

100 100

Ti Ti

18219B-8

Figure 4. Restarted Read Cycle


53Am79C965

Effect of AHOLDAssertion of AHOLD during bus master transfers willcause the PCnet-32 controller to float some portion ofthe address bus beginning at the next clock cycle. IfRDYRTN is returned while AHOLD is active, then thecycle completes, since the data bus may remain activeduring AHOLD. However, a new cycle will not be startedwhile AHOLD is active.

The portion of the Address Bus that will be floated at thetime of an address hold operation will be determined bythe value of the Cache Line Length register (BCR18,bits 15-11). Table 17 lists all of the legal values of CLLshowing the portion of the Address Bus that will becomefloated during an address hold operation.

If the RDYRTN signal is not returned while AHOLD isactive, then the PCnet-32 controller will resume drivingthe same address onto the address bus when AHOLD isreleased. The PCnet-32 controller will not reissue theADS signal at this time. See Figure 5 and Figure 6for details.

Table 17. CLL Value and Floating Address Pins


00000 None

00001 A31–A2

00010 A31–A3


00100 A31–A4


01000 A31–A5


10000 A31–A6


CLL Value

Note: The default value of CLL after H_RESET is00100. All timing diagrams in this document are drawnwith the assumption that this is the value of CLL.

ADS

Ti

BCLK

T1 T2 T2 T2 Ti Ti

A4-A31

A2-A3,BE0-BE3

RDYRTN

W/R

BRDY

BLAST

D0-D31

T1 T2 Ti

ToPCnet-32

AHOLD

HOLD

HLDA

100 104

100 104

ToPCnet-32

M/IO,D/C

Ti Ti

18219B-9

Figure 5. Read Cycle with AHOLDNote that initial access is allowed to complete in spite of AHOLD,

but next access is prevented from beginning until AHOLD is deasserted.


54 Am79C965

ADS

Ti

BCLK

T1 T2 T2 T2 T2 T2

A4-A31

A2-A3,BE0-BE3

RDYRTN

W/R

BRDY

BLAST

D0-D31

T1 T2 Ti

ToPCnet-32

AHOLD

HOLD

HLDA

100 104

100 104

ToPCnet-32

M/IO,D/C

100

Ti Ti

18219B-80

Figure 6. Read Cycle with AHOLDAddress is re-driven when AHOLD is deasserted,

since RDYRTN had not yet arrived.

Effect of Bus PreemptionIf a bus preemption event occurs during a basic transfercycle, then the behavior of the PCnet-32 controller willdepend upon which specific type of access is being per-formed. The general response of the PCnet-32 control-ler is that the current operation will complete before thePCnet-32 controller relinquishes the bus in response tothe preemption. “Current operation” in this sense refersto the general PCnet-32 controller operation, such as

“descriptor access”. Note that a “descriptor access” con-sists of one or two basic transfers. Therefore, both trans-fers of a descriptor access must be completed beforethe bus will be released in response to a preemption.See each of the sections for Initialization Block DMAtransfers, Descriptor DMA transfers, FIFO DMA trans-fers and Linear Burst Transfers for more specificinformation.


55Am79C965

Effect of LBS16 (VL-Bus mode only)Dynamic bus sizing is recognized by the PCnet-32 con-troller while operating in the VL-Bus mode. The LBS16signal is used to indicate to the PCnet-32 controllerwhether the VL-Bus target is a 16-bit or 32-bit periph-eral. When the target device indicates that it is 16 bits inwidth by asserting the LBS16 signal at least one LCLKperiod before asserting the RDYRTN signal, then thePCnet-32 controller will dynamically respond to the sizeconstraints of the peripheral by performing additionalaccesses. Table 18 shows the sequence of accessesthat will be performed by the PCnet-32 controller in re-sponse to the assertion of LBS16.

Figure 7 shows an example of an exchange between a16-bit VL-Bus peripheral and the PCnet-32 controller.Note that the LBS16 signal is asserted during the LCLK

that precedes the assertion of RDYRTN. In this particu-lar case, in order to maintain zero-wait state accesses,the 16-bit target must generate LBS16 in a very shorttime in order to meet the required setup time of LBS16into the PCnet-32 controller. If the peripheral were inca-pable of meeting the required setup time, then a waitstate would be needed in order to insure that LBS16 isasserted at least one LCLK prior to the assertion of theRDYRTN signal.

When the assertion of LBS16 during a PCnet-32 con-troller master access has created the need for a secondaccess as specified in the table above, and the WBACKsignal becomes active during the second access, then,when WBACK is deasserted, the PCnet-32 controllerwill repeat both accesses of the pair.



1 1 1 0 NR*

1 1 0 0 NR*

1 0 0 0 1 0 1 1

0 0 0 0 0 0 1 1

1 1 0 1 NR*

1 0 0 1 1 0 1 1

0 0 0 1 0 0 1 1

1 0 1 1 NR*

0 0 1 1 NR*

0 1 1 1 NR*

Next with LBS16Current Access

*NR = No second access Required for these cases


56 Am79C965

18219B-10

ADS

Ti

LCLK

T1 T2 T1 T2 Ti Ti

ADR4–ADR31

ADR2–ADR3,BE2–BE3

RDYRTN

W/R

BRDY

BLAST

DAT0–DAT31

Ti Ti Ti

ToPCnet-32

LBS16

LREQ

LGNT

100

100

ToPCnet-32

M/IO,D/C

100

BE0–BE1

100

Ti

Figure 7. VL-Bus Ready Cycle with LBS16 AssertedFour-byte single cycle access is

converted to two 2-byte accesses.


57Am79C965

Initialization Block DMA TransfersDuring execution of the PCnet-32 controller bus masterinitialization procedure, the PCnet-32 controllermicrocode will repeatedly request DMA transfers fromthe BIU. During each of these initialization block DMAtransfers, the BIU will perform two data transfer cycles(eight bytes) and then it will relinquish the bus (see Fig-ure 8). The two transfers within the mastership periodwill always be read cycles to ascending contiguous ad-dresses. The two transfers in each initialization blockDMA transfer will never be executed using linear burstmode. In 32-bit software mode, the number of bus mas-tership periods needed to complete the initialization pro-cedure is 4. There are 7 doublewords to transfer during

the bus master initialization procedure, so four bus mas-tership periods are needed in order to complete the in-itialization sequence. Note that the last doublewordtransfer of the last bus mastership period of the initiali-zation sequence accesses an unneeded location. Datafrom this transfer is discarded internally.

If a bus preemption event occurs during an initializationblock DMA transfer, then the PCnet-32 controller willcomplete both of the two data transfer cycles of the in-itialization block DMA transfer before releasing theHOLD signal and relinquishing the bus.

When SSIZE32 = 0 (CSR58[8]/BCR20[8]), then thenumber of bus mastership periods needed to completethe initialization procedure is 3 or 4.

18219B-11

ADS

Ti

BCLK

T1 T2 T1 T2 Ti Ti

A4–A31,M/IO, D/C

A2–A3,BE0–BE3

RDYRTN

W/R

BRDY

BLAST

D0–D31

Ti Ti Ti Ti

ToPCnet-32

ToPCnet-32

IADDi IADDi +4

IADDi IADDi +4

Figure 8. Initialization DMA Transfer


58 Am79C965

Descriptor DMA TransfersPCnet-32 controller will determine when a descriptor ac-cess is required. A descriptor DMA read will consist oftwo doubleword transfers. A descriptor DMA write willconsist of one or two double word transfer. The trans-fers within a descriptor DMA transfer mastership periodwill always be of the same type (either all read or allwrite). The transfers will be to addresses in the order asspecified in Table 19 and Table 20 (note that MD indi-cates TMD or RMD).

If buffer chaining is used (see Transmit and Receive De-scriptor Table Entry sections), writes to the descriptorsthat do not contain the End of Packet bit will consist ofonly one doubleword. This write will be to the same loca-tion as the second of the two writes performed when theEnd of Frame has been processed (i.e. to the locationthat contains the descriptor OWNership bit, MD1[31]).

Descriptor DMA transfers will never be executed usinglinear burst mode. During read accesses, the byte en-able signals will indicate that all byte lanes are active.Should some of the bytes not be needed, then thePCnet-32 controller will internally discard the extrane-ous information that was gathered during such a read.During write accesses, only the bytes which need to bewritten are enabled, by activating the correspondingbyte enable pins. See Figure 9 and Figure 10.

If a bus preemption event occurs during a descriptorDMA transfer, then the PCnet-32 controller will com-plete both of the two data transfer cycles of the descrip-tor DMA transfer, before releasing the HOLD signal andrelinquishing the bus.

The only significant differences between descriptorDMA transfers and initialization DMA transfers are thatthe addresses of the accesses follow different ordering.

Table 19. Bus Master Reads of Descriptors

Address LANCE PCnet-32 Address LANCE PCnet-32Sequence A[7:0] Item Accessed Item Accessed Sequence A[7:0]* Item Accessed Item Accessed

00 MD1[15:0], MD1[31:24], 04 MD1[15:8], MD1[31:0]MD0[15:0] MD0[23:0] MD2[15:0]

04 MD3[15:0], MD2[15:0], 00 MD1[7:0], MD0[31:0]MD2[15:0] MD1[15:0] MD0[15:0]

Bus Break Bus Break

32-Bit Software Mode16-Bit Software Mode

Table 20. Bus Master Writes of Descriptors

Address LANCE PCnet-32 Address LANCE PCnet-32Sequence A[7:0] Item Accessed Item Accessed Sequence A[7:0]* Item Accessed Item Accessed

04 MD3[15:0], MD2[15:0], 08 MD3[15:0], MD2[31:0]MD2[15:0] MD1[15:0] MD2[15:0]

00 MD1[15:0], MD1[31:24], 04 MD1[15:8], MD1[31:0]MD0[15:0] MD0[23:0] MD2[15:0]

Bus Break Bus Break

32-Bit Software Mode16-Bit Software Mode

*Address values for A[31:8] are constant throughout any single descriptor DMA transfer. Note that even though bits A[1:0] do notphysically exist in the system, these bits must be set to ZERO in the descriptor base address.


59Am79C965

18219B-12

ADS

Ti

BCLK

T1 T2 T1 T2 Ti Ti

A4–A31,M/IO, D/C

A2–A3,BE0–BE3

RDYRTN

W/R

BRDY

BLAST

D0–D31

Ti Ti Ti Ti

ToPCnet-32

ToPCnet-32

*Note that Message Descriptor addresses 1 and 0 are in descending order.

MD1* MD0*

MD1* MD0*

Figure 9. Descriptor DMA Read


60 Am79C965

18219B-13

ADS

Ti

BCLK

T1 T2 T1 T2 Ti Ti

A4–A31,M/IO, D/C

A2–A3,BE0–BE3

RDYRTN

W/R

BRDY

BLAST

D0–D31

Ti Ti Ti Ti

FromPCnet-32

FromPCnet-32

MD2*

MD2* MD1*

MD1*

*Note that Message Descriptor addresses 2 and 1 are in descending order.

Figure 10. Descriptor DMA Write

FIFO DMA TransfersPCnet-32 controller microcode will determine when aFIFO DMA transfer is required. This transfer mode willbe used for transfers of data to and from the PCnet-32controller FIFOs. Once the PCnet-32 controller BIU hasbeen granted bus mastership, it will perform a series ofconsecutive transfer cycles before relinquishing thebus. Each transfer will be performed sequentially, withthe issue of an address, and the transfer of the corre-sponding data with appropriate output signals to indi-cate selection of the active data bytes during thetransfer. All transfers within the master cycle will beeither read or write cycles, and all transfers will be tocontiguous, ascending addresses. The number of datatransfer cycles contained within a single bus cycle is ingeneral, dependent on the programming of theDMAPLUS option (CSR4, bit 14). Several other factorswill also affect the length of the bus cycle period. Thepossibilities are as follows:

If DMAPLUS = 0, a maximum of 16 transfers will be per-formed by default. This default value may be changedby writing to the burst register (CSR80). Note that

DMAPLUS = 0 merely sets a maximum value. The mini-mum number of transfers in the bus cycle will be deter-mined by all of the following variables: the settings of theFIFO watermarks, the particular conditions existingwithin the FIFOs, receive and transmit status conditions,the value of the DMA Burst Cycle (CSR80), the value ofthe DMA Bus Activity Timer (CSR82), and the timing ofany occurrence of preemption that takes place duringthe FIFO DMA transfer.

If DMAPLUS = 1, the bus cycle will continue until thetransmit FIFO is filled to its high threshold (read trans-fers) or the receive FIFO is emptied to its low threshold(write transfers), or until the DMA Bus Activity Timervalue (CSR82) has expired. Other variables may alsoaffect the end point of the burst in this mode. Amongthose variables are: the particular conditions existingwithin the FIFOs, receive and transmit status conditions,and bus preemption events.

The FIFO thresholds are programmable (see descrip-tion of CSR80), as are the Burst Cycle and Bus ActivityTimer values. The exact number of transfer cycles in thecase of DMAPLUS = 1 will be dependent on the latency


61Am79C965

of the system bus to the PCnet-32 controller’s master-ship request and the speed of bus operation, but will belimited by the value in the Bus Activity Timer register, theFIFO condition, receive and transmit status, and bypreemption events, if any. Barring a time-out by either ofthese registers, or a bus preemption by another master-ing device, or exceptional receive and transmit events,or an end of packet signal from the FIFO, the FIFO wa-termark settings and the extent of Bus Acknowledge la-tency will be the major factors determining the numberof accesses performed during any given arbitration cy-cle when DMAPLUS = 1.

The READY response of the memory device will alsoaffect the number of transfers when DMAPLUS = 1,since the speed of the accesses will affect the state ofthe FIFO. (During accesses, the FIFO may be filling oremptying on the network end. A slower memory re-

sponse will allow additional data to accumulate inside ofthe FIFO (during write transfers from the receive FIFO).If the accesses are slow enough, a complete doubleword may become available before the end of the arbi-tration cycle and thereby increase the number of trans-fers in that cycle.) The general rule is that the longer thebus grant latency or the slower the bus transfer opera-tions (or clock speed) or the higher the transmit water-mark or the lower the receive watermark or anycombination thereof the longer will be the averageburst length.

If a bus preemption event occurs during a FIFO DMAtransfer, then the PCnet-32 controller will complete thecurrent transfer and it will complete a maximum of fouradditional data transfer cycles before releasing theHOLD signal and relinquishing the bus.

18219B-14

ADS

Ti

BCLK

T1 T2 T1 T2 T1 T2

A4–A31,M/IO, D/C

A2–A3,BE0–BE3

RDYRTN

W/R

BRDY

BLAST

D0–D31

T1 T2 T1 T2 Ti

ToPCnet-32

ToPCnet-32

ToPCnet-32

ToPCnet-32

ToPCnet-32

Figure 11. FIFO DMA Read


62 Am79C965

18219B-15

ADS

Ti

BCLK

T1 T2 T1 T2 T1 T2

A4–A31,M/IO, D/C

A2–A3,BE0–BE3

RDYRTN

W/R

BRDY

BLAST

D0–D31

T1 T2 T1 T2 Ti

FromPCnet-32

FromPCnet-32

FromPCnet-32

FromPCnet-32

FromPCnet-32

Figure 12. FIFO DMA Write

Note that A[1:0] do not exist in a 32-bit system, but bothof these bits do exist in the buffer pointers that arepassed to the PCnet-32 controller in the descriptor.A[1:0] values will be decoded and presented on the busas byte enable (BE0-BE3) values during FIFO DMAtransfers.

Linear Burst DMA TransfersOnce the PCnet-32 controller has been granted busmastership, the PCnet-32 controller may request to per-form linear burst cycles by de-asserting the BLAST sig-nal. If the device being accessed wishes to supportlinear bursting, then it must assert BRDY and de-assertRDYRTN, with the same timing that RDYRTN wouldnormally be provided. Linear bursting is only performedby the PCnet-32 controller if the BREADE and/orBWRITE bits of BCR18 are set. These bits individuallyenable/disable the ability of the PCnet-32 controller toperform linear burst accesses during master read op-erations and master write operations, respectively. OnlyFIFO data transfers will make use of the linearburst mode.

The first transfer in the linear burst will consist of both anaddress and a data cycle, but subsequent transfers willcontain data only, until the LINBC upper limit of transfershave been executed. LINBC is a value from the BCR18register. The linear burst “upper limit” is created by tak-ing the BCR18 LINBC[2:0] value and multiplying by 4.The result is the number of transfers that will be per-formed within a single linear burst sequence.

The entire address bus will still be driven with appropri-ate values during the data cycles. When the LINBCupper limit of data transfers have been performed, anew ADS may be asserted (if there is more data to betransferred), with a new address on the A2–A31 pins.Following the new ADS cycle, the linear bursting of datawill resume. Ownership of the bus will be maintaineduntil other variables cause the PCnet-32 controllerto relinquish the bus. These variables have beendiscussed in the FIFO DMA transfers section above.They will be reviewed again within this section of thedocument.


63Am79C965

Transfers within a linear burst cycle will either be all reador all write cycles, and will always be to contiguous as-cending addresses. Linear Bursting of Read and Writeoperations can be individually enabled or disabledthrough the BREADE and BWRITE bits of BCR18 (bits 6and 5).

Linear Burst DMA transfers should be considered as asuperset of the FIFO DMA transfers. Linear burst DMAtransfers will only be used for data transfers to and fromthe PCnet-32 controller FIFOs and they will only be al-lowed when the burst enable bits of BCR18 have beenset. Linear Read bursting and Linear Write burstinghave individual enable bits in BCR18. Any combinationof linear burst enable bit settings is permissible.

Linear bursting is not allowed in systems that haveBCLK frequencies above 33 MHz. Linear bursting isautomatically disabled in VL-Bus systems that operateabove this frequency by connecting the VLBEN pin toeither ID(3) (for VL-Bus version 1.0 systems) or ID(4)AND ID(3) AND ID(1) AND ID(0) (for VL-Bus version 1.1or 2.0 systems). In Am486-style systems that haveBCLK frequencies above 33 MHz, disabling the linearburst capability is ideally carried out through EEPROMbit programming, since the EEPROM programming canbe setup for a particular machine’s architecture.

All byte lanes are always considered to be active duringall linear burst transfers. The BE3–BE0 signals will re-flect this fact.

Linear Burst DMA Starting Address RestrictionsA PCnet-32 controller linear burst will begin only whenthe address of the current transfer meets the followingcondition:

A[31:0] MOD (LINBC x 16) = 0,

The following table illustrates all possible starting ad-dress values for all legal LINBC values. Note thatA[31:6] are don’t care values for all addresses. Also note

that while A[1:0] do not physically exist within a 32 bitsystem, they are valid bits within the buffer pointer fieldof descriptor word 0. Thus, where A[1:0] are listed, theyrefer to the lowest two bits of the descriptor’s bufferpointer field. These bits will have an affect on determin-ing when a PCnet-32 controller linear burst operationmay legally begin and they will affect the output valuesof the BE3–BE0 pins, therefore they have been includedin Table 21 as A[1:0].

It is not necessary for the software to insure that thebuffer address pointer contained in descriptor word 0matches the address restrictions given in the table. If thebuffer pointer does not meet the conditions set forth inthe table, then the PCnet-32 controller will simply post-pone the start of linear bursting until enough ordinaryFIFO DMA transfers have been performed to bring thecurrent working buffer pointer value to a valid linearburst starting address. This operation is referred to as“aligning” the buffer address to a valid linear burst start-ing address. Once this has been done, the PCnet-32controller will recognize that the address for the currentaccess is a valid linear burst starting address, and it willautomatically begin to perform linear burst accesses atthat time, provided of course that the software has en-abled the linear burst mode.

Note that if the software would provide only valid linearburst starting addresses in the buffer pointer, then thePCnet-32 controller could avoid performing the align-ment operation. It would begin linear burst accesses onthe very first of the buffer transfers thereby allowing aslight gain in bus bandwidth efficiency.

Because of the linear burst starting address restrictionsgiven in the table above, the PCnet-32 controller linearburst mode is completely compatible with theAm486-style burst cycle when the LINBC[2:0] bits havebeen programmed with the value of 001.

Table 21. Linear Burst Addresses

Linear Burst AddressesLBS = Linear Burst Beginning A[5:0] =

LINBC[2:0] Size (No. of Transfers) (A[31:6] = Don’t Care)

0 0 (no linear bursting) Not Applicable

1 4 00, 10, 20, 30

2 8 00, 20

4 16 00

3,5,6,7 Reserved Not Applicable


64 Am79C965

Linear Burst DMA Timing Diagram ExplanatoryNoteNote that in all of the following timing diagrams for linearburst operations, a LINBC[2:0] value of 001 has beenassumed. This translates to a linear burst length of fourtransfers. When the linear burst size is four transfers,then A[31:4] are stable within a single linear burst se-quence, while A[3:2] and BE3-BE0 will change to reflectthe address of the current transfer. Note that for largervalues of LINBC[2:0] which correspond to longer linearburst lengths, the range of address pins that is stableduring each burst sequence is smaller. For example, ifLINBC[2:0] has the value of 010, then the linear burstlength is eight double word transfers or 32 bytes of data.With this value of LINBC, it takes five address bits totrack the changing addresses through the burst. Thismeans that only A[31:5] are stable during each linearburst sequence, while A[4:2] and BE3-BE0 will changeto reflect the address of the current transfer. ForLINBC[2:0] = 100, only A[31:6] are stable during eachlinear burst sequence, while A[5:2] and BE3-BE0 willchange to reflect the address of the current transfer, andso on. Table 22 summarizes this information.

Table 22. Stable Address Lines During Linear Burst

Portion of Address Bus LINBC Value Stable During Linear Burst

000 Linear Bursting Disabled

001 A[31:4]

010 A[31:5]

100 A[31:6]

Values of LINBC not shown in the table are not allowed.See the LINBC section of BCR18 for more details.

Since all of the timing diagrams assume a LINBC[2:0]value of 001, then A[31:4] are shown to be stable withineach linear burst sequence, and A[3:2] and BE3–BE0are shown as changing in order to reflect the address ofthe current transfer.

Linear Burst DMA Address AlignmentLinear bursting may begin during a bus mastership pe-riod which was initially performing only ordinary DMAoperations. (I.e. the value of BLAST is not restricted toZERO for an entire bus mastership period if ZERO wasthe value of BLAST on the first access of a bus master-ship period.) A change from non-linear bursting to linearbursting will normally occur during linear burst DMA ad-dress alignment operations.

If the PCnet-32 controller is programmed for LINEARburst mode (i.e. BREADE and/or BWRITE bits ofBCR18 are set to ONE), and the PCnet-32 controllerrequests the bus, but the starting address of the firsttransaction does not meet the conditions as specified inthe table above, then the PCnet-32 controller will per-form burst-cycle accesses (i.e.. it will provide an ADS foreach transfer) until it arrives at an address that doesmeet the conditions described in the table. At that time,and without releasing the bus, the PCnet-32 controllerwill invoke the linear burst mode. The simple externalmanifestation of this event is that the value of the BLASTsignal will change to deasserted (driven high) on thenext T2 cycle, thereby indicating a willingness of thePCnet-32 controller to perform linear bursting. (Notethat burst-cycle accesses are performed withBLAST = 0.)

Figure 13 shows an example of a linear burst DMA align-ment operation being performed:


65Am79C965

ADS

T2

BCLK

T1 T2 T2 T2 T2 Ti

A4–A31,M/IO, D/C

A2–A3,BE0–BE3

RDYRTN

W/R

BRDY

BLAST

D0–D31

HOLD

HLDA

T1T2T1Ti

ToPCnet-32

ToPCnet-32

ToPCnet-32

ToPCnet-32

ToPCnet-32

ToPCnet-32

Ti Ti

18219B-16Figure 13. FIFO DMA Read Followed by Linear Burst

Read During a Single Bus Mastership Period

Linear Burst DMA BLAST Signal TimingLinear burst cycles are requested by the PCnet-32 con-troller by deasserting the BLAST signal (i.e. BLAST = 1).When BLAST is deasserted by the PCnet-32 controller,the slave device is under no obligation to provide BRDY.Instead, it may provide RDYRTN in response to each ofthe PCnet-32 controller transfers. If RDYRTN is as-serted during accesses in which the PCnet-32 controllerhas deasserted BLAST, then the current transfer revertsto ordinary burst-cycle (see FIFO DMA Transfersection).

When BLAST is asserted, it signals the end of the cur-rent linear burst sequence.

In a cycle in which BLAST is asserted and following theassertion of either RDYRTN and/or BRDY by the slavedevice, the PCnet-32 controller may either relinquishthe bus or it may initiate a new sequence of linear burst

transfers without relinquishing the bus. If the PCnet-32controller continues with a new sequence of linear bursttransfers, the address asserted during the next T1 cyclewill always be the next address in sequence from theprevious T2 cycle. In other words, the PCnet-32 control-ler will never execute cycles within a single bus master-ship period that are not both ascending and contiguous,with the exception of the descriptor DMA accesses de-scribed above.

The decision to continue bus ownership will dependupon several variables, including the state of the receiveor transmit FIFO. All factors related to this decision arediscussed later in this section.

Figure 14 illustrates a typical case of multiple linearburst sequences being performed during a single busmastership period.


66 Am79C965

ADS

T2

BCLK

T1 T2 T2 T2 T2 Ti

A4–A31,M/IO, D/C

A2–A3,BE0–BE3

RDYRTN

W/R

BRDY

BLAST

D0–D31

HOLD

HLDA

T2T2T2T1Ti

ToPCnet-32

ToPCnet-32

ToPCnet-32

ToPCnet-32

ToPCnet-32

ToPCnet-32

ToPCnet-32

ToPCnet-32

Ti

18219B-17Figure 14. Linear Burst Read


67Am79C965

18219B-18

ADS

Ti

BCLK

T1 T2 T2 T2 T2 Ti

A4–A31,M/IO, D/C

A2–A3,BE0–BE3

RDYRTN

W/R

BRDY

BLAST

D0–D31

TiT2

FromPCnet-32

HOLD

HLDA

FromPCnet-32

FromPCnet-32

FromPCnet-32

T2Ti Ti

Figure 15. Linear Burst Write with Wait States Added by the Slave Device on the Third Transfer

Linear Burst DMA Ready Wait StatesThe PCnet-32 controller will insert wait states into linearburst DMA cycles if neither RDYRTN nor BRDY aresampled asserted at the end of each T2 cycle.

Interrupted Linear Burst DMA CyclesThe assertion of RDYRTN in the place of BRDY within alinear burst cycle will cause the linear burst to be“interrupted.”

In that case, the PCnet-32 controller will revert to ordi-nary two-cycle transfers that contain both a T1 and a T2cycle, except that BLAST will remain deasserted toshow that linear bursting is still being requested by thePCnet-32 controller. This situation is defined as an inter-rupted linear burst cycle. If BRDY is sampled asserted(without also sampling RDYRTN asserted during thesame access) during an interrupted linear burst cycle inwhich BLAST is deasserted, then linear bursting will re-sume. (Note that BLAST will become asserted during aninterrupted linear burst cycle during the transfer that

would have been the last transfer of the linear burst se-quence, had the sequence not been interrupted.)

When an interrupted linear burst cycle is resumed, thenthe next assertion of ADS will depend upon the initialstarting point of the linear burst, rather than on the re-sumption point.

For example, if the linear burst length = 4 (LINBC = 1),and BRDY is asserted during the first transfer, butRDYRTN is asserted on the second, then the PCnet-32controller will revert to ordinary DMA transfers on thethird transfer. If the responding device again assertsBRDY on the third access (while RDYRTN is deas-serted), the PCnet-32 controller will resume linear burst-ing from the current address. It will produce 1 more datacycle before asserting the next ADS, i.e. PCnet-32 con-troller will keep track of the initial linear burst end pointand will continue with the original linear burst after theRDYRTN interruption has occurred.


68 Am79C965

Figure 16 illustrates an example of an interrupted linearburst. Note that BLAST is asserted in the fourth transferafter the initial linear burst began, even though the linearburst was interrupted with the assertion of RDYRTN anda new ADS was driven for the third transfer. The externaleffect of the RDYRTN interruption is completely mani-fested in the insertion of the T1 cycle that contains theasserted ADS. The linear burst cycle is not affected inany other way.

Partial Linear BurstCertain factors may cause the PCnet-32 controller tolinearly burst fewer than the LINBC limit during a singlelinear burst sequence. BLAST will be asserted duringthe last data transfer. A linear burst that is terminated byBLAST before the LINBC limit is reached is called a par-tial linear burst.

A partial linear burst is recognizable in that the BLASTsignal is asserted while fewer than the LINBC limit of

transfers has been performed in the current linear burstsequence.

Factors that could generate a partial linear burst include:

No more data available for transfers from the currenttransmit buffer

No more data available for transfer from the receiveFIFO for this packet

No more space available for transfers to the currentreceive buffer

If any of these conditions occurs, then the PCnet-32controller will end the Linear Burst by asserting BLAST.Typically, during the case of a master read operation (fortransmit buffer transfers), the last transfer in the linearburst sequence will be the last transfer executed beforethe PCnet-32 controller releases the bus. This is true ofboth partial and completed linear burst sequences.

18219B-19

ADS

Ti

BCLK

T1 T2 T2 T1 T2 T1

A4-A31,M/IO,

D/C

A2-A3,BE0-BE3

RDYRTN

W/R

BRDY

BLAST

D0-D31

T2 T2T2

FromPCnet-32

HOLD

HLDA

FromPCnet-32

FromPCnet-32

FromPCnet-32

FromPCnet-32

Ti

Figure 16. “Interrupted” Linear Burst Write


69Am79C965

Typically, during the case of a master write operation(for receive buffer transfers) when receive packet datahas ended, the last transfer in the linear burst sequencewill be the last transfer executed before the PCnet-32controller releases the bus. This is true of both partialand completed linear burst sequences.

However, if the next transfer that the PCnet-32 control-ler is scheduled to execute will be to the last availablelocation of a receive or transmit buffer, then thePCnet-32 controller may assert BLAST on the currenttransfer and then use an ordinary cycle to make the lasttransfer to the buffer. This event occurs because of therestrictions placed upon the byte enable signals duringthe linear burst operation. As mentioned in the initial de-scription of linear burst accesses (section Linear BurstDMA Transfers), all byte lanes of the data bus are al-ways enabled during linear burst operations. Note, how-ever, that in the case of the last buffer location, thePCnet-32 controller may own only a portion of the dou-ble word location. In such cases, it is necessary to

discontinue linear burst accesses on the second fromlast buffer location so that an basic transfer with somebyte lanes disabled can be used for the final transfer.

Figure 17 shows a partial linear burst that occurred whileapproaching the transfer of the last bytes of data to areceive buffer. The linear burst begins when 10 bytes ofspace still remain in the receive buffer. (The number ofspaces remaining for the figure as drawn could be any-where from 9 to 12 spaces. The value of 10 spaces hasbeen chosen just for purposes of illustration.) After thefirst linear burst transfer, the PCnet-32 controller seesthat between 6 bytes of space remain, and knowing thatthe second transfer will use another 4 bytes of space,the PCnet-32 controller is able to predict that the thirdtransfer will be the last. Therefore, it asserts BLAST onthe second transfer to terminate the linear burst opera-tion. However, the PCnet-32 controller retains owner-ship of the bus so that it may, immediately thereon,make an basic transfer to the last two spaces inthe buffer.

ADS

Ti

BCLK

T1 T2 T2 T1 Ti Ti

A4-A31,M/IO,

D/C

A2-A3,BE0-BE3

RDYRTN

W/R

BRDY

BLAST

D0-D31

TiT2

FromPCnet-32

HOLD

HLDA

FromPCnet-32

FromPCnet-32

100 104 108

Ti

18219B-20

Figure 17. Typical Partial Linear Burst Write, Followed by a Basic Transfer During the Same Bus Mastership Period


70 Am79C965

Length of Bus Mastership PeriodThe number of data transfer cycles within the total busmastership period is dependent on the programming ofthe DMAPLUS option (CSR4, bit 14). The possibilitiesare as follows:

If DMAPLUS = 0, a maximum of 16 transfers will be per-formed by default. This default value may be changedby writing to the burst register (CSR80). Note thatDMAPLUS = 0 merely sets a maximum value. The mini-mum number of transfers in the burst will be determinedby all of the following variables: the settings of the FIFOwatermarks and the conditions of the FIFOs, the valueof the DMA Burst Cycle (CSR80), the value of the DMABus Activity Timer (CSR82), and any occurrence ofpreemption that takes place during the burst.

If DMAPLUS = 1, linear bursting will continue until thetransmit FIFO is filled to its high threshold or the receiveFIFO is emptied to its low threshold, or until the DMABus Activity Timer value (CSR82) has expired. A buspreemption event is another cause of termination of cy-cles. The FIFO thresholds are programmable (see de-scription of CSR80), as are the Burst Cycle and BusActivity Timer values. The exact number of total transfercycles in the case of DMAPLUS = 1 will be dependent onthe latency of the system bus to the PCnet-32 control-ler’s mastership request and the speed of bus operation,but will be limited by the value in the Bus Activity TimerRegister, the FIFO condition and by preemption occur-rences, if any.

The exact response of the PCnet-32 controller to any ofthe conditions mentioned above can be complicated.For detail of the response to any particular stimulus, seeeach of the sections that describes PCnet-32 control-ler response.

Note that the number of transfer cycles between eachADS assertion will always only be controlled by LINBC,RDYRTN, BOFF, HLDA and FIFO conditions. The num-ber of transfer cycles separating ADS assertions will notbe affected by DMAPLUS or by the values in the Burst

Cycle and Bus Activity Timer Register. However, thesefactors can influence the number of transfers that is per-formed during any given arbitration cycle.

Barring a time-out by the Burst Cycle or the Bus ActivityTimer Register, or a bus preemption by another master-ing device, the FIFO watermark settings and the extentof Bus Acknowledge latency will be the major factors indetermining the number of accesses performed duringany given arbitration cycle. The BRDY response time ofthe memory device will also affect the number of trans-fers, since the speed of the accesses will affect the stateof the FIFO. (During accesses, the FIFO may be filling oremptying on the network end. For example, on a Re-ceive operation, a slower device will allow additionaldata to accumulate inside of the FIFO. If the accessesare slow enough, a complete double word may becomeavailable before the end of the arbitration cycle andthereby increase the number of transfers in that cycle.)The general rule is that the longer the bus grant latencyor the slower the bus transfer operations or the slowerthe clock speed or the higher the transmit watermark orthe lower the receive watermark or any combinationthereof, will produce longer total burst lengths.

If a bus preemption event occurs after the execution ofthe first T2 cycle of the fourth from the last transfer cyclewithin a linear burst DMA sequence, then the PCnet-32controller will complete the current linear burst se-quence and will execute a new linear burst sequencebefore releasing the HOLD signal and relinquishing thebus. If a bus preemption event occurs before or concur-rent with the execution of the first T2 cycle of the fourthfrom the last transfer cycle within a linear burst DMAsequence, then the PCnet-32 controller will completethe current linear burst sequence and then will releasethe HOLD signal and will relinquish the bus. Within thecontext of this explanation, a single transfer cycle refersto the execution of a data transfer, regardless of thenumber of clock cycles taken, i.e. wait states areincluded in this definition of a transfer cycle. SeeFigure 18.


71Am79C965

18219B-21

ADS

BCLK

T1 T2 T2 T2 T2 Ti

A4-A31,M/IO,

D/C

A2-A3,BE0-BE3

RDYRTN

W/R

BRDY

BLAST

D0-D31

Ti Ti Ti T1

HOLD

HLDA

ToPCnet-32

ToPCnet-32

ToPCnet-32

ToPCnet-32

*

Ti TiTi

*Note : HOLD will always go inactive for 2 BCLK cycles before being reasserted.

Figure 18. Linear Burst Read with Preemption During T2


72 Am79C965

18219B-22

ADS

BCLK

T1 T2 T2 T2 T2 T1

A4-A31,M/IO,

D/C

A2-A3,BE0-BE3

RDYRTN

W/R

BRDY

BLAST

D0-D31

T2 T2 T2 T2 Ti

HOLD

HLDA

ToPCnet-32

ToPCnet-32

ToPCnet-32

ToPCnet-32

ToPCnet-32

ToPCnet-32

ToPCnet-32

ToPCnet-32

TiT1

Figure 19. Linear Burst Read with Preemption During One of the Last Three T2 Cycles of the Sequence

If a bus preemption event occurs on a T1 cycle (specifi-cally, a T1 cycle in which the ADS signal for a new linearburst sequence is asserted), then the next linear burstsequence will be executed before the PCnet-32 control-ler releases the HOLD signal and relinquishes the bus.

(If the T1 cycle in which the preemption occurred was tobegin an basic transfer, then the basic transfer plus asmany as two additional basic transfers will be executedbefore relinquishing the bus.)


73Am79C965

* Note: HOLD is always held inactive for 2 BCLK cycles before being reasserted.

ADS

T2

BCLK

T1 T2 T2 T2 T2 Ti

A4–A31,M/IO, D/C

A2–A3,BE0–BE3

RDYRTN

W/R

BRDY

BLAST

D0–D31

Ti Ti

HOLD

HLDA

T2T2T2

ToPCnet-32

ToPCnet-32

ToPCnet-32

ToPCnet-32

ToPCnet-32

ToPCnet-32

ToPCnet-32

ToPCnet-32

*

Ti

18219B-23

Figure 20. Linear Burst Read with Preemption thatOccurs During the T1 Cycle


75Am79C965

ADS

BCLK

T2 T2 T2 Tb Tb

A4–A31,M/IO, D/C

A2–A3,BE0–BE3

RDYRTN

W/R

BRDY

BLAST

D0–D31

T1b T2 T1 T2 T1

HOLD

HLDA

BOFF

104 108100 108 10C 110

ToPCnet-32

ToPCnet-32

ToPCnet-32

T2 T2

114

ToPCnet-32

ToPCnet-32

18219B-25

Figure 22. Restarted Linear Burst Read in which BOFF was Asserted After BRDY of First Transferin Linear Burst Sequency. Hence, Linear Burst Reverts to Ordinary Cycles Until Next

Legal Linear Burst Starting Address is Reached

In general, if the linear burst is suspended by anotherbus master (either because of BOFF or PCnet-32 con-troller releasing HOLD) then any partially completed lin-ear burst access will not resume when the PCnet-32controller regains bus ownership. But if the PCnet-32controller linear burst is interrupted by the receipt of

RDYRTN in place of BRDY, then the PCnet-32 control-ler will resume the linear burst operation as indicated bythe BLAST signal.

Register accesses cannot be performed to thePCnet-32 device while BOFF is asserted.


76 Am79C965

Effect of AHOLDAssertion of AHOLD during Linear Burst transfers willcause the PCnet-32 controller to float some portion ofthe address bus beginning at the next clock cycle. IfBRDY is returned while AHOLD is active, then the linearburst sequence will continue until the current burstwould otherwise normally terminate, since the data busand the lower portion of the address bus may remainactive during AHOLD. However, a new linear burst se-quence, requiring a new ADS assertion, will not bestarted while AHOLD is active.

When AHOLD is asserted during T1 of a linear burst,then the linear burst operation will be suspended untilAHOLD is deasserted. Once AHOLD is deasserted,then the PCnet-32 controller will start the suspendedlinear burst with the intended address. See Figure 23.(Note that the intended T1 of the linear burst sequencehas been labeled Ta in the figure, since a T1 was neverexecuted due to the suspension of the address bus re-quired by the assertion of AHOLD.)

When AHOLD is asserted in the middle of a linear burst,the linear burst may proceed without stalling or halting.AHOLD requires that PCnet-32 controller float a portionof its address bus, but linear burst data cycles will stillproceed, since the AHOLD signal only affects a portionof the address bus, and that portion of the address bus isnot being used for the middle accesses of a linear burst.

However, if AHOLD is asserted in the middle of a linearburst operation, and the AHOLD signal is held longenough that a new linear burst sequence will start (anew ADS is to be issued by the PCnet-32 controller)then at the end of the current linear sequence, thePCnet-32 controller must wait for the AHOLD signal tobecome inactive before beginning the next linear se-quence, since the AHOLD signal would now interferewith the PCnet-32 controller’s wish to assert ADS and anew address on the entire address bus. During the timethat the PCnet-32 controller is waiting for the release of

the AHOLD signal, the PCnet-32 controller will continueto drive the command signals, but ADS will be driveninactive.

Note that if RDYRTN is asserted during a linear burst se-quence while AHOLD is active, then no more access willbe performed until AHOLD is deasserted. This is be-cause the assertion of RDYRTN will cause thePCnet-32 controller to insert a new T1 cycle into the lin-ear burst. A T1 cycle requires assertion of ADS, but ADSassertion is not allowed as long as AHOLD is still as-serted. Therefore, the T1 cycle is delayed until theAHOLD is deasserted.

The portion of the Address Bus that will be floated at thetime of an address hold operation will be determined bythe value of the Cache Line Length register (BCR18,bits 15–11). Table 23 lists all of the legal values of CLLshowing the portion of the Address Bus that will becomefloated during an address hold operation.

Table 23. CLL Value of Floated Address in AHOLD


00000 None

00001 A31–A2

00010 A31–A3


00100 A31–A4


01000 A31–A5


10000 A31–A6


CLL Value

Note that the default value of CLL after H_RESET is00100. All timing diagrams in this document are drawnwith the assumption that this is the value of CLL.


78 Am79C965

ADS

Ti

BCLK

T1 T2 T2 T2 T2 Th

A4-A31

A2-A3,BE0-BE3

RDYRTN

W/R

BRDY

BLAST

D0-D31

Th T1 T2 T2

AHOLD

HOLD

HLDA

100 110

100

M/IO,D/C

ToPCnet-32

ToPCnet-32

ToPCnet-32

ToPCnet-32

ToPCnet-32

104 108 10C 114110

Ti

18219B-27

Figure 24. Linear Burst Read Cycle with AHOLDNote that Linear Burst sequence is allowed to complete in spite of AHOLD,

but next linear Burst sequence is prevented from beginning until AHOLD is deasserted.

Note that if the BRDY (or RDYRTN) signal is not re-turned while AHOLD is active, then the PCnet-32 con-troller will resume driving the same address onto theaddress bus when AHOLD is released. The PCnet-32controller will not reissue the ADS signal at this time.

Bus Activity Timer Register Time Out During Linear BurstWhen the Bus Activity Timer Register (CSR82 bits[15:0]) times out before or concurrent with the executionof the first T2 cycle of the fourth from the last transfercycle within a linear burst DMA sequence, then the lin-

ear burst will continue until a legal starting address isreached, and then the PCnet-32 controller will relinquishthe bus. If the Bus Activity Timer Register times out afterthe execution of the first T2 cycle of the fourth from thelast transfer cycle within a linear burst DMA sequence,then the PCnet-32 controller will complete the currentlinear burst sequence and will execute a new linearburst sequence before releasing the HOLD signal andrelinquishing the bus. (Effectively, the Bus Activity Timertime-out is treated in a manner identical to the occur-rence of a preemption event.) Therefore, when pro-


79Am79C965

grammed for Linear Burst mode, the PCnet-32controller bus mastership time may exceed the Bus Ac-tivity Timer limit.

This is done because an immediate abort of the linearburst due to timer expiration would leave the currentbuffer pointer at an unaligned location. This wouldcause an address alignment of several ordinary cyclesto be executed during the next FIFO DMA operation.Repeated occurrences of this nature would compromisethe usefulness of the linear burst mode, since this wouldincrease the number of non-linear burst cycles that areperformed. This in turn would increase the busbandwidth requirement of the PCnet-32 controller.Therefore, because the PCnet-32 controller LinearBurst operation does not strictly obey the Burst Timer,the user should program the Burst Timer value in such amanner as to include the expected linear burst releasetime. If the user has enabled the Linear Burst function,and wishes the PCnet-32 controller to limit bus activity toMAX_TIME µs, then the Burst Timer should be pro-grammed to a value of:

MAX_TIME- [((3+lbs) x w + 10 + lbs) x (BCLK period)]

This is because the PCnet-32 controller may use asmuch as one “linear burst size” plus three transfers inorder to complete the linear burst before releasing thebus.

As an example, if the linear burst size is 4 transfers, andthe number of wait states for the system memory is 2,and the BCLK period is 30 ns and the MAX time allowedon the bus is 3 µs, then the Burst Timer should be pro-grammed for:

MAX_TIME- [((3+lbs) x w + 10 + lbs) x (BCLK period)];

3 µs – [(3 + 4) x 2 +10 + 4) x (30 ns)] = 3 µs – (28 x 30 ns) = 3 – 0.84 µs = 2.16 µs.

Then, if the PCnet-32 controller’s Burst Timer times outafter 2.16 µs when the PCnet-32 controller has com-pleted all but the last three transfers of a linear burst,then the PCnet-32 controller may take as much as0.84 µs to complete the bursts and release the bus. Thebus release will occur at 2.16 + 0.84 = 3 µs.

Burst Cycle Time Out During Linear BurstWhen the Burst Cycle (CSR80 bits [7:0]) times out in themiddle of a linear burst, the linear burst will continue untila legal starting address is reached, and then thePCnet-32 controller will relinquish the bus.

The discussion for the Burst Cycle is identical to the dis-cussion for the Bus Activity Timer Register, except thatthe quantities are in terms of transfers instead of interms of time.

The equation for the proper burst register setting is:

Burst count setting = (desired_max DIV (length of lin-ear burst in transfers)) x length of linear burst intransfers,

where DIV is the operation that yields the INTEGERportion of the ÷ operation.

Illegal Combinations of Watermark and LINBCCertain combinations of watermark programming andLINBC programming may create situations whereno linear bursting is possible, or where the FIFO may beexcessively read or excessively written. Such combina-tions are declared as illegal.

Combinations of watermark settings and LINBC set-tings must obey the following relationship:

watermark (in bytes) ≥ LINBC (in bytes)

Combinations of watermark and LINBC settings thatviolate this rule may cause unexpected behavior.

Slave TimingSlave timing in the PCnet-32 controller is designed toperform to both Am486 32-bit timing requirements andVESA VL-Bus timing requirements at the same time.Since the VESA VL-Bus is based upon Am486 bus tim-ing, there is really little difference evident, except forhold-off requirements on the part of the slave driving theRDY, BRDY, and data signals when the high speedwrite signal is false. VESA VL-Bus requires that none ofthese signals are driven by the slave until the second T2cycle when the high speed write signal is false. Since thePCnet-32 controller does not examine the high-speedwrite bit, it assumes that this signal is never true, andtherefore always obeys the more stringent requirementof not being allowed to drive RDY, BRDY and the databus until the second T2. In addition, the PCnet-32 con-troller will drive RDY and BRDY inactive for one halfBCLK cycle at the end of the slave access, immediatelyfollowing the BCLK cycle in which the PCnet-32 control-ler asserted RDY. Again, this behavior is required by theVESA VL-Bus specification, but it is not required for op-eration within an Am486 system. The PCnet-32 control-ler performs in this manner, regardless of the PCnet-32controller mode setting.

Slave timing can generally be inferred from the bus mas-ter timing diagrams, with the exception of the followinginformation:

PCnet-32 controller never responds with BRDY activeduring slave accesses. All PCnet-32 controller slave re-sponses use only the RDY signal. BRDY will always bedeasserted during all PCnet-32 controller slave ac-cesses. RDY is a PCnet-32 controller output signal. It isused during PCnet-32 controller slave accesses.RDYRTN is a PCnet-32 controller input signal. It is usedduring all PCnet-32 controller bus master accesses, aswell as during PCnet-32 controller slave read accesses.

The typical number of wait states added to a slave ac-cess on the part of the PCnet-32 controller is 6 or 7BCLK cycles, depending upon the relative phases of theinternal Buffer Management Unit clock and the BCLK


80 Am79C965

signal, since the internal Buffer Management Unit clockis a divide-by-two version of the BCLK signal.

The PCnet-32 controller RDY and RDYRTN signalsmay be wired together. This allows the PCnet-32controller to operate within a system that has a singleREADY signal.

The LDEV signal is generated in response to a validPCnet-32 controller I/O address on the bus togetherwith a valid ADS signal. LDEV is generated in an asyn-chronous manner by the PCnet-32 controller. See theparameter listings for delay values of the LDEV signal.

RDY, BRDY and D[31:0] are never driven until the sec-ond T2 state of a slave access. Before that time, it isexpected that a system pull-up device is holding theRDY and BRDY signals in a deasserted state.

The RDY and BRDY signals are always driven high forone half BCLK cycle immediately following the BCLKperiod during which RDY was driven asserted. Then theRDY and BRDY signals are floated. This behavior isperformed regardless of the PCnet-32 controller modesetting. See Figure 25.

18219B-28

ADS

Ti

BCLK

T1 T2 T2 T2 T2 T2

ADDRESS,BE0-BE3,

M/IO,D/C

RDY

W/R

BRDY

D0-D31

T2 T2 T2x Ti

FromPCnet-32

LDEV

Valid Not Valid

Not Valid

RDYRTN

Figure 25. Slave RDY Timing

VESA VL-Bus Mode TimingVESA VL-Bus mode functional timing is essentiallyidentical to the timing of the Am486 32-bit mode, exceptthat the bus request and bus acknowledge signals haveinverted senses from those shown in the previous timingdiagrams and the AHOLD signal does not exist while thePCnet-32 controller is programmed for VL-Bus mode. Inaddition, dynamic bus sizing is supported in VESA VL-Bus mode, through the use of the LBS16 signal. Thefollowing section describes possible LBS16 interactionswhile programmed for the VESA VL-Bus mode of

operation. Other differences exist between VL-Busmode and Am486 mode, but these other differences arenot directly related to the master or slave cycle timings.

Effect of LBS16 (VL-Bus mode only)Dynamic bus sizing is recognized by the PCnet-32 con-troller while operating in the VL-Bus mode. The LBS16signal is used to indicate to the PCnet-32 controllerwhether the VL-Bus target is a 16-bit or 32-bit periph-eral. When the target device indicates that it is 16 bits inwidth by asserting the LBS16 signal at least one LCLK


81Am79C965

period before asserting the BRDY signal, then thePCnet-32 controller will dynamically respond to the sizeconstraints of the peripheral by performing additional

accesses. Table 24 indicates the sequence of accessesthat will be performed by the PCnet-32 controller in re-sponse to the assertion of LBS16.


Current Access Next with LBS16


1 1 1 0 NR*

1 1 0 0 NR*

1 0 0 0 1 0 1 1

0 0 0 0 0 0 1 1

1 1 0 1 NR*

1 0 0 1 1 0 1 1

0 0 0 1 0 0 1 1

1 0 1 1 NR*

0 0 1 1 NR*

0 1 1 1 NR*

*NR = No second access Required for these cases


82 Am79C965

Figure 26 shows an example of an exchange between a16-bit VL-Bus peripheral and the PCnet-32 controllerduring ordinary read cycles while programmed for VL-Bus mode of operation. Note that the LBS16 signal isasserted during the LCLK that precedes the assertion ofRDYRTN. In this particular case, in order to maintainzero-wait state accesses, the 16-bit target must gener-ate LBS16 in a very short time in order to meet the re-quired setup time of LBS16 into the PCnet-32 controller.If the peripheral were incapable of meeting the requiredsetup time, then a wait state would be needed in order to

insure that LBS16 is asserted at least one LCLK prior tothe assertion of the RDYRTN signal. This situation isillustrated in the second double word access of the dia-gram. The wait state only needs to be inserted on thefirst access of the sequence, since from that point on,LBS16 could be held active low until the entire doubleword transfer had completed, thus adequately satisfyingthe LBS16 setup requirement for the second RDYRTNassertion. Note that only two bytes of data are trans-ferred during each T2 cycle so that the total number ofbytes transferred during each access is four.

ADS

T2

LCLK

T2 T2 Ti Ti

ADR4–ADR31,M/IO, D/C

ADR2–ADR3,BE2–BE3

RDYRTN

W/R

BRDY

BLAST

DAT0–DAT31

LREQ

LGNT

T1T2T2T1Ti

ToPCnet-32

ToPCnet-32

ToPCnet-32

BE0–BE1

LBS16

100

ToPCnet-32

100 104

Ti

104

104

18219B-29Figure 26. VL-Bus Basic Read with LBS16


83Am79C965

Figure 27 shows an example of an exchange between a16-bit VL-Bus peripheral and the PCnet-32 controllerduring linear burst mode while programmed for VL-Busmode of operation. Note that the LBS16 signal is as-serted during the LCLK that precedes the assertion ofBRDY. In this particular case, in order to maintain zero-wait state accesses, the 16-bit target must generateLBS16 in a very short time in order to meet the requiredsetup time of LBS16 into the PCnet-32 controller. If theperipheral were incapable of meeting the required setuptime, then a wait state would be needed in order to in-sure that LBS16 is asserted at least one LCLK prior tothe assertion of the BRDY signal. For linear burst se-quences, this wait state would only need to be inserted

on the first access of the sequence, since from that pointon, LBS16 could be held active low until the entire se-quence had completed, thus adequately satisfying theLBS16 setup requirement for each subsequent BRDYassertion. Note that only 2 bytes of data are transferredduring each T2 cycle so that the total number of bytestransferred during the linear burst sequence is 16, eventhough 8 T2 cycles are executed.

When the assertion of LBS16 during a PCnet-32 con-troller master access has created the need for a secondaccess as specified in the table above, and the WBACKsignal becomes active during the second access, thenwhen WBACK is deasserted, the PCnet-32 controllerwill repeat both accesses of the pair.

18219B-30

ADS

T2

LCLK

T2 T2 T2 T2 Ti

ADR4-ADR31,

M/IO,D/C

ADR2-ADR3,

BE2-BE3

RDYRTN

W/R

BRDY

BLAST

DAT0-DAT31

LREQ

LGNT

T2T2T2T1Ti

ToPCnet-32

ToPCnet-32

ToPCnet-32

ToPCnet-32

ToPCnet-32

ToPCnet-32

ToPCnet-32

BE0-BE1

LBS16

100

ToPCnet-32

100

100

104 108 10C

Ti Ti

Figure 27. VL-Bus Linear Burst Read with LBS16


84 Am79C965

Bus Master and Bus Slave Data Byte PlacementThe general rule of data placement is that the activedata byte lanes are indicated by the byte enable signalsfor all transfers. Note that during all master read opera-tions, the PCnet-32 controller will always activate allbyte enables, even though some byte lanes may notcontain “valid” data as indicated by a buffer pointervalue. In such instances, the PCnet-32 controller will in-ternally discard unneeded bytes.

Note that in all 32-bit environments, regardless of themode settings, the placement of data bytes on the databus during all PCnet-32 controller bus operations (mas-ter and slave) will proceed in accordance with the databyte duplication rules of the Am386DX. The Am386DXrequirement is for duplication of active data bytes in cor-responding lower-half byte lanes when the access is abyte or word access that utilizes the upper half of thedata bus. PCnet-32 controller performs data byte dupli-cation in this manner. The Am386DX does not indicatebyte duplication when the active data bytes of a byte orword access are exclusively contained in the lower halfof the data bus, therefore, the PCnet-32 controller willnot perform data byte duplication in this case. Byte

duplication for bus master writes and bus slave readswill follow Table 25.

A[1:0] in the table refer to software pointers, since A[1:0]pins do not physically exist in the system. (Softwarepointers include I/O address software pointers in thedriver code for I/O accesses to the PCnet-32 controller,or software pointers for the initialization block, descrip-tor areas or buffer areas that are used by the PCnet-32controller during master accesses.)

For master read operations, the PCnet-32 controller ex-pects data according to the byte enable signaling only.Byte lanes with inactive byte enables are expected tocarry invalid data.

For slave write operations, the PCnet-32 controller ex-pects data according to the byte enable signaling only.Byte lanes with inactive byte enables are expected tocarry invalid data.

For master write operations, the PCnet-32 controller willproduce data as indicated in Table 25.

For slave read operations, the PCnet-32 controller willproduce data as indicated for the BSWP = 0 cases inTable 25, regardless of the actual setting of the BSWPbit.


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Table 25. Master and Slave Byte Placement

Case No. A[1:0] BSWP BE3–BE0 D[31:24] D[23:16] D[15:8] D[7:0]

1a 00 0 0000 Byte3 Byte2 Byte1 Byte0

1b 00 1 0000 Byte0 Byte1 Byte2 Byte3

2a 01 0 0001 Byte2 Byte1 Byte0 Undef

2b 01 1 1000 Undef Byte0 Byte1 Byte2

3a 10 0 0011 Byte1 Byte0 Copy1 Copy0

3b 10 1 1100 Undef Undef Byte0 Byte1

4a 11 0 0111 Byte0 Undef Copy0 Undef

4b 11 1 1110 Undef Undef Undef Byte0

5a 00 0 1000 Undef Byte2 Byte1 Byte0

5b 00 1 0001 Byte0 Byte1 Byte2 Undef

6a 01 0 0001 Byte2 Byte1 Byte0 Undef

6b 01 1 1000 Undef Byte0 Byte1 Byte2





9a 00 0 1100 Undef Undef Byte1 Byte0

9b 00 1 0011 Byte0 Byte1 Copy0 Copy1

10a 01 0 1001 Undef Byte1 Byte0 Undef

10b 01 1 1001 Undef Byte0 Byte1 Undef





13a 00 0 1110 Undef Undef Undef Byte0

13b 00 1 0111 Byte0 Undef Copy0 Undef

14a 01 0 1101 Undef Undef Byte0 Undef

14b 01 1 1011 Undef Byte0 Undef Copy0

15a 10 0 1011 Undef Byte0 Undef Copy0

15b 10 1 1101 Undef Undef Byte0 Undef



Note that cases 10, 12, and 15 will not normally be pro-duced during PCnet-32 controller bus master opera-tions. These cases will only occur during bus masteroperations if the software programs an extremely short

buffer size into the descriptor BCNT field, where ex-tremely short means exactly 4, 3, 2 or 1 bytes in length.

BSWP = 0 corresponds to little Endian byte ordering.BSWP = 1 corresponds to big Endian byte ordering.


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Buffer Management UnitThe buffer management unit is a micro-coded statemachine which implements the initialization procedureand manages the descriptors and buffers. The buffermanagement unit operates at a speed of BCLK ÷2.

InitializationPCnet-32 controller initialization includes the reading ofthe initialization block in memory to obtain the operatingparameters. The initialization block must be located on adouble word (4-byte) address boundary, regardless ofthe setting of the SSIZE32, (CSR58[8]/BCR20[8]) bit.The initialization block is read when the INIT bit in CSR0is set. The INIT bit should be set before or concurrentwith the STRT bit to insure correct operation. Twodoublewords are read during each period of bus master-ship. When SSIZE32 = 1 (CSR58[8]/ BCR20[8]) , thisresults in a total of 4 arbitration cycles (3 arbitration cy-cles if SSIZE32 = 0). Once the initialization block hasbeen completely read in and internal registers havebeen updated, IDON will be set in CSR0, and an inter-rupt generated (if IENA is set). At this point, the BMUknows where the receive and transmit descriptor ringsand hence, normal network operations will begin.

The Initialization Block is vectored by the contents ofCSR1 (least significant 16 bits of address) and CSR2(most significant 16 bits of address). The block containsthe user defined conditions for PCnet-32 controller op-eration, together with the base addresses and lengthinformation of the transmit and receive descriptor rings.

There is an alternative method to initialize the PCnet-32controller. Instead of initialization via the initializationblock in memory, data can be written directly into theappropriate registers. Either method may be used at thediscretion of the programmer. If the registers are writtento directly, the INIT bit must not be set, or the initializa-tion block will be read in, thus overwriting the previouslywritten information. Please refer to Appendix C for de-tails on this alternative method.

Re-InitializationThe transmitter and receiver sections of the PCnet-32controller can be turned on via the initialization block(MODE Register DTX, DRX bits; CSR15[1:0]). Thestates of the transmitter and receiver are monitored bythe host through CSR0 (RXON, TXON bits). ThePCnet-32 controller should be reinitialized if the trans-mitter and/or the receiver were not turned on during theoriginal initialization, and it was subsequently requiredto activate them or if either section was shut off due tothe detection of an error condition (MER, UFLO, TXBUFF error).

Re-initialization may be done via the initialization blockor by setting the STOP bit in CSR0, followed by writingto CSR15, and then setting the START bit in CSR0.Note that this form of restart will not perform the same inthe PCnet-32 controller as in the LANCE. In particular,upon restart, the PCnet-32 controller reloads thetransmit and receive descriptor pointers with their

respective base addresses. This means that the soft-ware must clear the descriptor own bits and reset itsdescriptor ring pointers before the restart of thePCnet-32 controller. The reload of descriptor base ad-dresses is performed in the LANCE only after initializa-tion, so a restart of the LANCE without initializationleaves the LANCE pointing at the same descriptor loca-tions as before the restart.

Buffer ManagementBuffer management is accomplished through messagedescriptor entries organized as ring structures in mem-ory. There are two rings, a receive ring and a transmitring. The size of a message descriptor entry is 4doublewords, or 16 bytes, when SSIZE32 = 1. The sizeof a message descriptor entry is 4 words, or 8 bytes,when SSIZE32 = 0 (CSR58[8]/BCR20[8]).

Descriptor RingsEach descriptor ring must be organized in a contiguousarea of memory. At initialization time (setting the INIT bitin CSR0), the PCnet-32 controller reads the user-de-fined base address for the transmit and receive descrip-tor rings, as well as the number of entries contained inthe descriptor rings. Descriptor ring base addressesmust be on a 16-byte boundary when SSIZE32 = 1, or onan 8-byte boundary when SSIZE32 = 0. A maximum of128 (or 512, depending upon the value of SSIZE32) ringentries is allowed when the ring length is set through theTLEN and RLEN fields of the initialization block. How-ever, the ring lengths can be set beyond this range (up to65535) by writing the transmit and receive ring lengthregisters (CSR76, CSR78) directly.

Each ring entry contains the following information:

1. The address of the actual message data buffer inuser or host memory

2. The length of the message buffer

3. Status information indicating the condition of thebuffer

To permit the queuing and de-queuing of message buff-ers, ownership of each buffer is allocated to either thePCnet-32 controller or the host. The OWN bit within thedescriptor status information, either TMD or RMD (seesection on TMD or RMD), is used for this purpose.OWN = “1” signifies that the PCnet-32 controller cur-rently has ownership of this ring descriptor and its asso-ciated buffer. Only the owner is permitted to relinquishownership or to write to any field in the descriptor entry.A device that is not the current owner of a descriptorentry cannot assume ownership or change any field inthe entry. A device may, however, read from a descrip-tor that it does not currently own. Software should al-ways read descriptor entries in sequential order. Whensoftware finds that the current descriptor is owned by thePCnet-32 controller, then the software must not read“ahead” to the next descriptor. The software should waitat the unOWNed descriptor until ownership has beengranted to the software (when SPRINTEN = 1 (CSR3,


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bit5), then this rule is modified. See the SPRINTEN de-scription). Strict adherence to these rules insures that“Deadly Embrace” conditions are avoided.

Descriptor Ring Access Mechanism At initialization, the PCnet-32 controller reads the baseaddress of both the transmit and receive descriptor ringsinto CSRs for use by the PCnet-32 controller during sub-sequent operations.

As the final step in the self-initialization process, thebase address of each ring is loaded into each of the

current descriptor address registers and the address ofthe next descriptor entry in the transmit and receiverings is computed and loaded into each of the next de-scriptor address registers.

When SSIZE32 = 0, software data structures are 16 bitswide. Figure 28 illustrates the relationship between theInitialization Base Address, the Initialization Block, theReceive and Transmit Descriptor Ring Base Addresses,the Receive and Transmit Descriptors and the Receiveand Transmit Data Buffers, for the case of SSIZE32 = 0.

18219B-35

InitializationBlock

24-Bit Base Address Pointer to

Initialization Block

IADR[15:0]IADR[23:16]RES

CSR1CSR2

TDRA[15:0]

MODEPADR[15:0]

PADR[31:16]PADR[47:32]

LADRF[15:0]LADRF[31:16]

LADRF[47:32]LADRF[63:48]

RDRA[15:0]

RLEN RES RDRA[23:16]

TLEN RES TDRA[23:16]

RcvBuffers

•••

RMD0RMD1 RMD2 RMD3

Rcv DescriptorRing

N N NN

••

•

1st Desc.Start

2nd Desc.Start

RMD0

XmtBuffers

•••

RX DESCRIPTOR RINGS

TMD0TMD1 TMD2 TMD3

RX DESCRIPTOR RINGS

Xmt DescriptorRing

M M MM

••

•

1st Desc.Start

2nd Desc.Start

TMD0

DataBuffer

N

DataBuffer

1

DataBuffer

2

DataBuffer

M

DataBuffer

1

DataBuffer

2

Figure 28. 16-Bit Initialization Block and Descriptor Rings


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When SSIZE32 = 1, software data structures are 32 bitswide. Figure 29 illustrates the relationship between theInitialization Base Address, the Initialization Block, theReceive and Transmit Descriptor Ring Base Addresses(TDRA/RDRA), the Receive and Transmit Descriptorsand the Receive and Transmit Data Buffers, for the caseof SSIZE32 = 1.

PollingIf there is no network channel activity and there is nopre- or post-receive or pre- or post-transmit activity be-ing performed by the PCnet-32 controller, then thePCnet-32 controller will periodically poll the current re-ceive and transmit descriptor entries in order to ascer-tain their ownership. If the DPOLL bit in CSR4 is set,then transmit polling function is disabled.

A typical polling operation consists of the following: ThePCnet-32 controller will use the current receive descrip-tor address stored internally to vector to the appropriateReceive Descriptor Table Entry (RDTE). It will then usethe current transmit descriptor address (stored inter-nally) to vector to the appropriate Transmit DescriptorTable Entry (TDTE). The accesses will be made in thefollowing order: RMD1, then RMD0 of the current RDTEduring one bus arbitration, and after that, TMD1, thenTMD0 of the current TDTE during a second bus arbitra-tion. All information collected during polling activity willbe stored internally in the appropriate CSRs (i.e.CSR18, CSR19, CSR20, CSR21, CSR40, CSR42,CSR50, CSR52). UnOWNed descriptor status will beinternally ignored.

18219B-36

InitializationBlock

32-Bit Base Address Pointer to

Initialization Block

CSR1CSR2

RcvBuffers

•••

RMD0RMD1 RMD2 RMD3

Rcv DescriptorRing

N N NN

••

•

1st Desc.Start

2nd Desc.Start

RMD0

XmtBuffers

•••

RX DESCRIPTOR RINGS

TMD0TMD1 TMD2 TMD3

RX DESCRIPTOR RINGS

Xmt DescriptorRing

M M MM

••

•

1st Desc.Start

2nd Desc.Start

TMD0

DataBuffer

N

DataBuffer

1

DataBuffer

2

DataBuffer

M

DataBuffer

2

DataBuffer

1

PADR[31:0]

IADR[31:16] IADR[15:0]

TLEN RES RLEN RES MODE

PADR[47:32]RESLADRF[31:0]LADRF[63:32]RDRA[31:0]TDRA[31:0]

Figure 29. 32-Bit Initialization Block and Descriptor Rings


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A typical receive poll is the product of the following con-ditions:

1. PCnet-32 controller does not possess ownership ofthe current RDTE and the poll time has elapsed andRXON = 1, or

2. PCnet-32 controller does not possess ownershipof the next RDTE the poll time has elapsed andRXON = 1.

If RXON = 0 the PCnet-32 controller will never pollRDTE locations.

The ideal system should always have at least one RDTEavailable for the possibility of an unpredictable receiveevent. (This condition is not a requirement. If this condi-tion is not met, it simply means that frames will bemissed by the system because there was no bufferspace available.) But the typical system usually has atleast one or two RDTEs available for the possibility of anunpredictable receive event. Given that this condition issatisfied, the current and next RDTE polls are rarelyseen and hence, the typical poll operation simply con-sists of a check of the status of the current TDTE. Whenthere is only one RDTE (because the RLEN was set tozero), then there is no “next RDTE” and ownership of“next RDTE” cannot be checked. If there is at least oneRDTE, the RDTE poll will rarely be seen and the typicalpoll operation simply consists of a check of the currentTDTE.

A typical transmit poll is the product of the followingconditions:

1. PCnet-32 controller does not possess ownership ofthe current TDTE and

DPOLL = 0 and

TXON = 1 and

the poll time has elapsed, or


DPOLL = 0 and

TXON = 1 and

a frame has just been received, or


DPOLL = 0 and

TXON = 1 and

a frame has just been transmitted.

Setting the TDMD bit of CSR0 will cause the microcodecontroller to exit the poll counting code and immediatelyperform a polling operation. If RDTE ownership has notbeen previously established, then an RDTE poll will beperformed ahead of the TDTE poll. If the microcode isnot executing the poll counting code when the TDMD bitis set, then the demanded poll of the TDTE will be de-layed until the microcode returns to the poll count-ing code.

The user may change the poll time value from the de-fault of 65,536 BCLK periods by modifying the valuein the Polling Interval register (CSR47). Note that if anon-default value is desired, then a strict sequence ofsetting the INIT bit in CSR0, waiting for IDON (CSR0[8]),then writing to CSR47, and then setting STRT in CSR0must be observed, otherwise the default value will notbe overwritten. See the CSR47 section for details.

Transmit Descriptor Table Entry (TDTE)If, after a TDTE access, the PCnet-32 controller findsthat the OWN bit of that TDTE is not set, then thePCnet-32 controller resumes the poll time count andreexamines the same TDTE at the next expiration of thepoll time count.

If the OWN bit of the TDTE is set, but STP = 0, thePCnet-32 controller will immediately request the bus inorder to reset the OWN bit of this descriptor. (This condi-tion would normally be found following a LCOL or RE-TRY error that occurred in the middle of a transmitframe chain of buffers.) After resetting the OWN bit ofthis descriptor, the PCnet-32 controller will again imme-diately request the bus in order to access the next TDTElocation in the ring.

If the OWN bit is set and the buffer length is 0, the OWNbit will be reset. In the LANCE the buffer length of 0 isinterpreted as a 4096-byte buffer. It is acceptable tohave a 0 length buffer on transmit with STP = 1 orSTP = 1 and ENP = 1. It is not acceptable to have 0length buffer with STP = 0 and ENP =1.

If the OWN bit is set and the start of packet (STP) bit isset, then microcode control proceeds to a routine thatwill enable transmit data transfers to the FIFO. ThePCnet-32 controller will look ahead to the next transmitdescriptor after it has performed at least one transmitdata transfer from the first buffer. (More than one trans-mit data transfer may possibly take place, dependingupon the state of the transmitter.) The contents of TMD0and TMD1 will be stored in Next Xmt Buffer Address(CSR64 and CSR65), Next Xmt Byte Count (CSR66)and Next Xmt Status (CSR67) regardless of the state ofthe OWN bit. This transmit descriptor look-ahead opera-tion is performed only once.

If the PCnet-32 controller does not own the next TDTE(i.e. the second TDTE for this frame), then it will com-plete transmission of the current buffer and then updatethe status of the current (first) TDTE with the BUFF andUFLO bits being set. This will cause the transmitter to bedisabled (CSR0, TXON=0). The PCnet-32 controller willhave to be re-initialized to restore the transmit function.The situation that matches this description implies thatthe system has not been able to stay ahead of thePCnet-32 controller in the transmit descriptor ring andtherefore, the condition is treated as a fatal error. (Toavoid this situation, the system should always set thetransmit chain descriptor own bits in reverse order.)

If the PCnet-32 controller does own the second TDTE ina chain, it will gradually empty the contents of the first


90 Am79C965

buffer (as the bytes are needed by the transmit opera-tion), perform a single-cycle DMA transfer to update thestatus of the first descriptor (reset the OWN bit inTMD1), and then it may perform one data DMA accesson the second buffer in the chain before executing an-other look-ahead operation (i.e. a look-ahead to the thirddescriptor.)

The PCnet-32 controller can queue up to two frames inthe transmit FIFO. Call them frame “X” and frame “Y”,where “Y” is after “X”. Assume that frame “X” is currentlybeing transmitted. Because the PCnet-32 controller canperform look-ahead data transfer past the ENP of frame“X”, it is possible for the PCnet-32 controller to com-pletely transfer the data from a buffer belonging to frame“Y” into the FIFO even though frame “X” has not yetbeen completely transmitted. At the end of this “Y” bufferdata transfer, the PCnet-32 controller will write interme-diate status (change the OWN bit to a zero) for the “Y”frame buffer, if frame “Y” uses data chaining. The lastTDTE for the “X” frame (containing ENP) has not yetbeen written, since the “X” frame has not yet been com-pletely transmitted. Note that the PCnet-32 controllerhas, in this instance, returned ownership of a TDTE tothe host out of a “normal” sequence. For this reason, itbecomes imperative that the host system should neverread the Transmit DTE ownership bits out of order.

There should be no problems for software which proc-esses buffers in sequence, waiting for ownership beforeproceeding.

If an error occurs in the transmission before all of thebytes of the current buffer have been transferred, thenTMD2 and TMD1 of the current buffer will be written. Insuch a case, data transfers from the next buffer will notcommence. Instead, following the TMD2/TMD1 update,the PCnet-32 controller will go to the next transmitframe, if any, skipping over the rest of the frame whichexperienced an error, including chained buffers. This isdone by returning to the polling microcode wherePCnet-32 controller will immediately access the next de-scriptor and find the condition OWN=1 and STP=0 asdescribed earlier. As described for that case, thePCnet-32 controller will reset the own bit for this descrip-tor and continue in like manner until a descriptor withOWN=0 (no more transmit frames in the ring) orOWN=1 and STP=1 (the first buffer of a new frame)is reached.

At the end of any transmit operation, whether successfulor with errors, immediately following the completion ofthe descriptor updates, the PCnet-32 controller will al-ways perform another poll operation. As described ear-lier, this poll operation will begin with a check of thecurrent RDTE, unless the PCnet-32 controller alreadyowns that descriptor. Then the PCnet-32 controller willproceed to polling the next TDTE. If the transmit descrip-tor OWN bit has a zero value, then the PCnet-32 control-ler will resume poll time count incrementing. If thetransmit descriptor OWN bit has a value of ONE, thenthe PCnet-32 controller will begin filling the FIFO with

transmit data and initiate a transmission. This end-of-operation poll coupled with the TDTE look-ahead opera-tion allows the PCnet-32 controller to avoid inserting polltime counts between successive transmit frames.

Whenever the PCnet-32 controller completes a transmitframe (either with or without error) and writes the statusinformation to the current descriptor, then the TINT bit ofCSR0 is set to indicate the completion of a transmission.This causes an interrupt signal if the IENA bit of CSR0has been set and the TINTM bit of CSR3 is reset.

Receive Descriptor Table Entry (RDTE)If the PCnet-32 controller does not own both the currentand the next Receive Descriptor Table Entry then thePCnet-32 controller will continue to poll according to thepolling sequence described above. If the receive de-scriptor ring length is 1, then there is no next descriptorto be polled.

If a poll operation has revealed that the current and thenext RDTE belong to the PCnet-32 controller then addi-tional poll accesses are not necessary. Future poll op-erations will not include RDTE accesses as long as thePCnet-32 controller retains ownership of the current andthe next RDTE.

When receive activity is present on the channel, thePCnet-32 controller waits for the complete address ofthe message to arrive. It then decides whether to acceptor reject the frame based on all active addressingschemes. If the frame is accepted the PCnet-32 control-ler checks the current receive buffer status registerCRST (CSR41) to determine the ownership of the cur-rent buffer.

If ownership is lacking, then the PCnet-32 controller willimmediately perform a (last ditch) poll of the currentRDTE. If ownership is still denied, then the PCnet-32controller has no buffer in which to store the incomingmessage. The MISS bit will be set in CSR0 and an inter-rupt will be generated if INEA=1 (CSR0) and MISSM=0(CSR3). Another poll of the current RDTE will not occuruntil the frame has finished.

If the PCnet-32 controller sees that the last poll (either anormal poll, or the last-ditch effort described in theabove paragraph) of the current RDTE shows valid own-ership, then it proceeds to a poll of the next RDTE. Fol-lowing this poll, and regardless of the outcome of thispoll, transfers of receive data from the FIFO may begin.

Regardless of ownership of the second receive descrip-tor, the PCnet-32 controller will continue to perform re-ceive data DMA transfers to the first buffer, usingburst-cycle DMA transfers. If the frame length exceedsthe length of the first buffer, and the PCnet-32 controllerdoes not own the second buffer, ownership of the cur-rent descriptor will be passed back to the system by writ-ing a zero to the OWN bit of RMD1 and status will bewritten indicating buffer (BUFF=1) and possibly over-flow (OFLO=1) errors.


91Am79C965

If the frame length exceeds the length of the first (cur-rent) buffer, and the PCnet-32 controller does own thesecond (next) buffer, ownership will be passed back tothe system by writing a zero to the OWN bit of RMD1when the first buffer is full. Receive data transfers to thesecond buffer may occur before the PCnet-32 controllerproceeds to look ahead to the ownership of the thirdbuffer. Such action will depend upon the state of theFIFO when the status has been updated on the first de-scriptor. In any case, look-ahead will be performed tothe third buffer and the information gathered will bestored in the chip, regardless of the state of the owner-ship bit. As in the transmit flow, look-ahead operationsare performed only once.

This activity continues until the PCnet-32 controller rec-ognizes the completion of the frame (the last byte of thisreceive message has been removed from the FIFO).The PCnet-32 controller will subsequently update thecurrent RDTE status with the end of frame (ENP) indica-tion set, write the message byte count (MCNT) of thecomplete frame into RMD2 and overwrite the “current”entries in the CSRs with the “next” entries.

Media Access ControlThe Media Access Control engine incorporates the es-sential protocol requirements for operation of a compli-ant Ethernet/802.3 node, and provides the interfacebetween the FIFO sub-system and the Manchester En-coder/Decoder (MENDEC).

The MAC engine is fully compliant to Section 4 of ISO/IEC 8802-3 (ANSI/IEEE Standard 1990 Second edition)and ANSI/IEEE 802.3 (1985).

The MAC engine provides programmable enhancedfeatures designed to minimize host supervision, busutilization, and pre- or post-message processing. Theseinclude the ability to disable retries after a collision, dy-namic FCS generation on a frame-by-frame basis, andautomatic pad field insertion and deletion to enforceminimum frame size attributes and reduces busbandwidth use.

The two primary attributes of the MAC engine are:

Transmit and receive message data encapsulation.

— Framing (frame boundary delimitation, framesynchronization)

— Addressing (source and destination addresshandling)

— Error detection (physical medium transmissionerrors)

Media access management.

— Medium allocation (collision avoidance)

— Contention resolution (collision handling)

Transmit and Receive Message Data EncapsulationThe MAC engine provides minimum frame size enforce-ment for transmit and receive frames. WhenAPAD_XMT = 1 (CSR4[11]), transmit messages will bepadded with sufficient bytes (containing 00h) to ensurethat the receiving station will observe an informationfield (destination address, source address, length/type,data and FCS) of 64 bytes. When ASTRP_RCV = 1(CSR4[10]), the receiver will automatically strip padbytes from the received message by observing thevalue in the length field, and stripping excess bytes if thisvalue is below the minimum data size (46 bytes). Bothfeatures can be independently over-ridden to allow ille-gally short (less than 64 bytes of frame data) messagesto be transmitted and/or received. Use of this featuredecreases bus usage because the pad bytes are nottransferred into or out of host memory.

Framing (Frame Boundary Delimitation, FrameSynchronization)The MAC engine will autonomously handle the con-struction of the transmit frame. Once the Transmit FIFOhas been filled to the predetermined threshold (set byXMTSP in CSR80), and providing access to the channelis currently permitted, the MAC engine will commencethe 7 byte preamble sequence (10101010b, where firstbit transmitted is a 1). The MAC engine will subse-quently append the Start Frame Delimiter (SFD) byte(10101011b) followed by the serialized data from theTransmit FIFO. Once the data has been completed, theMAC engine will append the FCS (most significant bitfirst) which was computed on the message (destinationaddress, source address, length field, data field, andpad (if applicable)).

Note that the user is responsible for the correct orderingand content in each of the fields in the frame, includingthe destination address, source address, length/typeand frame data.

The receive section of the MAC engine will detect anincoming preamble sequence and lock to the encodedclock. The internal MENDEC will decode the serial bitstream and present this to the MAC engine. The MACwill discard the first 8-bits of information before search-ing for the SFD sequence. Once the SFD is detected, allsubsequent bits are treated as part of the frame. TheMAC engine will inspect the length field to ensure mini-mum frame size, strip unnecessary pad characters (ifenabled), and pass the remaining bytes through the Re-ceive FIFO to the host. If pad stripping is performed, theMAC engine will also strip the received FCS bytes, al-though the normal FCS computation and checking willoccur. Note that apart from pad stripping, the frame will


92 Am79C965

be passed unmodified to the host. If the length field hasa value of 46 or greater, the MAC engine will not attemptto validate the length against the number of bytes con-tained in the message.

If the frame terminates or suffers a collision before 64bytes of information (after SFD) have been received, theMAC engine will automatically delete the frame from theReceive FIFO, without host intervention.

Addressing (Source and Destination Address Handling)The first 6 bytes of information after SFD will be inter-preted as the destination address field. The MAC engineprovides facilities for physical, logical (multicast) andbroadcast address reception. In addition, multiple physi-cal addresses can be constructed (perfect address fil-tering) using external logic in conjunction with theEADI interface.

Error Detection (Physical Medium TransmissionErrors)The MAC engine provides several facilities which reportand recover from errors on the medium. In addition, thenetwork is protected from gross errors due to inability ofthe host to keep pace with the MAC engine activity.

On completion of transmission, the following transmitstatus is available in the appropriate TMD and CSRareas:

The number of transmission retry attempts (ONE,MORE or RTRY).

Whether the MAC engine had to Defer (DEF) due tochannel activity.

Excessive deferral (EXDEF), indicating that thetransmitter has experienced Excessive Deferral onthis transmit frame, where Excessive Deferral is de-fined in ISO 8802-3 (IEEE/ANSI 802.3).

Loss of Carrier (LCAR) indicates that there was aninterruption in the ability of the MAC engine to moni-tor its own transmission. Repeated LCAR errors indi-cate a potentially faulty transceiver or networkconnection.

Late Collision (LCOL) indicates that the transmissionsuffered a collision after the slot time. This is indica-tive of a badly configured network. Late collisionsshould not occur in a normal operating network.

Collision Error (CER) indicates that the transceiverdid not respond with an SQE Test message withinthe predetermined time after a transmission com-pleted. This may be due to a failed transceiver, dis-connected or faulty transceiver drop cable, or thefact the transceiver does not support this feature (orit is disabled).

In addition to the reporting of network errors, the MACengine will also attempt to prevent the creation of anynetwork error due to the inability of the host to servicethe MAC engine. During transmission, if the host fails tokeep the Transmit FIFO filled sufficiently, causing an

underflow, the MAC engine will guarantee the messageis either sent as a runt packet (which will be deleted bythe receiving station) or has an invalid FCS (which willalso cause the receiver to reject the message).

The status of each receive message is available in theappropriate RMD and CSR areas. FCS and Framing er-rors (FRAM) are reported, although the received frameis still passed to the host. The error will only be reportedif an FCS error is detected and there are a non integralnumber of bytes in the message. The MAC engine willignore up to 7 additional bits at the end of a message(dribbling bits), which can occur under normal networkoperating conditions. The reception of 8 additional bitswill cause the MAC engine to de-serialize the entirebyte, and will result in the received message and FCSbeing modified.

The PCnet-32 controller can handle up to 7 dribbling bitswhen a received frame terminates. During the recep-tion, the FCS is generated on every serial bit (includingthe dribbling bits) coming from the cable, although theinternally saved FCS value is only updated on the eighthbit (on each byte boundary). The framing error is re-ported to the user as follows:

If the number of dribbling bits are 1 to 7 and there isno CRC (FCS) error, then there is no Framing error(FRAM = 0).

If the number of dribbling bits are 1 to 7 and there is aCRC (FCS) error, then there is also a Framing error(FRAM = 1).

If the number of dribbling bits = 0, then there is noFraming error. There may or may not be a CRC(FCS) error.

Counters are provided to report the Receive CollisionCount and Runt Packet Count for network statistics andutilization calculations.

Note that if the MAC engine detects a received framewhich has a 00b pattern in the preamble (after the first8-bits which are ignored), the entire frame will be ig-nored. The MAC engine will wait for the network to goinactive before attempting to receive additional frames.

Media Access ManagementThe basic requirement for all stations on the network isto provide fairness of channel allocation. The802.3/Ethernet protocols define a media access mecha-nism which permits all stations to access the channelwith equality. Any node can attempt to contend for thechannel by waiting for a predetermined time (Inter Pack-et Gap internal) after the last activity, before transmittingon the media. The channel is a multidrop communica-tions media (with various topological configurations per-mitted) which allows a single station to transmit and allother stations to receive. If two nodes simultaneouslycontend for the channel, their signals will interact caus-ing loss of data, defined as a collision. It is the responsi-bility of the MAC to attempt to avoid and recover from a


93Am79C965

collision, to guarantee data integrity for the end-to-endtransmission to the receiving station.

Medium AllocationThe IEEE/ANSI 802.3 Standard (ISO/IEC 8802-3 1990)requires that the CSMA/CD MAC monitor the mediumfor traffic by watching for carrier activity. When carrier isdetected, the media is considered busy, and the MACshould defer to the existing message.

The ISO 8802-3 (IEEE/ANSI 802.3) Standard also al-lows optional two part deferral after a receive message.

See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.1:

“Note: It is possible for the PLS carrier sense indica-tion to fail to be asserted during a collision on the me-dia. If the deference process simply times the interpacket gap based on this indication it is possible for ashort inter packet gap to be generated, leading to apotential reception failure of a subsequent frame. Toenhance system robustness the following optionalmeasures, as specified in 4.2.8, are recommendedwhen InterFrameSpacing Part1 is other than zero:

1. Upon completing a transmission, start timing theinterpacket gap, as soon as transmitting and car-rier sense are both false.

2. When timing an inter packet gap following recep-tion, reset the inter packet gap timing if carriersense becomes true during the first 2/3 of the in-ter packet gap timing interval. During the final 1/3of the interval the timer shall not be reset to en-sure fair access to the medium. An initial periodshorter than 2/3 of the interval is permissible in-cluding zero.”

The MAC engine implements the optional receive twopart deferral algorithm, with a first part inter-frame-spac-ing time of 6.0 µs. The second part of the inter-frame-spacing interval is therefore 3.6 µs.

The PCnet-32 controller will perform the two part defer-ral algorithm as specified in Section 4.2.8 (Process Def-erence). The Inter Packet Gap (IPG) timer will starttiming the 9.6 µs InterFrameSpacing after the receivecarrier is de-asserted. During the first part deferral (In-terFrameSpacingPart1 - IFS1) the PCnet-32 controllerwill defer any pending transmit frame and respond to thereceive message. The IPG counter will be reset to zerocontinuously until the carrier de-asserts, at which pointthe IPG counter will resume the 9.6 µs count once again.Once the IFS1 period of 6.0 µs has elapsed, thePCnet-32 controller will begin timing the second part de-ferral (InterFrameSpacingPart2 - IFS2) of 3.6 µs. OnceIFS1 has completed, and IFS2 has commenced, thePCnet-32 controller will not defer to a receive frame if atransmit frame is pending. This means that thePCnet-32 controller will not attempt to receive the re-ceive frame, since it will start to transmit, and generate acollision at 9.6 µs. The PCnet-32 controller will guaran-tee to complete the preamble (64-bit) and jam (32-bit)sequence before ceasing transmission and invoking therandom backoff algorithm.

This transmit two part deferral algorithm is implementedas an option which can be disabled using the DXMT2PDbit in CSR3. Two part deferral after transmission is use-ful for ensuring that severe IPG shrinkage cannot occurin specific circumstances, causing a transmit messageto follow a receive message so closely as to make themindistinguishable.

During the time period immediately after a transmissionhas been completed, the external transceiver (in thecase of a standard AUI connected device), should gen-erate the SQE Test message (a nominal 10 MHz burst of5-15 Bit Times duration) on the CI± pair (within 0.6 - 1.6µs after the transmission ceases). During the time pe-riod in which the SQE Test message is expected thePCnet-32 controller will not respond to receive car-rier sense.

See ANSI/IEEE Std 802.3-1990 Edition, 7.2.4.6 (1)):

“At the conclusion of the output function, the DTEopens a time window during which it expects to seethe signal_quality_error signal asserted on the Con-trol In circuit. The time window begins when theCARRIER_ STATUS becomes CARRIER_OFF. Ifexecution of the output function does not causeCARRIER_ON to occur, no SQE test occurs in theDTE. The duration of the window shall be at least4.0 µs but no more than 8.0 µs. During the time win-dow the Carrier Sense Function is inhibited.”

The PCnet-32 controller implements a carrier sense“blinding” period within 0 µs–4.0 µs from de-assertion ofcarrier sense after transmission. This effectively meansthat when transmit two part deferral is enabled(DXMT2PD is cleared) the IFS1 time is from 4 µs to 6 µsafter a transmission. However, since IPG shrinkage be-low 4 µs will rarely be encountered on a correctly config-ured networks, and since the fragment size will be largerthan the 4 µs blinding window, then the IPG counter willbe reset by a worst case IPG shrinkage/fragment sce-nario and the PCnet-32 controller will defer its transmis-sion. In addition, the PCnet-32 controller will not restartthe “blinding” period if carrier is detected within the4.0 µs – 6.0 µs IFS1 period, but will commence timing ofthe entire IFS1 period.

Contention Resolution (Collision Handling)Collision detection is performed and reported to theMAC engine by the integrated Manchester Encoder/De-coder (MENDEC).

If a collision is detected before the complete preamble/SFD sequence has been transmitted, the MAC Enginewill complete the preamble/SFD before appending thejam sequence. If a collision is detected after the pream-ble/SFD has been completed, but prior to 512 bits beingtransmitted, the MAC Engine will abort the transmis-sion, and append the jam sequence immediately. Thejam sequence is a 32-bit all zeroes pattern.

The MAC Engine will attempt to transmit a frame a totalof 16 times (initial attempt plus 15 retries) due to normalcollisions (those within the slot time). Detection of


94 Am79C965

collision will cause the transmission to be re-scheduled,dependent on the backoff time that the MAC Enginecomputes. If a single retry was required, the ONE bit willbe set in the Transmit Frame Status. If more than oneretry was required, the MORE bit will be set. If all 16attempts experienced collisions, the RTRY bit will be set(ONE and MORE will be clear), and the transmit mes-sage will be flushed from the FIFO. If retries have beendisabled by setting the DRTY bit in CSR15, the MACEngine will abandon transmission of the frame on detec-tion of the first collision. In this case, only the RTRY bitwill be set and the transmit message will be flushed fromthe FIFO.

If a collision is detected after 512 bit times have beentransmitted, the collision is termed a late collision. TheMAC Engine will abort the transmission, append the jamsequence and set the LCOL bit. No retry attempt will bescheduled on detection of a late collision, and the trans-mit message will be flushed from the FIFO.

The ISO 8802-3 (IEEE/ANSI 802.3) Standard requiresuse of a “truncated binary exponential backoff” algo-rithm which provides a controlled pseudo randommechanism to enforce the collision backoff interval, be-fore re-transmission is attempted.

See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.5:

“At the end of enforcing a collision (jamming), theCSMA/CD sublayer delays before attempting to re-transmit the frame. The delay is an integer multiple ofslotTime. The number of slot times to delay beforethe nth re-transmission attempt is chosen as a uni-formly distributed random integer r in the range:

0 ≤ r < 2k –1

where k = min (n,10).”

The PCnet-32 controller provides an alternative algo-rithm, which suspends the counting of the slot time/IPGduring the time that receive carrier sense is detected.This aids in networks where large numbers of nodes arepresent, and numerous nodes can be in collision. It ef-fectively accelerates the increase in the backoff time inbusy networks, and allows nodes not involved in the col-lision to access the channel whilst the colliding nodesawait a reduction in channel activity. Once channel ac-tivity is reduced, the nodes resolving the collision timeout their slot time counters as normal.

Manchester Encoder/Decoder (MENDEC)The integrated Manchester Encoder/Decoder providesthe PLS (Physical Layer Signaling) functions requiredfor a fully compliant ISO 8802-3 (IEEE/ANSI 802.3) sta-tion. The MENDEC provides the encoding function fordata to be transmitted on the network using the high ac-curacy on-board oscillator, driven by either the crystaloscillator or an external CMOS level compatible clock.The MENDEC also provides the decoding function fromdata received from the network. The MENDEC containsa Power On Reset (POR) circuit, which ensures that allanalog portions of the PCnet-32 controller are forced

into their correct state during power up, and preventserroneous data transmission and/or reception duringthis time.

External Crystal CharacteristicsWhen using a crystal to drive the oscillator, the crystalspecification shown in Table 26 may be used to ensureless than ±0.5 ns jitter at the transmit outputs.

Table 26. External Crystal Specification

1.Parallel Resonant Frequency 20 MHz

2.Resonant Frequency Error –50 +50 PPM

3.Change in Resonant Frequency With Respect To Temperature –40 +40 PPM(0°C–70°C)*

4.Crystal Load Capacitance 20 50 pF

5.Motional Crystal Capacitance (C1) 0.022 pF

6.Series Resistance 25 ohm

7.Shunt Capacitance 7 pF

8.Drive Level TBD mW

*Requires trimming spec.; no trim is 50 ppm total.

Min Nom Max UnitParameter

External Clock Drive CharacteristicsWhen driving the oscillator from an external clocksource, XTAL2 must be left floating (unconnected). Anexternal clock having the following characteristics mustbe used to ensure less than ±0.5 ns jitter at the transmitoutputs. See Table 27.

Table 27. External Clock Drive Characteristics

Clock Frequency: 20 MHz ±0.01%

Rise/Fall Time (tR/tF): < 6 ns from 0.5 V to VDD–0.5

XTAL1 HIGH/LOW Time 20 ns min

(tHIGH/tLOW):

XTAL1 Falling Edge to < ±0.2 ns at Falling Edge Jitter: 2.5 V input (VDD/2)

MENDEC Transmit PathThe transmit section encodes separate clock and NRZdata input signals into a standard Manchester encodedserial bit stream. The transmit outputs (DO±/TXD±) aredesigned to operate into terminated transmission lines.When operating into a 78 Ω terminated transmissionline, the transmit signaling meets the required outputlevels and skew for Cheapernet, Ethernet andIEEE-802.3.

Transmitter Timing and OperationA 20 MHz fundamental mode crystal oscillator providesthe basic timing reference for the MENDEC portion ofthe PCnet-32 controller. The crystal is divided by two, tocreate the internal transmit clock reference. Both clocksare fed into the MENDEC’s Manchester Encoder to gen-erate the transitions in the encoded data stream. The


95Am79C965

internal transmit clock is used by the MENDEC to inter-nally synchronize the Internal Transmit Data (ITXDAT)from the controller and Internal Transmit Enable(ITXEN). The internal transmit clock is also used as astable bit rate clock by the receive section of theMENDEC and controller.

The oscillator requires an external ±0.01% timing refer-ence. The accuracy requirements, if an external crystalis used are tighter because allowance for the on-boardparasitics must be made to deliver a final accuracy of0.01%.

Transmission is enabled by the controller. As long as theITXEN request remains active, the serial output of thecontroller will be Manchester encoded and appear atDO±/TXD±. When the internal request is dropped by thecontroller, the differential transmit outputs go to one oftwo idle states, dependent on TSEL in the ModeRegister (CSR15, bit 9):

TSEL LOW: The idle state of DO±/TXD± yields “zero”differential to operate transformer-coupledloads.

TSEL HIGH: In this idle state, DO+/TXD+ is positivewith respect to DO–/TXD– (logical HIGH).

Receiver PathThe principal functions of the Receiver are to signal thePCnet-32 controller that there is information on the re-ceive pair, and separate the incoming Manchester en-coded data stream into clock and NRZ data.

The Receiver section (see Figure 30) consists of twoparallel paths. The receive data path is a zero threshold,wide bandwidth line receiver. The carrier path is an off-set threshold bandpass detecting line receiver. Both re-ceivers share common bias networks to allow operationover a wide input common mode range.

Input Signal ConditioningTransient noise pulses at the input data stream are re-jected by the Noise Rejection Filter. Pulse width rejec-tion is proportional to transmit data rate.

The Carrier Detection circuitry detects the presence ofan incoming data frame by discerning and rejectingnoise from expected Manchester data, and controls thestop and start of the phase-lock loop during clock acqui-sition. Clock acquisition requires a valid Manchester bitpattern of 1010b to lock onto the incoming message.

When input amplitude and pulse width conditions aremet at DI±/RXD±, the internal enable signal from theMENDEC to controller (IRXCRS) is asserted and aclock acquisition cycle is initiated.

Clock AcquisitionWhen there is no activity at DI± (receiver is idle), thereceive oscillator is phase locked to the internal transmitclock. The first negative clock transition (bit cell center offirst valid Manchester “0”) after IRXCRS is asserted in-terrupts the receive oscillator. The oscillator is then re-started at the second Manchester “0” (bit time 4) and isphase locked to it. As a result, the MENDEC acquiresthe clock from the incoming Manchester bit pattern in 4bit times with a “1010” Manchester bit pattern.

ISRDCLK and IRXDAT are enabled 1/4 bit time afterclock acquisition in bit cell 5. IRXDAT is at a HIGH statewhen the receiver is idle (no ISRDCLK). IRXDAT how-ever, is undefined when clock is acquired and may re-main HIGH or change to LOW state wheneverISRDCLK is enabled. At 1/4 bit time through bit cell 5,the controller portion of the PCnet-32 controller sees thefirst ISRDCLK transition. This also strobes in the incom-ing fifth bit to the MENDEC as Manchester “1”. IRXDATmay make a transition after the ISRDCLK rising edge inbit cell 5, but its state is still undefined. The Manchester“1” at bit 5 is clocked to IRXDAT output at 1/4 bit time inbit cell 6.

NoiseRejectFilter

DataReceiver

CarrierDetectCircuit

ManchesterDecoder

IRXDAT*

ISRDCLK*

IRXCRS*

DI±/RXD±

*Internal signal

18219B-37

Figure 30. Receiver Block Diagram


96 Am79C965

PLL TrackingAfter clock acquisition, the phase-locked clock is com-pared to the incoming transition at the bit cell center(BCC) and the resulting phase error is applied to a cor-rection circuit. This circuit ensures that the phase-locked clock remains locked on the received signal.Individual bit cell phase corrections of the VoltageControlled Oscillator (VCO) are limited to 10% of thephase difference between BCC and phase-lockedclock. Hence, input data jitter is reduced in ISRDCLK by10 to 1.

Carrier Tracking and End of MessageThe carrier detection circuit monitors the DI± inputs afterIRXCRS is asserted for an end of message. IRXCRSde-asserts 1 to 2 bit times after the last positive transi-tion on the incoming message. This initiates the end ofreception cycle. The time delay from the last rising edgeof the message to IRXCRS de-assert allows the last bitto be strobed by ISRDCLK and transferred to the con-troller section, but prevents any extra bit(s) at the endof message.

Data DecodingThe data receiver is a comparator with clocked output tominimize noise sensitivity to the DI±/RXD± inputs. Inputerror is less than ± 35 mV to minimize sensitivity to inputrise and fall time. ISRDCLK strobes the data receiveroutput at 1/4 bit time to determine the value of theManchester bit, and clocks the data out on IRXDAT onthe following ISRDCLK. The data receiver also gener-ates the signal used for phase detector comparison tothe internal MENDEC voltage controlled oscillator(VCO).

Jitter Tolerance DefinitionThe MENDEC utilizes a clock capture circuit to align itsinternal data strobe with an incoming bit stream. Theclock acquisition circuitry requires four valid bits with thevalues 1010b. Clock is phase-locked to the negativetransition at the bit cell center of the second “0” inthe pattern.

Since data is strobed at 1/4 bit time, Manchester transi-tions which shift from their nominal placement through1/4 bit time will result in improperly decoded data. Withthis as the criteria for an error, a definition of “JitterHandling” is:

The peak deviation approaching or crossing 1/4 bitcell position from nominal input transition, for whichthe MENDEC section will properly decode data.

Attachment Unit Interface(AUI)The AUI is the PLS (Physical Layer Signaling) to PMA(Physical Medium Attachment) interface which effec-tively connects the DTE to a MAU. The differentialinterface provided by the PCnet-32 controller is fullycompliant to Section 7 of ISO 8802-3 (ANSI/IEEE802.3).

After the PCnet-32 controller initiates a transmission itwill expect to see data “looped-back” on the DI± pair

(when the AUI port is selected). This will internally gen-erate a “carrier sense”, indicating that the integrity of thedata path to and from the MAU is intact, and that theMAU is operating correctly. This “carrier sense” signalmust be asserted within TBD bit times after the firsttransmitted bit on DO± (when using the AUI port). If “car-rier sense” does not become active in response to thedata transmission, or becomes inactive before the endof transmission, the loss of carrier (LCAR) error bit willbe set in the Transmit Descriptor Ring (TMD2, bit27)after the frame has been transmitted.

Differential Input TerminationsThe differential input for the Manchester data (DI±) isexternally terminated by two 40.2 Ω ±1% resistors andone optional common-mode bypass capacitor, asshown in the Differential Input Termination diagram be-low. The differential input impedance, ZIDF, and thecommon-mode input impedance, ZICM, are specified sothat the Ethernet specification for cable termination im-pedance is met using standard 1% resistor terminators.If SIP devices are used, 39 Ω is also a suitable value.The CI± differential inputs are terminated in exactly thesame way as the DI± pair.

PCnet-ISA

DI+

DI-

40.2 Ω 40.2 Ω

0.01 µFto 0.1 µF

AUI IsolationTransformer

16907B-918219B-38

PCnet-32

Figure 31. AUI Differential Input Termination

Collision DetectionA MAU detects the collision condition on the networkand generates a differential signal at the CI± inputs. Thiscollision signal passes through an input stage which de-tects signal levels and pulse duration. When the signal isdetected by the MENDEC it sets the ICLSN line HIGH.The condition continues for approximately 1.5 bit timesafter the last LOW-to-HIGH transition on CI±.

Twisted-Pair Transceiver (T-MAU)The T-MAU implements the Medium Attachment Unit(MAU) functions for the Twisted Pair Medium, as speci-fied by the supplement to ISO 8802-3 (IEEE/ANSI802.3) standard (Type 10BASE-T). The T-MAU pro-vides twisted pair driver and receiver circuits, includingon-board transmit digital predistortion and receiversquelch and a number of additional features includingLink Status indication, Automatic Twisted Pair ReceivePolarity Detection/Correction and Indication, Receive


97Am79C965

Carrier Sense, Transmit Active and Collision Presentindication.

T-MAU gets reset during power-up by H_RESET, byS_RESET when reset port is read, or by asserting theRESET pin. T-MAU is not reset by STOP.

Twisted Pair Transmit FunctionThe differential driver circuitry in the TXD± and TXP±pins provides the necessary electrical driving capabilityand the pre-distortion control for transmitting signalsover maximum length Twisted Pair cable, as specifiedby the 10BASE-T supplement to the ISO 8802-3 (IEEE/ANSI 802.3) Standard. The transmit function for dataoutput meets the propagation delays and jitter specifiedby the standard.

Twisted Pair Receive FunctionThe receiver complies with the receiver specifications ofthe ISO 8802-3 (IEEE/ANSI 802.3) 10BASE-T Stan-dard, including noise immunity and received signal re-jection criteria (‘Smart Squelch’). Signals meeting thiscriteria appearing at the RXD± differential input pair arerouted to the MENDEC. The receiver function meets thepropagation delays and jitter requirements specified bythe standard. The receiver squelch level drops to half itsthreshold value after unsquelch to allow reception ofminimum amplitude signals and to offset carrier fade inthe event of worst case signal attenuation and crosstalknoise conditions.

Note that the 10BASE-T Standard defines the receiveinput amplitude at the external Media Dependent Inter-face (MDI). Filter and transformer loss are not specified.The T-MAU receiver squelch levels are defined to ac-count for a 1 dB insertion loss at 10 MHz, which is typicalfor the type of receive filters/transformers employed.

Normal 10BASE-T compatible receive thresholds areemployed when the LRT (CSR15[9]) bit is LOW. Whenthe LRT bit is set (HIGH), the Low Receive Thresholdoption is invoked, and the sensitivity of the T-MAU re-ceiver is increased. This allows longer line lengths to beemployed, exceeding the 100 m target distance of nor-mal 10BASE-T (assuming typical 24 AWG cable). Theincreased receiver sensitivity compensates for the in-creased signal attenuation caused by the additional ca-ble distance.

However, making the receiver more sensitive meansthat it is also more susceptible to extraneous noise, pri-marily caused by coupling from co-resident services(crosstalk). For this reason, it is recommended thatwhen using the Low Receive Threshold option that theservice should be installed on 4-pair cable only. Multi-pair cables within the same outer sheath have lowercrosstalk attenuation, and may allow noise emitted fromadjacent pairs to couple into the receive pair, and be ofsufficient amplitude to falsely unsquelch the T-MAU.

Link Test FunctionThe link test function is implemented as specified by10BASE-T standard. During periods of transmit pair in-activity, ’Link beat pulses’ will be periodically sent over

the twisted pair medium to constantly monitor mediumintegrity.

When the link test function is enabled (DLNKTST bit inCSR15 is cleared), the absence of link beat pulses andreceive data on the RXD± pair will cause the T-MAU togo into a link fail state. In the link fail state, data transmis-sion, data reception, data loopback and the collision de-tection functions are disabled, and remain disabled untilvalid data or >5 consecutive link pulses appear on theRXD± pair. During link fail, the Link Status signal is inac-tive. When the link is identified as functional, the LinkStatus signal is asserted. The LNKST pin displays theLink Status signal by default.

Transmission attempts during Link Fail state will pro-duce no network activity and will produce LCAR andCERR error indications.

In order to inter-operate with systems which do not im-plement Link Test, this function can be disabled by set-ting the DLNKTST bit in CSR15. With link test disabled,the data driver, receiver and loopback functions as wellas collision detection remain enabled irespective of thepresence or absence of data or link pulses on the RXD±pair. Link Test pulses continue to be sent regardless ofthe state of the DLNKTST bit.

Polarity Detection and ReversalThe T-MAU receive function includes the ability to invertthe polarity of the signals appearing at the RXD± pair ifthe polarity of the received signal is reversed (such as inthe case of a wiring error). This feature allows dataframes received from a reverse wired RXD± input pair tobe corrected in the T-MAU prior to transfer to theMENDEC. The polarity detection function is activatedfollowing H_RESET or Link Fail, and will reverse thereceive polarity based on both the polarity of any previ-ous link beat pulses and the polarity of subsequentframes with a valid End Transmit Delimiter (ETD).

When in the Link Fail state, the T-MAU will recognizelink beat pulses of either positive or negative polarity.Exit from the Link Fail state is made due to the receptionof 5–6 consecutive link beat pulses of identical polarity.On entry to the Link Pass state, the polarity of the last 5link beat pulses is used to determine the initial receivepolarity configuration and the receiver is reconfigured tosubsequently recognize only link beat pulses of the pre-viously recognized polarity.

Positive link beat pulses are defined as received signalwith a positive amplitude greater than 585 mV (LRT =HIGH) with a pulse width of 60 ns–200 ns. This positiveexcursion may be followed by a negative excursion.This definition is consistent with the expected receivedsignal at a correctly wired receiver, when a link beatpulse which fits the template of Figure 14-12 of the10BASE-T Standard is generated at a transmitter andpassed through 100 m of twisted pair cable.

Negative link beat pulses are defined as received sig-nals with a negative amplitude greater than 585 mV witha pulse width of 60 ns–200 ns. This negative excursion


98 Am79C965

may be followed by a positive excursion. This definitionis consistent with the expected received signal at a re-verse wired receiver, when a link beat pulse which fitsthe template of Figure 14-12 in the 10BASE-T Standardis generated at a transmitter and passed through 100 mof twisted pair cable.

The polarity detection/correction algorithm will remain“armed” until two consecutive frames with valid ETD ofidentical polarity are detected. When “armed”, the re-ceiver is capable of changing the initial or previous po-larity configuration based on the ETD polarity.

On receipt of the first frame with valid ETD followingH_RESET or link fail, the T-MAU will utilize the inferredpolarity information to configure its RXD± input, regard-less of its previous state. On receipt of a second framewith a valid ETD with correct polarity, the detection/cor-rection algorithm will “lock-in” the received polarity. If thesecond (or subsequent) frame is not detected as con-firming the previous polarity decision, the most recentlydetected ETD polarity will be used as the default. Notethat frames with invalid ETD have no effect on updatingthe previous polarity decision. Once two consecutiveframes with valid ETD have been received, the T-MAUwill disable the detection/correction algorithmuntil either a Link Fail condition occurs or H_RESET isactivated.

During polarity reversal, an internal POL signal will beactive. During normal polarity conditions, this internalPOL signal is inactive. The state of this signal can beread by software and/or displayed by LED when en-abled by the LED control bits in the Bus ConfigurationRegisters (BCR4–BCR7).

Twisted Pair Interface StatusThree signals (XMT, RCV and COL) indicate whetherthe T-MAU is transmitting, receiving, or in a collisionstate with both functions active simultaneously. Thesesignals are internal signals and the behavior of the LEDoutputs depends on how the LED Output circuiting isprogrammed.

The T-MAU will power up in the Link Fail state and thenormal algorithm will apply to allow it to enter the LinkPass state. In the Link Pass state, transmit or receiveactivity will be indicated by assertion of RCV signal go-ing active. If T-MAU is selected using the PORTSEL bitsin CSR15, then when moving from AUI to T-MAU selec-tion the T-MAU will be forced into the Link Fail state.

In the Link Fail state, XMT, RCV and COL are inactive.

Collision Detect FunctionActivity on both twisted pair signals RXD± and TXD±constitutes a collision, thereby causing the COL signalto be activated. (COL is used by the LED control circuits)COL will remain active until one of the two colliding sig-nals changes from active to idle. However, transmissionattempt in Link Fail state results in LCAR and CERR

indication. COL stays active for 2-bit times at the end ofa collision.

Signal Quality Error (SQE) Test (Heartbeat) FunctionThe SQE function is disabled when the 10BASE-T portis selected.

Jabber FunctionThe Jabber function inhibits the twisted pair transmitfunction of the T-MAU if the TXD± circuit is active for anexcessive period (20 ms–150 ms). This prevents anyone node from disrupting the network due to a ’stuck-on’or faulty transmitter. If this maximum transmit time isexceeded, the T-MAU transmitter circuitry is disabled,the JAB bit is set (CSR4, bit1), the COL signal is as-serted. Once the transmit data stream to the T-MAU isremoved, an “unjab” time of 250 ms–750 ms will elapsebefore the T-MAU COL and re-enables the trans-mit circuitry.

Power DownThe T-MAU circuitry can be made to go into power sav-ings mode. This feature is useful in battery powered orlow duty cycle systems. The T-MAU will go into powerdown mode when H_RESET is active, coma mode isactive, or the T-MAU is not selected. Refer to the PowerSavings Modes section for descriptions of the variouspower down modes.

Any of the three conditions listed above resets the inter-nal logic of the T-MAU and places the device into powerdown mode. In this mode, the Twisted Pair driver pins(TXD±,TXP±) are driven LOW, and the internal T-MAUstatus signals (LNKST, RCVPOL, XMT, RCV and COL)signals are inactive.

Once H_RESET ends, coma mode is disabled, and theT-MAU is selected. The T-MAU will remain in the resetstate for up to 10 µs. Immediately after the reset condi-tion is removed, the T-MAU will be forced into the LinkFail state. The T-MAU will move to the Link Pass stateonly after 5 – 6 link beat pulses and/or a single receivedmessage is detected on the RD± pair.

In snooze mode, the T-MAU receive circuitry will remainenabled even while the SLEEP pin is driven LOW.

The T-MAU circuitry will always go into power downmode if H_RESET is asserted, coma mode is enabled,or the T-MAU is not selected.

10BASE-T Interface ConnectionFigure 32 shows the proper 10BASE-T network inter-face design. Refer to the PCnet Family Technical Man-ual (PID # 18216A) for more design details, and refer toAppendix A for a list of compatible 10BASE-T filter/transformer modules.

Note that the recommended resistor values and filterand transformer modules are the same as those used bythe IMR (Am79C980) and the IMR+ (Am79C981).


99Am79C965

18219B-39

XMTFilter

RCVFilter

RJ45Connector

Filter &Transformer

Module

PCnet-32

TD+

TD-

RD+

RD-

1

2

3

6

61.9 Ω

422 Ω

61.9 Ω

422 Ω

100 Ω

1.21 KΩ1:1

1:1

TXD+

TXP+

TXD-

TXP-

RXD+

RXD-

Figure 32. 10BASE-T Interface Connection

IEEE 1149.1 Test Access Port InterfaceAn IEEE 1149.1 compatible boundary scan Test AccessPort is provided for board level continuity test and diag-nostics. All digital input, output and input/output pins aretested. Analog pins, including the AUI differential driver(DO±) and receivers (DI±, CI±), and the crystal input(XTAL1/XTAL2) pins, are tested. The T-MAU driversTXD±, TXP± and receiver RXD± are also tested.

The following is a brief summary of the IEEE 1149.1compatible test functions implemented in the PCnet-32controller.

Boundary Scan CircuitThe boundary scan test circuit requires four pins (TCK,TMS, TDI and TDO), defined as the Test Access Port(TAP). It includes a finite state machine (FSM), an in-struction register, a data register array, and a power-onreset circuit. Internal pull-up resistors are provided forthe TDI, TCK, and TMS pins. The TCK pin must not beleft unconnected. The boundary scan circuit remains ac-tive during Sleep.

TAP FSMThe TAP engine is a 16-state FSM, driven by the TestClock (TCK) and the Test Mode Select (TMS) pins. This

FSM is in its reset state at power-up or after H_RESET.An independent power-on reset circuit is provided to en-sure the FSM is in the TEST_LOGIC_RESET state atpower-up.

Supported InstructionsIn addition to the minimum IEEE 1149.1 requirements(BYPASS, EXTEST, and SAMPLE instructions), threeadditional instructions (IDCODE, TRIBYP and SET-BYP) are provided to further ease board-level testing.All unused instruction codes are reserved. See Table 28for a summary of supported instructions.

Instruction Register and Decoding LogicAfter H_RESET or S_RESET or STOP, the IDCODEinstruction is always invoked. The decoding logic givessignals to control the data flow in the DATA registersaccording to the current instruction.

Boundary Scan Register (BSR)Each BSR cell has two stages. A flip-flop and a latch areused for the SERIAL SHIFT STAGE and the PARALLELOUTPUT STAGE, respectively.

Table 28. IEEE 1149.1 Supported Instruction Summary

Instruction Selected InstructionName Description Data Reg Mode Code

EXTEST External Test BSR Test 0000

IDCODE ID Code Inspection ID REG Normal 0001

SAMPLE Sample Boundary BSR Normal 0010

TRIBYP Force Tristate Bypass Normal 0011

SETBYP Control Boundary To 1/0 Bypass Test 0100

BYPASS Bypass Scan Bypass Normal 1111


100 Am79C965

There are four possible operation modes in theBSR cell:

1 Capture

2 Shift

3 Update

4 System Function

Other Data Register

1) BYPASS REG (1 Bit)

2) DEV ID REG (32 bits)

Bits 31–28: Version

Bits 27–12: Part number (0010 0100 0011 0000)

Bits 11–1: Manufacturer ID. The 11 bit manufacturer ID code for AMD is 00000000001 according to JEDEC Publication 106-A.

Bit 0: Always a logic 1

3) INSCAN0

This is an internal scan path for AMD internal test-ing use.

EADI (External Address Detection Interface)This interface is provided to allow external address filter-ing. It is selected by setting the EADISEL bit in BCR2 toa ONE. This feature is typically utilized for terminal serv-ers, bridges and/or router products. The EADI interfacecan be used in conjunction with external logic to capturethe packet destination address from the serial bit streamas it arrives at the PCnet-32 controller, compare thecaptured address with a table of stored addresses oridentifiers, and then determine whether or not thePCnet-32 controller should accept the packet.

The EADI interface outputs are delivered directly fromthe NRZ decoded data and clock recovered by theManchester decoder or input into the GPSI port. Thisallows the external address detection to be performed inparallel with frame reception and address comparison inthe MAC Station Address Detection (SAD) block of thePCnet-32 controller.

SRDCLK is provided to allow clocking of the receive bitstream into the external address detection logic.SRDCLK runs only during frame reception activity.Once a received frame commences and data and clockare available from the decoder, the EADI logic will moni-tor the alternating (“1,0”) preamble pattern until the twoones of the Start Frame Delimiter (“1,0,1,0,1,0,1,1”) aredetected, at which point the SF/BD output will bedriven HIGH.

The SF/BD signal will initially be LOW. The assertion ofSF/BD is a signal to the external address detection logicthat the SFD has been detected and that subsequentSRDCLK cycles will deliver packet data to the external

logic. Therefore, when SF/BD is asserted, the externaladdress matching logic should begin de-serialization ofthe SRD data and send the resulting destination ad-dress to a content addressable memory (CAM) or otheraddress detection device.

In order to reduce the amount of logic external to thePCnet-32 controller for multiple address decoding sys-tems, the SF/BD signal will toggle at each new byteboundary within the packet, subsequent to the SFD.This eliminates the need for externally supplying byteframing logic.

The EAR pin should be driven LOW by the external ad-dress comparison logic to reject a frame.

If an address match is detected by internal addresscomparison with either the Physical or Logical or broad-cast Address contained within the PCnet-32 controller,then the frame will be accepted regardless of the condi-tion of EAR. Internal address match is disabled whenPROM (CSR15[15]) = 0, DRCVBC (CSR15[14]) = 1,DRCVPA (CSR15[13]) = 1 and Logical Address Filter(CSR8–CSR11) = 0.

When the EADISEL bit of BCR2 is set to a ONE andinternal address match is disabled, then all incomingframes will be accepted by the PCnet-32 controller, un-less the EAR pin becomes active during the first 64bytes of the frame (excluding preamble and SFD). Thisallows external address lookup logic approximately 58byte times after the last destination address bit is avail-able to generate the EAR signal, assuming that thePCnet-32 controller is not configured to accept runtpackets. EAR will be ignored after 64 byte times after theSFD. The frame will be accepted if EAR has not beenasserted before this time. If Runt Packet Accept is en-abled, then the EAR signal must be generated prior tothe receive message completion, if packet rejection is tobe guaranteed. Runt packet sizes could be as short as12 byte times (assuming 6 bytes for source address,2 bytes for length, no data, 4 bytes for FCS) after the lastbit of the destination address is available. EAR musthave a pulse width of at least 150 ns.

When the EADISEL bit of BCR2 is set to a ONE and thePROM bit of the Mode Register is set to a ONE, then allincoming frames will be accepted by the PCnet-32 con-troller, regardless of any activity on the EAR pin.

The EADI outputs continue to provide data throughoutthe reception of a packet. This allows the external logicto capture packet header information to determineprotocol type, inter-networking information, and otheruseful data.

The EADI interface will operate as long as the STRT bitin CSR0 is set, even if the receiver and/or transmitterare disabled by software (DTX and DRX bits in CSR15are set). This configuration is useful as a semi-power-down mode in that the PCnet-32 controller will not per-form any power-consuming DMA operations. However,


101Am79C965

external circuitry can still respond to “control” frames onthe network to facilitate remote node control.

Table 29 summarizes the operation of the EADIinterface.

Table 29. EADI Operations

ReceivedPROM EAR Required Timing Messages

1 X No timing requirements All Received Frames

0 1 No timing requirements All Received Frames

0 0 Low for 150 ns within PCnet-32 Controller512 bits after SFD Internal Physical and

Logical AddressMatches

General Purpose Serial Interface (GPSI)The PCnet-32 controller is capable of providing a purelydigital network interface in the form of the General Pur-pose Serial Interface. This interface matches the func-tionality provided by earlier AMD network controllerproducts, such as the Am7990 LANCE, Am79C90C-LANCE, Am79C900 ILACC controller, Am79C940MACE controller, and Am79C960 PCnet-ISA controller.

The GPSI interface is selected through the PORTSELbits of the Mode register (CSR15) and enabled throughthe TSTSHDW bits of BCR18 (bits 3 and 4) or enabledthrough the GPSIEN bit in CSR124 (bit 4). The possiblesettings to invoke the GPSI mode are shown inTable 30.

Table 30. GPSI Mode Selection

TSTSHDWValue PVALID GPSIEN Operating

(BCR18 [4:3]) (BCR19 [15]) (CSR124[4]) Mode

00 1 0 NormalOperating

Mode

10 1 X GPSI Mode

01 1 0 Reserved

11 1 X Reserved

XX 0 0 NormalOperating

Mode

XX 0 1 GPSI Mode

Note that the TSTSHDW bit values are only active whenPVALID is TRUE.

The GPSI interface is multiplexed through 7 of the upper8 address bits of the system bus interface. Therefore,applications that require the use of the GPSI interfacewill be limited to the use of only 24 address bits (A[23]through A[2] plus the byte enables, which decode intotwo effective address bits).

In order to prevent the PCnet-32 controller from inter-preting the GPSI signals as address bits during the Soft-ware Relocatable Mode and during slave accesses, the24-bit Software Relocatable Mode Address 24 modeand the I/O Address Width 24 mode of the PCnet-32controller must be invoked. Note that if SoftwareRelocatable Mode is invoked, then PVALID must havebeen set to ZERO, and, therefore, the GPSI mode is notactive and therefore, the Software Relocatable Modemight assume that all 30 address bits are visible. But in asystem that uses GPSI mode, the GPSI signals wouldlikely all be hardwired to the address pins, and, there-fore, even though the device never made it into GPSImode, it will still not be able to see the upper addressbits. Therefore, it is always recommended that SRMA24mode be invoked as described in the next paragraph:

Software Relocatable Mode Address 24 mode is in-voked by connecting the LED2/SRDCLK pin to a LOWlevel during H_RESET and during the execution of theSoftware Relocation operation. When the LED2/SRDCLK pin is LOW during H_RESET and SoftwareRelocatable Mode, then the device will be programmedto use 24 bits of addressing while snooping accesses onthe bus during Software Relocatable Mode; In this case,the PCnet-32 controller will assume that bits A[31]through A[24] are matched at all times, regardless of theactual values on these pins.

I/O Address Width 24 mode is invoked by writing a ONEto the IOAW24 bit of BCR21 (bit 8 of BCR21). This canbe accomplished safely in either of two ways:

1) A Software Relocation operation can write a ONE toBCR21, bit 8

2) A read of the EEPROM contents can write a ONE toBCR21, bit 8, if the EEPROM contents are correctlyprogrammed

These two methods do NOT require a slave access tothe PCnet-32 controller, and therefore may be per-formed in a system in which the GPSI signals are per-manently connected to the A[31] through A[23] pins(assuming SRMA24 mode is invoked via the LED2/SRDCLK pin to use method 1).

The PCnet-32 controller upper address pins are recon-figured during GPSI mode to the functions listed inTable 31. Note that pin number 143 (A24) has noequivalent GPSI function and should be left uncon-nected when GPSI mode is enabled.

GPSI signal functions are described in the pin descrip-tion section under the GPSI subheading.

At the time that GPSI mode is entered, the internal MACclock is switched from a XTAL1-derived clock to a clockderived from the STDCLK input. The STDCLK input de-termines the network data rate and therefore must meetfrequency and stability specifications.


102 Am79C965

Table 31. GPSI Pin Configurations

GPSI PCnet-32/ PCnet-32 PCnet-32I/O LANCE ILACC PCnet-ISA Pin Normal

GPSI Function Type GPSI Pin GPSI Pin GPSI Pin Number Pin Function

Transmit Data O TX TXD TXDAT 132 A31

Transmit Enable O TENA RTS TXEN 133 A30

Transmit Clock I TCLK TXC STDCLK 134 A29

Collision I CLSN CDT CLSN 137 A28

Receive Carrier Sense I RENA CRS RXCRS 138 A27

Receive Clock I RCLK RXC SRDCLK 140 A26

Receive Data I RX RXD RXDAT 141 A25

Note that the XTAL1 input must always be driven with aclock source, even if GPSI mode is to be used. It is notnecessary for the XTAL1 clock to meet the normal fre-quency and stability requirements in this case. Any fre-quency between 8 MHz and 20 MHz is acceptable.However, voltage drive requirements do not change.When GPSI mode is used, XTAL1 must be driven forseveral reasons:

1) The default pin RESET configuration for thePCnet-32 controller is “AUI port selected,” and untilGPSI mode is selected, the XTAL1 clock is neededfor some internal operations (namely, RESET).

2) The XTAL1 clock drives the EEPROM read opera-tion, regardless of the network mode selected.

3) The XTAL1 clock determines the length of a ResetRegister read operation, regardless of the networkmode selected (due to the internal RESET causedby the read).

Note that if a clock slower than 20 MHz is provided at theXTAL1 input, the time needed for EEPROM read andReset Register Read operations will increase.

Power Savings ModesThe PCnet-32 controller supports two hardware powersavings modes. Both are entered by driving the SLEEPpin LOW.

In coma mode, the PCnet-32 controller will go into adeep sleep with no means to use the network to auto-matically wake itself up. Coma mode is enabled whenthe AWAKE bit in BCR2 is reset. Coma mode is the de-fault power down mode. When coma mode is invoked,the T-MAU circuitry will go into power down mode. Thesystem bus interface will be floated and inactive duringcoma mode. LDEV and the selected interrupt pin will bedriven to inactive levels. While in coma mode, if thePCnet-32 controller is configured for a daisy chain(HOLDI and HLDAO or LREQI and LGNTO signalshave been selected with the JTAGSEL pin), then thedaisy chain signal LREQI/HOLDI will be passed directlyto LREQ/HOLD and the system arbitration signal LGNT/

HLDA will be passed directly to the daisy-chain signalLGNTO/HLDAO.

In snooze mode, enabled by setting the AWAKE bit inBCR2 and driving the SLEEP pin LOW, the T-MAU re-ceive circuitry will remain enabled even while theSLEEP pin is driven LOW. The LNKST output will alsocontinue to function, indicating a good 10BASE-T link ifthere are link beat pulses or valid frames present. ThisLNKST pin can be used to drive an LED and/or externalhardware that directly controls the SLEEP pin of thePCnet-32 controller. This configuration effectivelywakes the system when there is any activity on the10BASE-T link. Auto wake mode can be used only if theT-MAU is the selected network port. Link beat pulsesare not transmitted during Auto-wake mode.

The system bus interface will be floated and inactiveduring snooze mode. LDEV and the selected interruptpin will be driven to inactive levels. While in snoozemode, if the PCnet-32 controller is configured for a daisychain (HOLDI and HLDAO or LREQI and LGNTO sig-nals have been selected with the JTAGSEL pin), thenthe daisy chain signal LREQI/HOLDI will be passed di-rectly to LREQ/HOLD and the system arbitration signalLGNT/HLDA will be passed directly to the daisy-chainsignal LGNTO/HLDAO.

If the HOLD output is active when the SLEEP pin is as-serted, then the PCnet-32 controller will wait until theHLDA input is asserted. Then the PCnet-32 controllerwill deassert the HOLD pin and finally, it will internallyenter either the coma or snooze sleep mode.

Before the sleep mode is invoked, the PCnet-32 control-ler will perform an internal S_RESET. This S_RESEToperation will not affect the values of the BCR registers.

The SLEEP pin should not be asserted during powersupply ramp-up. If it is desired that SLEEP be assertedat power up time, then the system must delay the asser-tion of SLEEP until three BCLK cycles after the comple-tion of a valid pin RESET operation.


103Am79C965

Software AccessI/O Resources PCnet-32 Controller I/O Resource MappingThe PCnet-32 controller has several I/O resources.These resources use 32 bytes of I/O space that begin atthe PCnet-32 controller I/O Base Address.

The PCnet-32 controller allows two modes of slave ac-cess. Word I/O mode treats all PCnet-32 controller I/OResources as two-byte entities spaced at two-byte ad-dress intervals. Double Word I/O mode treats allPCnet-32 controller I/O Resources as four-byte entitiesspaced at four-byte address intervals. The selectionof WIO or DWIO mode is accomplished by one oftwo ways:

1) H_RESET function.

The PCnet-32 controller I/O mode setting will defaultto WIO after H_RESET (i.e. DWIO =0).

2) Automatic determination of DWIO mode due todoubleword I/O write access to offset 10h.

DWIO is automatically programmed as active when thesystem attempts a double word write access to offset10h of the PCnet-32 controller I/O space. Note that thisspace corresponds to RDP, regardless of whetherDWIO or WIO mode has been programmed. The powerup H_RESET value of DWIO will be ZERO, and thisvalue will be maintained until a double word access isperformed to PCnet-32 controller I/O space.

Therefore, if DWIO mode is desired, it is imperative thatthe first access to the PCnet-32 controller be a doubleword write access to offset 10h.

Alternatively, if DWIO mode is not desired, then it is im-perative that the software never executes a double wordwrite access to offset 10h of the PCnet-32 controller I/Ospace.

Once the DWIO bit has been set to a ONE, only aH_RESET can reset it to a ZERO.

The DWIO mode setting is unaffected by S_RESET orthe STOP bit.

WIO I/O Resource MapWhen the PCnet-32 controller I/O space is mapped asWord I/O, then the resources that are allotted to thePCnet-32 controller occur on word boundaries that areoffset from the PCnet-32 controller I/O Base Address asshown in Table 32.

Table 32. Word I/O Mapping

Offset No. of (Hex) Bytes Register

0 2 Address PROM

2 2 Address PROM

4 2 Address PROM

6 2 Address PROM

8 2 Address PROM

A 2 Address PROM

C 2 Address PROM

E 2 Address PROM

10 2 RDP

12 2 RAP (shared by RDP and BDP)

14 2 Reset Register

16 2 BDP

18 2 Vendor Specific Word

1A 2 Reserved

1C 2 Reserved

1E 2 Reserved

When PCnet-32 controller I/O space is Word mapped,all I/O resources fall on word boundaries and all I/O re-sources are word quantities. However, while in Word I/Omode, address PROM accesses may also be accessedas individual bytes on byte addresses.

Attempts to write to any PCnet-32 controller I/O re-sources (except to offset 10h, RDP) as 32 bitquantities while in Word I/O mode are illegal and maycause unexpected reprogramming of the PCnet-32 con-troller control registers. Attempts to read from anyPCnet-32 controller I/O resources as 32 bit quantitieswhile in Word I/O mode are illegal and will yieldundefined values.

An attempt to write to offset 10H (RDP) as a 32 bit quan-tity while in Word I/O mode will cause the PCnet-32 con-troller to exit WIO mode and immediately thereafter, toenter DWIO mode.

Accesses to non-word address boundaries are not al-lowed while in WIO mode, with the exception of the


104 Am79C965

APROM locations. The PCnet-32 controller may or maynot produce an LDEV and a RDY signal in response tosuch accesses, but data will be undefined.

Accesses of non-word quantities to any I/O resource arenot allowed while in WIO mode, with the exception ofbyte reads from the APROM locations. PCnet-32 con-troller may or may not produce an LDEV and will notproduce a RDY signal in response to such accesses,but data will be undefined.

The Vendor Specific Word (VSW) is not implemented bythe PCnet-32 controller. This particular I/O address isreserved for customer use and will not be used by futureAMD Ethernet controller products. If more than oneVendor Specific Word is needed, it is suggested that theVSW location should be divided into a VSW RegisterAddress Pointer (VSWRAP) at one location (e.g.VSWRAP at byte location 18h) and a VSW Data Port(VSWDP) at the other location (e.g. VSWDP at byte lo-cation 19h). Alternatively, the system may capture RAPdata accesses in parallel with the PCnet-32 controllerand therefore share the PCnet-32 controller RAP to al-low expanded VSW space. PCnet-32 controller will notrespond to access to the VSW I/O address.

DWIO I/O Resource MapWhen the PCnet-32 controller I/O space is mapped asDouble Word I/O, then all of the resources that are allot-ted to the PCnet-32 controller occur on double wordboundaries that are offset from the PCnet-32 controllerI/O Base Address as shown in Table 33.

Table 33. Double Word I/O Mapping

Offset No. of (Hex) Bytes Register

0 4 Address PROM

4 4 Address PROM

8 4 Address PROM

C 4 Address PROM

10 4 RDP

14 4 RAP (shared by RDP and BDP)

18 4 Reset Register

1C 4 BDP

When PCnet-32 controller I/O space is Double Wordmapped, all I/O resources fall on double word bounda-ries. Address PROM resources are double word quanti-ties in DWIO mode. RDP, RAP and BDP contain onlytwo bytes of valid data. The other two bytes of theseresources are reserved for future use. The reservedbits must be written as zeros, and when read, are con-sidered undefined.

Accesses to non-double word address boundaries arenot allowed while in DWIO mode. The PCnet-32 control-ler may or may not produce an LDEV and a RDY signal

in response to such accesses, but data will beundefined.

Accesses of less than 4 bytes to any I/O resource arenot allowed while in DWIO mode (i.e. PCnet-32 control-ler will not respond to such accesses. PCnet-32 control-ler will not produce an LDEV and a RDY signal inresponse to such accesses), but data will be undefined.A double word write access to the RDP offset of 10h willautomatically program DWIO mode.

Note that in all cases when I/O resource width is definedas 32 bits, the upper 16 bits of the I/O resource is re-served and written as ZEROs and read as undefined,except for the APROM locations and CSR88.

DWIO mode is exited by asserting the RESET pin. As-sertion of S_RESET or setting the STOP bit of CSR0 willhave no effect on the DWIO mode setting.

I/O Space CommentsThe following statements apply to both WIO and DWIOmapping:

The RAP is shared by the RDP and the BDP.

The PCnet-32 controller does not respond to any ad-dresses outside of the offset range 0h-17h whenDWIO = 0 or 0h-1F when DWIO = 1. I/O offsets 18hthrough 1Fh are not used by the PCnet-32 controllerwhen programmed for DWIO = 0 mode. Locations 1Ahthrough 1Fh are reserved for future AMD use and there-fore should not be implemented by the user if upwardcompatibility to future AMD devices is desired.

Note that Address PROM accesses do not directly ac-cess the EEPROM, but are redirected to a set of shadowregisters on board the PCnet-32 controller that contain acopy of the EEPROM contents that was obtained duringthe automatic EEPROM read operation that follows theRESET operation.

PCnet-32 Controller I/O Base AddressThe I/O Base Address Registers (BCR16 and BCR17)will reflect the current value of the base of the PCnet-32controller I/O address space. BCR16 contains the lower16 bits of the 32-bit I/O base address for the PCnet-32controller. BCR17 contains the upper 16 bits of the32-bit I/O base address for the PCnet-32 controller. Thisset of registers is both readable and writeable by thehost. The value contained in these registers is affectedthrough three means:

1. Immediately following the H_RESET operation, theI/O Base Address will be determined by theEEPROM read operation. During this operation, theI/O Base Address register will become programmedwith the value of the I/O Base Address field of theEEPROM.

2. If no EEPROM exists, or if an error is detected in theEEPROM data, then the PCnet-32 controller will en-ter Software Relocatable Mode . While in thismode, the PCnet-32 controller will not respond toany I/O accesses directly. However, the PCnet-32


105Am79C965

controller will snoop accesses on the system bus.When the PCnet-32 controller detects a specificsequence of four write accesses to I/O address378h, then the PCnet-32 controller will assume thatthe software is attempting to relocate the PCnet-32controller. On eight subsequent write accesses toI/O address 378h, the PCnet-32 controller will acceptthe data on the bus as a new I/O Base Address andother programming information, and it will leaveSoftware Relocatable Mode. At this point, thePCnet-32 controller will begin responding to I/O ac-cesses directly.

While the PCnet-32 controller is in softwarerelocatable mode, if the LED2 pin is pulled LOW,then the SRMA24 mode is entered and only thelower 24 bits of address are matched to 378h.

3. The I/O Base Address Registers may be directly writ-ten to, provided that the PCnet-32 controller is notcurrently in the Software Relocatable Mode.

Software Relocation of I/O ResourcesIn order to allow for jumperless Ethernet implementa-tions, the I/O Base Address register value will be auto-matically altered by the PCnet-32 controller during anEEPROM read operation. In this case, the value of theI/O Base Address for the PCnet-32 controller will be di-rectly dependent upon the value of the BCR16 andBCR17 fields that are stored in the EEPROM. If noEEPROM exists and an EEPROM read is attempted,then the PCnet-32 controller will enter SoftwareRelocatable Mode.

Software Relocatable ModeWhile in Software Relocatable Mode, the PCnet-32 con-troller will not respond to any access on the system bus.However, the PCnet-32 controller will snoop any I/Owrite accesses that may be present. The PCnet-32 con-troller will watch for a specific sequence of accesses inorder to determine a value for the I/O Base AddressRegisters. Specifically, the PCnet-32 controller will waitfor a sequence of 12 uninterrupted byte-write accessesto I/O address 378h.

The 12 byte-write accesses must occur without inter-vening I/O accesses to other locations, and they mustcontain the data in the order shown in Table 34.

BE0 is required to be active during all SoftwareRelocatable Mode snoop accesses. BE3–BE1 mayhave any value during Software Relocatable Modesnoop accesses.

Table 34. I/O Base Address Write Sequence in SRM

ASCIII/O Address D[7:0]* Inter–

Access No. (Hex) (Hex) pretation

1 0000 0378 41 A

2 0000 0378 4D M

3 0000 0378 44 D

4 0000 0378 01 NA

5 0000 0378 IOBASEL[7:0] NA

6 0000 0378 IOBASEL[15:8] NA

7 0000 0378 IOBASEU[7:0] NA

8 0000 0378 IOBASEU[15:8] NA

9 0000 0378 BCR2[7:0] NA

10 0000 0378 BCR2[15:8] NA

11 0000 0378 BCR21[7:0] NA

12 0000 0378 BCR21[15:8] NA

*Note that D[31:8] are don’t care, since the accesses are required to one byte in width.

Immediately following the 12th write access in the se-quence, the PCnet-32 controller will leave SoftwareRelocatable Mode, and it will then respond to I/O ac-cesses to the 32 bytes of I/O space that begins at the I/OBase Address location.

Note that in Figure 33 (Software Relocatable ModeSnoop Accesses), the data that is accepted by thePCnet-32 controller will always be the data that is pre-sented during the first T2 cycle, regardless of the state ofthe RDYRTN input.

Since the PCnet-32 controller will not respond to theSoftware Relocatable Mode snoop accesses, someother device must drive the RDYRTN signal duringthese accesses. In a typical PC environment, these I/Oaccesses will be directed toward the data port of a paral-lel port. Therefore, the RDYRTN will typically be gener-ated by the parallel port controller. In systems in whichthe parallel port device does not exist, or is at a differentlocation, the 378h accesses will go unclaimed by anydevice on the local bus or on the expansion bus. In thiscase, the chipset will typically terminate the access byproviding the RDYRTN signal after some access-time-out counter has elapsed.


106 Am79C965

ADS

T1

BCLK

T2 T2 T1 T2 T1 T2

A4–A31,M/IO, D/C

A2–A3,BE1–BE3

RDYRTN

W/R

BRDY

BLAST

D8–D31

T2 T2 Ti T1

Don't Care

I/O Address 378h I/O Address 378h I/O Address 378h I/O Address 378h

T2

PCnet-32 controllerlatches snoop data

on this edge


on this edge


on this edge

BE0

I/O Address 378h I/O Address 378h I/O Address 378h

D0–D7 SRMData

SRMData

SRMData

I/O Address 378h

18219B-40Figure 33. Software Relocatable Mode Snoop Cycles

The I/O Base Address register value may be altered by adirect write to BCR16 and BCR17 by the host. Slaveaccesses to the PCnet-32 controller should not be per-formed until both BCR16 and BCR17 have been writtenwith new values. An intermediate I/O Base address willbe created when only one of the two registers has beenwritten. Therefore, this method of I/O Base address re-assignment is not recommended.

I/O Register AccessAll I/O resources are accessed with similar I/O buscycles.

I/O accesses to the PCnet-32 controller begin with avalid ADS strobe and an address on the A[31:2] linesthat falls within the I/O space of the PCnet-32 controller.The PCnet-32 controller I/O space will be determined by

the I/O Base Address Registers. EEPROM read opera-tions will determine the value of the I/O Base AddressRegisters.

The PCnet-32 controller will respond to an access to itsI/O space by asserting the LDEV signal and eventually,by asserting the RDY signal.

Typical I/O access times are 6 or 7 BCLK periods. Theexact number of clock cycles for any particular accesswill depend upon the relative phases of the signal on theBCLK pin and the internal clock that is used to drive thePCnet-32 controller buffer management unit. Since thePCnet-32 controller buffer management unit operateson a clock that is a ÷2 version of the interface clock, it ispossible for the buffer management unit to introduceone or more BCLK wait delays to allow for


107Am79C965

synchronization of the two state machines before pro-ceeding with the access. The PCnet-32 buffer manage-ment unit uses BCLK ÷ 2, so the maximum number ofBCLK cycles needed to synchronize the BIU and buffermanagement units is one BCLK period.

APROM AccessThe APROM space is a convenient place to store thevalue of the IEEE station address. This space is auto-matically loaded from the serial EEPROM, if anEEPROM is present. Its contents have no effect on theoperation of the controller. The software must copy thestation address from the APROM space to the Initializa-tion Block or to CSR12–CSR14 in order for the receiverto accept unicast frames directed to this station.

When programmed for WIO mode, any byte or word ad-dress from an offset of 0h to an offset of Fh may be read.An appropriate byte or word of APROM contents will bedelivered by the PCnet-32 controller in response to ac-cesses that fall within the APROM range of 0h to Fh.

When programmed for DWIO mode, only double wordaddresses from an offset of 0h to an offset of Fh may beread. An appropriate double word of APROM contentswill be delivered in response to accesses that fall withinthe APROM range of 0h to Fh.

Reads of non-double word quantities are not allowed inDWIO mode, even though such an access may be prop-erly aligned to a double word address boundary.

Write access to any of the APROM locations is allowed,but only 4 bytes on doubleword boundaries in DWIOmode or 2 bytes on word boundaries in WIO mode. TheIESRWE bit (see BCR2) must be set in order to enablesuch a write. Only the PCnet-32 controller on-boardIEEE Shadow registers are modified by writes toAPROM locations. The EEPROM is unaffected bywrites to APROM locations.

Note that the APROM locations occupy 16 bytes ofspace, yet the IEEE station address requirement is for 6bytes. The 6 bytes of IEEE station address occupy thefirst 6 locations of the APROM space. The next six bytesare reserved. Bytes 12 and 13 should match the value ofthe checksum of bytes 1 through 11 and 14 and 15.Bytes 14 and 15 should each be ASCII “W” (57 h) if com-patibility to AMD driver software is desired.

RDP Access (CSR Register Space)RDP = Register Data Port. The RDP is used with theRAP to gain access to any of the PCnet-32 controllerCSR locations.

Access to any of the CSR locations of the PCnet-32 con-troller is performed through the PCnet-32 controller’sRegister Data Port (RDP). In order to access a particularCSR location, the Register Address Port (RAP) shouldfirst be written with the appropriate CSR address. TheRDP now points to the selected CSR. A read of the RDPwill yield the selected CSR’s data. A write to the RDP willwrite to the selected CSR.

When programmed for WIO mode, the RDP has a widthof 16 bits, hence, all CSR locations have 16 bits of width.Note that when accessing RDP, the upper two bytes ofthe data bus will be undefined since the byte masks willnot be active for those bytes.

If DWIO mode has been invoked, then the RDP has awidth of 32 bits, hence, all CSR locations have 32 bits ofwidth and the upper two bytes of the data bus will beactive, as indicated by the byte mask. In this case, notethat the upper 16 bits of all CSR locations (exceptCSR88) are reserved and written as zeros and read asundefined values. Therefore, during RDP write opera-tions in DWIO mode, the upper 16 bits of all CSR loca-tions should be written as ZEROs.

RAP AccessRAP = Register Address Port. The RAP is used with theRDP and with the BDP to gain access to any of the CSRand BCR register locations, respectively. The RAP con-tains the address pointer that will be used by an accessto either the RDP or BDP. Therefore, it is necessary toset the RAP value before accessing a specific CSR orBCR location. Once the RAP has been written with avalue, the RAP value remains unchanged until anotherRAP write occurs, or until an H_RESET or S_RESEToccurs. RAP is set to all zeros when an H_RESET orS_RESET occurs. RAP is unaffected by the STOP bit.

When programmed for WIO mode, the RAP has a widthof 16 bits. Note that when accessing RAP, the lower twobytes of the data bus will be undefined since the bytemasks will not be active for those bytes

When programmed for DWIO mode, the RAP has awidth of 32 bits. In DWIO mode, the upper 16 bits of theRAP are reserved and written as zeros and read as un-defined. These bits should be written as zeros.

BDP Access (BCR Register Space)BDP = Bus Configuration Register Data Port. The BDPis used with the RAP to gain access to any of thePCnet-32 controller BCR locations.

Access to any of the BCR locations of the PCnet-32 con-troller is performed through the PCnet-32 controller’sBCR Data Port (BDP ). In order to access a particularBCR location, the Register Address Port (RAP) shouldfirst be written with the appropriate BCR address. TheBDP now points to the selected BCR. A read of the BDPwill yield the selected BCR ’s data. A write to the BDPwill write to the selected BCR.

When programmed for WIO mode, the BDP has a widthof 16 bits, hence, all BCR locations have 16 bits of widthin WIO mode. Note that when operating in WIO mode,the upper two bytes of the data bus will be undefinedsince the byte mask will not be active for those bytes.

If DWIO mode has been invoked, then the BDP has awidth of 32 bits, hence, all BCR locations have 32 bits ofwidth and the upper two bytes of the data bus will beactive, as indicated by the byte mask. In this case, note


108 Am79C965

that the upper 16 bits of all BCR locations are reservedand written as zeros and read as undefined. Therefore,during BDP write operations in DWIO mode, the upper16 bits of all BCR locations should be written as zeros.

Reset Register (S_RESET)A read of the reset register creates an internalS_RESET pulse in the PCnet-32 controller. This readaccess cycle must be 16 bits wide in WIO mode and 32bits wide in DWIO mode. The internal S_RESET pulsethat is generated by this access is different from both theassertion of the hardware RESET pin (H_RESET) andfrom the assertion of the software STOP bit. Specifi-cally, the Reset register’s S_RESET will be the equiva-lent of the assertion of the RESET pin (H_RESET)assertion for all CSR locations, but S_RESET will haveno effect at all on the BCR locations, and S_RESET willnot cause a deassertion of the HOLD pin.

The NE2100 LANCE based family of Ethernet cards re-quires that a write access to the reset register followseach read access to the reset register. The PCnet-32controller does not have a similar requirement. The writeaccess is not required but it does not have any harmfuleffects.

Write accesses to the reset register will have no effecton the PCnet-32 controller.

Note that a read of the Reset register will take longerthan the normal I/O access time of the PCnet-32 control-ler. This is because an internal S_RESET pulse will begenerated due to this access, and the access will not beallowed to complete on the system bus until the internalS_RESET operation has been completed. This is toavoid the problem of allowing a new I/O access to pro-ceed while the S_RESET operation has not yet com-pleted, which would result in erroneous data being

returned by (or written into) the PCnet-32 controller. Thelength of a read of the Reset register can be as long as128 BCLK cycles when Am386 mode has been selectedand 64 BCLK cycles when Am486 mode or VESA VL-Bus mode has been selected.

Note that a read of the Reset register will not cause adeassertion of the HOLD signal, if it happens to be ac-tive at the time of the read to the reset register. TheHOLD signal will remain active until the HLDA signal issynchronously sampled as asserted. Following the readof the RESET register, on the next clock cycle after theHLDA signal is synchronously sampled as asserted, thePCnet-32 controller will deassert the HOLD signal). Nobus master accesses will have been performed duringthis brief bus ownership period.

Note that this behavior differs from that which occurs fol-lowing the assertion of a minimum-width pulse on theRESET pin (H_RESET). A RESET pin assertion willcause the HOLD signal to deassert within six clock cy-cles following the assertion. In the RESET pin case, thePCnet-32 controller will not wait for the assertion of theHLDA signal before deasserting the HOLD signal.

Vendor Specific WordThis I/O offset is reserved for use by the system de-signer. The PCnet-32 controller will not respond to ac-cesses directed toward this offset.

Reserved I/O SpaceThese locations are reserved for future use by AMD.The PCnet-32 controller does not respond to accessesdirected toward these locations, but future AMD prod-ucts that are intended to be upward compatible with thePCnet-32 controller may decode accesses to these lo-cations. Therefore, the system designer may not utilizethese I/O locations.


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Hardware AccessPCnet-32 Controller Master AccessesThe particular signals involved in a PCnet-32 controllerbus master transfer depends upon the bus mode thathas been selected. There are two bus modes to choosefrom. They are:

Am486 32-bit mode

VESA VL-Bus mode

Complete descriptions of the signals involved in busmaster transactions for each mode may be found in thepin description section of this document. Timing dia-grams for master accesses may be found in the blockdescription section for the Bus Interface Unit. This sec-tion simply lists the types of master accesses that will beperformed by the PCnet-32 controller with respect todata size and address information.

The PCnet-32 controller will support master accessesonly to 32-bit peripherals in Am486 environments. ThePCnet-32 controller does not support master accessesto 16-bit peripherals in the 486 local bus mode.

The PCnet-32 controller will support master accesses toeither 32-bit or 16-bit peripherals in VESA VL-Busmode. Support of master accesses to 16-bit peripheralsin VESA VL-Bus mode is provided through the LBS16input pin.

The PCnet-32 controller is not compatible with 8-bit sys-tems, since there is no mode that supports PCnet-32controller accesses to 8-bit peripherals.

Table 35 describes all possible bus master accessesthat the PCnet-32 controller will perform. The right-most column lists all operations that may execute thegiven access.

Table 35. Master Accesses

BE3–Access R/W BE0 Possible Instance

4-Byte Read RD 0000 Descriptor Read or Initialization BlockRead or Transmit Data Buffer Read

4-Byte Write WR 0000 Descriptor Write or Receive Data Buffer Write

3-Byte Write WR 1000 Receive Data Buffer Write



2-Byte Write WR 1001* Receive Data Buffer Write





1-Byte Write WR 0111 Descriptor Write or Receive Data Buffer Write

*Cases marked with an asterisk represent extreme bound-ary conditions that are the result of programming one- andtwo-byte buffer sizes, and therefore will not be seen undernormal circumstances.


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Note that all PCnet-32 controller master read operationswill always activate all byte enables. (Note the excep-tion, when LBS16 has been asserted in VL-Bus mode,requiring a second access. In all LBS16 cases, the sec-ond access (if required) will have BE1 and BE0 dis-abled.). Therefore, no one-, two- or three-byte readoperations are indicated in the table.

In the instance where a transmit buffer pointer addressbegins on a non-doubleword boundary, the pointer willbe truncated to the next double word boundary addressthat lies below the given pointer address and the firstread access from the transmit buffer will be indicated onthe byte enable signals as a four-byte read from this ad-dress. Any data from byte lanes that lie outside of theboundary indicated by the buffer pointer will be dis-carded inside of the PCnet-32 controller. Similarly, if theend of a transmit buffer occurs on a non-doublewordboundary, then all byte lanes will be indicated as activeby the byte enable signals, and any data from byte lanesthat lie outside of the boundary indicated by the bufferpointer will be discarded inside of the PCnet-32controller.

Slave Access to I/O ResourcesThe PCnet-32 controller is a 32-bit peripheral deviceon the system bus. However, the width of individual

software resources on board the PCnet-32 controllermay be either 16-bits or 32-bits. The PCnet-32 controllerI/O resource widths are determined by the value ofthe DWIO bit (BCR 18, bit 7) as indicated in Table 36.

Note that when I/O resource width is defined as 32 bits(DWIO mode), the upper 16 bits of the I/O resource isreserved and written as ZEROs and read as undefined,except for the APROM locations. The APROM locationsare the only I/O resources for which all 32 bits will havedefined values. However, this is true only when thePCnet-32 controller is in DWIO mode.

Configuring the PCnet-32 controller for DWIO mode isaccomplished whenever there is any attempt to performa 32-bit write access to the RDP location (offset 10h).See the DWIO section for more details.

Table 37 describes all possible bus slave accesses thatmay be directed toward the PCnet-32 controller. (I.e. thePCnet-32 controller is the slave device during the trans-fer.) The four byte columns (D31–D24, D23–D16,D15–D8, D7–D0) indicate the value on the data bus dur-ing the access.

Table 36. I/O Resource Access

PCnet-32 Controller DWIO Setting I/O Resource Width Example Application

DWIO = 0 16-bit Existing PCnet-ISA driver that assumes16-bit I/O mapping and 16-bit resource widths

DWIO = 1 32-bit New drivers written specifically for thePCnet-32 controller


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Table 37. Slave Accesses

R/W BE3–BE0 D31–D24 D23–D16 D15–D8 D7–D0 Comments

RD 0000 Data Data Data Data Double word access to double wordaddress, e.g. 300, 30C, 310 (DWIO mode only)

RD 1100 Undef Undef Data Data WIO Mode Only: Word access to even word address, e.g. 300, 30C, 310

RD 0011 Data Data Copy Copy WIO Mode Only: Word access to oddword address, e.g. 302, 30E, 312

RD 1110 Undef Undef Undef Data WIO Mode APROM Read Only: Byte access to lower byte of even word address, e.g. 300, 304

RD 1101 Undef Undef Data Undef WIO Mode APROM Read Only: Byte access to upper byte of even word address, e.g. 301, 305

RD 1011 Undef Data Undef Copy WIO Mode APROM Read Only: Byte access to lower byte of odd word address, e.g. 302, 306

RD 0111 Data Undef Copy Undef WIO Mode APROM Read Only: Byte access to upper byte of odd word address, e.g. 303, 307

WR 0000 Data Data Data Data Double word access to double word address, e.g. 300, 30C, 310 (DWIO mode only)

WR 1100 Undef Undef Data Data WIO Mode Only: Word access to even word address, e.g. 300, 30C, 310

WR 0011 Data Data Undef Undef WIO Mode Only: Word access to odd word address, e.g. 302, 30E, 312

Data = indicates the position of the active bytes.

Copy = indicates the positions of copies of the active bytes.

Undef = indicates byte locations that are undefined during the transfer.

EEPROM Microwire AccessThe PCnet-32 controller contains a built-in capability forreading and writing to an external EEPROM. This built-in capability consists of a microwire interface for directconnection to a microwire compatible EEPROM, anautomatic EEPROM read feature, and a user-program-mable register that allows direct access to the microwireinterface pins.

Automatic EEPROM Read OperationShortly after the deassertion of the RESET pin, thePCnet-32 controller will read the contents of theEEPROM that is attached to the microwire inter-face. The automatic EEPROM read begins with EECSbeing asserted approximately 2.5 EESK periods 2.5

t42( )following the deassertion of the RESET pin. Because ofthis automatic-read capability of the PCnet-32 control-ler, an EEPROM can be used to program many of thefeatures of the PCnet-32 controller at power-up, allow-ing system-dependent configuration information to bestored in the hardware, instead of inside of operatingcode. PCnet-32 controller interrupt pins will be floatedduring H_RESET and will remain floated until either the

EEPROM has been successfully read, or, following anEEPROM read failure, a Software Relocatable Modesequence has been successfully executed.

If an EEPROM exists on the microwire interface, thePCnet-32 controller will read the EEPROM contents atthe end of the H_RESET operation. The EEPROM con-tents will be serially shifted into a temporary register andthen sent to various register locations on board thePCnet-32 controller. System bus interaction will not oc-cur during the EEPROM read operation after H_RE-SET, since H_RESET will put the PCnet-32 controllerinto a state that will not recognize any I/O accesses andthe PCnet-32 controller will not yet be at an operatingpoint that requires it to request the bus for busmastering.

Thirty-four bytes of the EEPROM are set aside forPCnet-32 configuration programming and 2 bytes of theEEPROM are set aside for user programming of logicthat is external to the PCnet-32 controller and may ormay not be pertinent to the operation of the PCnet-32controller within the system. The user may gain accessto the EEPROM data by snooping the PCnet-32


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controller automatic read operation. Logic may be at-tached to the EEPROM interface to snoop the entireEEPROM read operation using the microwire signalsdirectly, or a simpler scheme may be invoked by takingadvantage of an additional signal provided by thePCnet-32 controller (i.e. the SHFBUSY signal).

A checksum verification is performed on the data that isread from the EEPROM. If the checksum verification ofthe EEPROM data fails, then at the end of the EEPROMread sequence, the PCnet-32 controller will force allEEPROM-programmable register locations back totheir H_RESET default values and then the PCnet-32controller will enter Software Relocatable Mode. The8-bit checksum for the entire 36 bytes of the EEPROMshould be FFh. In the event of a checksum failure, Soft-ware Relocatable Mode is entered (PCnet-32 controllerbegins snooping for a 12-byte sequence) within 1 EESKperiod following the deassertion of EECS 1

t42( ).If the absence of an EEPROM has been signaled by theEESK/LED1/SFBD pin at the time of the automatic readoperation, then the PCnet-32 controller will recognizethis condition and will abort the automatic read opera-tion and reset both the PREAD and PVALID bits inBCR19. At this point, the PCnet-32 controller will enterthe Software Relocatable Mode, and the EEPROM-pro-grammable registers will be assigned their H_RESETdefault values. Software Relocatable Mode is entered(PCnet-32 controller begins snooping for 12-bytesequence) within 2.5 EESK periods 2.5

t42( ) following thedeassertion of the RESET pin when absence of anEEPROM is signalled by the EESK/LEDI SFBD pin.

If the user wishes to modify any of the configuration bitsthat are contained in the EEPROM, then the 7 com-mand, data and status bits of BCR19 can be used towrite to the EEPROM. After writing to the EEPROM, thehost should set the PREAD bit of BCR19. This actionforces a PCnet-32 controller re-read of the EEPROM sothat the new EEPROM contents will be loaded into theEEPROM-programmable registers on board thePCnet-32 controller. (The EEPROM-programmableregisters may also be reprogrammed directly, but onlyinformation that is stored in the EEPROM will be pre-served at system power-down.) When the PREAD bit ofBCR19 is set, it will cause the PCnet-32 controller toignore further accesses on the system interface bus un-til the completion of the EEPROM read operation.

EEPROM Auto-DetectionThe PCnet-32 controller uses the EESK/LED1/SFBDpin to determine if an EEPROM is present in the system.At all rising BCLK edges during the assertion of the RE-SET pin, the PCnet-32 controller will sample the value ofthe EESK/LED1/SFBD pin. If the sampled value is aONE, then the PCnet-32 controller assumes that an

EEPROM is present, and the EEPROM read operationbegins shortly after the RESET pin is deasserted. If thesampled value of EESK/LED1/SFBD is a ZERO, thenthe PCnet-32 controller assumes that an externalpulldown device is holding the EESK/LED1/SFBD pinlow, and therefore, there is no EEPROM in the system.In this case, the PCnet-32 controller will enter SoftwareRelocatable Mode. Note that if the designer creates asystem that contains an LED circuit on the EESK/LED1/SFBD pin but has no EEPROM present, then theEEPROM auto-detection function will incorrectly con-clude that an EEPROM is present in the system. How-ever, this will not pose a problem for the PCnet-32controller, since it will recognize the lack of an EEPROMat the end of the read operation, when the checksumverification fails. At this point, the PCnet-32 controllerwill enter Software Relocatable Mode.

The real intention of the EEPROM auto-detection fea-ture is to allow a user to preempt a “good EEPROM” bytemporarily resistively shorting the EESK/LED1/SFBDpin to ground. This may need to be done if an add-in cardcontaining the PCnet-32 controller and its EEPROM hasbeen programmed in one system and then later movedto a different system without also moving configurationinformation that indicates the I/O Base address of thecard. The card would power up in the second systemwith an unknown I/O Base address if the configurationinformation were not carried with the card to the newsystem. By allowing the EESK/LED1/SFBD pin to betemporarily resistively shorted to ground, the PCnet-32controller is fooled into believing that the EEPROM doesnot exist, and it will enter Software Relocatable Mode.This allows the new system to reconfigure the I/O Baseaddress of the PCnet-32 controller to a location that iscompatible to the parameters of the new system. Thisinformation will then be written into the EEPROM by aconfiguration utility through the EEPROM access port(BCR19), in spite of the fact that the PCnet-32 controllerbelieves that there is no EEPROM. The resistive short toground may now be removed, and the next power-up ofthe system will place the PCnet-32 controller into a I/Olocation that is known by this system. When the PREADbit of BCR19 is set, an EEPROM read operation will beperformed, regardless of the value of the EESK/LED1/SFBD pin. Note that the H_RESET-generatedEEPROM read operation always obeys the EESK/LED1/SFBD indication.

Table 38 indicates the possible combinations of EEDETand the existence of an EEPROM and the resulting op-erations that are possible on the EEPROM microwireinterface. Note that the EEDET value (BCR19, bit 3) isdetermined from EESK/LED1/SFBD pin setting, and itmay be set even though there is no EEPROM present.


113Am79C965

Table 38. Effect of EEDET on EEPROM Operation

EEDET Value EEPROM Result of Automatic EEPROM Read (BCR19[3]) Connected? Result if PREAD is set to ONE Operation Following H_RESET

0 No EEPROM read operation is attempted. First TWO EESK clock cyclesEntire read sequence will occur, are generated, then EEPROMchecksum failure will result, PVALID read operation is aborted and is reset to ZERO. PVALID is reset to ZERO.

0 Yes EEPROM read operation is attempted. First TWO EESK clock cycles are Entire read sequence will occur, generated, then EEPROM read checksum operation will pass, PVALID operation is aborted and PVALID is is set to ONE. reset to ZERO.

1 No EEPROM read operation is attempted. EEPROM read operation is attempted. Entire read sequence will occur, Entire read sequence will occur, checksum failure will result, PVALID checksum failure will result, is reset to ZERO. PVALID is reset to ZERO.

1 Yes EEPROM read operation is attempted. EEPROM read operation is attempted. Entire read sequence will occur, Entire read sequence will occur, checksum operation will pass, PVALID checksum operation will pass, is set to ONE. PVALID is set to ONE.

Systems Without an EEPROMSome systems may be able to save the cost of anEEPROM by storing the ISO 8802-3 (IEEE/ANSI 802.3)station address and other configuration informationsomewhere else in the system. For such a system, a twostep process is required. The first step will get thePCnet-32 controller into its normal operating modewithin the system. The second step will load the IEEEstation address. The designer has several choices:

1) If the LED1 and SFBD functions are not needed inthe system, then the system designer may connectthe EESK/LED1/SFBD pin to a resistive pulldowndevice. This will indicate to the EEPROM auto-de-tection function that no EEPROM is present, and thePCnet-32 controller will use Software RelocatableMode to acquire its I/O Base Address and other con-figuration information (See the section on SoftwareRelocatable Mode).

2) If either of the LED1 or SFBD functions is needed inthe system, then the system designer will connectthe EESK/LED1/SFBD pin to a resistive pullup de-vice and the EEPROM auto-detection function willincorrectly conclude that an EEPROM is present inthe system. However, this will not pose a problem forthe PCnet-32 controller, since it will recognize thelack of an EEPROM at the end of the read operation,when the checksum verification fails. At this point,the PCnet-32 controller into the SoftwareRelocatable Mode to acquire its I/O Base Addressand other configuration information (See the sectionon Software Relocatable Mode).

In either case, following the execution of SoftwareRelocatable Mode, additional information, including theISO 8802-3 (IEEE/ANSI 802.3) station address, may beloaded into the PCnet-32 controller. Note that theIESRWE bit (bit 8 of BCR2) must be set before thePCnet-32 controller will accept writes to the APROM off-sets within the PCnet-32 controller I/O resources map.Startup code in the system BIOS can perform the Soft-ware Relocatable Mode accesses, the IESRWE bitwrite, and the APROM writes.

If compatibility to existing driver code is desired, then itis not recommended that the ISO 8802-3 (IEEE/ANSI802.3) station address be loaded into the InitializationBlock structure in memory instead of the APROM loca-tions, since existing code typically expects to find theISO 8802-3 (IEEE/ANSI 802.3) station address at theAPROM offsets from the PCnet-32 controller I/O BaseAddress.

Direct Access to the Microwire InterfaceThe user may directly access the microwire port throughthe EEPROM register, BCR19. This register containsbits that can be used to control the microwire interfacepins. By performing an appropriate sequence of I/O ac-cesses to BCR19, the user can effectively write to andread from the EEPROM. This feature may be used by asystem configuration utility to program hardware con-figuration information into the EEPROM.


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EEPROM-Programmable RegistersThe following registers contain configuration informa-tion that will be programmed automatically during theEEPROM read operation:

1) I/O offsets 0h–Fh Address PROM locations

2) BCR2 Miscellaneous Configuration register

3) BCR16 I/O Base Address Lower

4) BCR17 I/O Base Address Upper

5) BCR18 Burst Size and Bus Control Register

6) BCR21 Interrupt Control Register

If the PREAD bit (BCR19) is reset to ZERO and thePVALID bit (BCR19) is reset to ZERO, then the

EEPROM read has experienced a failure and the con-tents of the EEPROM programmable register will be setto default H_RESET values. At this point, the PCnet-32controller will enter Software Relocatable Mode.

Note that accesses to the Address PROM I/O locationsdo not directly access the Address EEPROM itself. In-stead, these accesses are routed to a set of “shadow”registers on board the PCnet-32 controller that areloaded with a copy of the EEPROM contents during theautomatic read operation that immediately follows theH_RESET operation.

EEPROM MAPThe automatic EEPROM read operation will access 18words (i.e. 36 bytes) of the EEPROM. The format of theEEPROM contents is shown in Table 39, beginning withthe byte that resides at the lowest EEPROM address.

Table 39. EEPROM Content

EEPROMWord Byte MSB Byte LSBAddr Addr (Most Significant Byte) Addr (Lease Significant Byte)

0 1 2nd byte of the ISO 8802-3 0 First byte of the ISO 8802-3 (Lowest (IEEE/ANSI 802.3) station physical (IEEE/ANSI 802.3) station physical Address) address for this node address for this node, where first byte

refers to the first byte to appear on the802.3 medium

1 3 4th byte of the node address 2 3rd byte of the node address

2 5 6th byte of the node address 4 5th byte of the node address

3 7 Reserved location: must be 00h 6 Reserved location: must be 00h

4 9 Hardware ID: must be 10h if 8 Driver IRQ: Must be programmed to thecompatibility to AMD drivers is desired system IRQ channel number being used

if AMD drivers are used.

5 B User programmable space A User programmable space

6 D MSB of two-byte checksum, which is the C LSB of two-byte checksum, which issum of bytes 0-B and bytes E and F the sum of bytes 0-B and bytes E and F

7 F Must be ASCII “W” (57h) if compatibility E Must be ASCII “W” (57h) if compatibility to AMD driver software is desired to AMD driver software is desired

8 11 BCR16[15:8] (I/O Base Address Lower) 10 BCR16[7:0] (I/O Base Address Lower)

9 13 BCR17[15:8] (I/O Base Address Upper) 12 BCR17[7:0] (I/O Base Address Upper)

A 15 BCR18[15:8] (Burst Size and Bus Control) 14 BCR18[7:0] (Burst Size and Bus Control)

B 17 BCR2[15:8] (Miscellaneous configuration) 16 BCR2[7:0] (Miscellaneous configuration)

C 19 BCR21[15:8] (Interrupt Control) 18 BCR21[7:0] (Interrupt Control)

D 1B Reserved location: must be 00h 1A Reserved location: must be 00h

E 1D Reserved location: must be 00h 1C Reserved location: must be 00h

F 1F checksum adjust byte for the first 1E Reserved location: must be 00h36 bytes of the EEPROM contents; checksum of the first 36 bytes of the EEPROM should total to FFh

10 21 Reserved location: must be 00h 20 Reserved location: must be 00h

11 23 User programmable byte locations 22 User programmable byte locations

EEPROM Contents


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Note that the first bit out of any WORD location in theEEPROM is treated as the MSB of the register that is be-ing programmed. For example, the first bit out ofEEPROM WORD location 08h will be written intoBCR16[15], the second bit out of EEPROM WORD loca-tion 08h will be written into BCR16[14], etc.

There are two checksum locations within the EEPROM.The first is required for the EEPROM address. Thischecksum will be used by AMD driver software to verifythat the ISO 8802-3 (IEEE/ANSI 802.3) station addresshas not been corrupted. The value of bytes C and Dshould match the 16-bit sum of bytes 0 through B and Eand F. The second checksum location “byte 1F ” is not achecksum total, but is, instead, a checksum adjustment.The value of this byte should be such that the total 8-bitchecksum for the entire 36 bytes of EEPROM dataequals the value FFh. The checksum adjust byte isneeded by the PCnet-32 controller in order to verify thatthe EEPROM contents have not been corrupted.

Byte address 8h of the EEPROM map contains thedriver IRQ field. The content of this field is used by AMDdrivers to program the interrupt channel being used bythe PCnet-32. Note that the PCnet-32 interrupt pin se-lection is NOT effected by this field. The interrupt pinselection is controlled only by the appropriate bits inBCR21. The system interrupt channel associated witheach of the PCnet-32 INTR pins is application-depend-ent. AMD drivers utilize byte location 8h of the EEPROMto resolve this dependency.

EEPROM-Programming of System LogicWhen the user has shareable hardware resources in thesystem and wishes to have these resources pro-grammed at power up, the user may desire to take ad-vantage of the extra space in the EEPROM that is usedto configure the PCnet-32 controller in order to store theadditional configuration information. The PCnet-32 con-troller provides a convenient means of access for theuser who wishes to utilize this space. The schematic inFigure 34 illustrates an example of logic that is used togenerate static control signals for some programmablefeatures of the system, where the programminginformation is stored on board the PCnet-32 controller’sEEPROM and the logic is to be automatically pro-grammed after RESET.

Note that the EECS signal pulses low during theEEPROM read operation and is therefore unsuitable foruse as a gate signal for the programmable logic outputs.PCnet-32 controller provides an additional signal,SHFBUSY, which will remain active HIGH during the en-tire EEPROM read operation. This signal will thereforebe suitable for use as the gate of the programmablelogic outputs as shown in the diagram. Note that sincemost of the EEPROM microwire interface signals aremultiplexed with other PCnet-32 controller functions, itis necessary for the SHFBUSY pin to enable the shiftpath of the programmable logic, otherwise the shift pathwould become active when the EESK and EEDO func-tions were operating as their alternate functions.

RESET

OUT1 OUT2 OUT3

FFRFFRFFR

R

DENCK

Q...up to 16 bits

PCnet-32Controller

EEDI

RESET

EEDO

EECS

EESK

SHFBUSY

EEPROM(93LC46)

EEDI

RESET

EEDO

EECS

EESK

R

DENCK

Q

R

DENCK

Q

18219B-41

Figure 34. Programming System Logic Through the PCnet-32 EEPROM Read Operation


116 Am79C965

SHFBUSY will be HIGH for the entire EEPROM readoperation, and therefore all EEPROM contents will havebeen shifted through the external logic before it settleson its final, programmed value. If the EEPROM check-sum verification fails, then the EEPROM contents areassumed to be invalid, and the SHFBUSY signal will re-main HIGH after the completion of the EEPROM readoperation. This action will prevent incorrect system logicvalues from being driven into the system. If theEEPROM checksum verification passes, then theEEPROM contents are assumed to be valid, and theSHFBUSY signal will return to a LOW state after thecompletion of the EEPROM read operation.

Transmit OperationThe transmit operation and features of the PCnet-32controller are controlled by programmable options.

Transmit Function ProgrammingAutomatic transmit features such as retry on collision,FCS generation/transmission, and pad field insertioncan all be programmed to provide flexibility in the(re-)transmission of messages.

Disable retry on collision (DRTY) is controlled by theDRTY bit of the Mode register (CSR15) in the initializa-tion block.

Automatic pad field insertion is controlled by theAPAD_XMT bit in CSR4. If APAD_XMT is set, auto-matic pad field insertion is enabled, the DXMTFCS fea-ture is over-ridden, and the 4 byte FCS will be added tothe transmitted frame unconditionally. If APAD_XMT isclear, no pad field insertion will take place and runt pack-et transmission is possible.

The disable FCS generation/transmission feature canbe programmed dynamically on a frame by frame basis.See the ADD_FCS description of TMD1.

Transmit FIFO Watermark (XMTFW in CSR80) sets thepoint at which the BMU requests more data from thetransmit buffers for the FIFO. A minimum of “XMTFW”empty spaces must be available in the transmit FIFObefore the BMU will request the system bus in order totransfer transmit packet data into the transmit FIFO.

Transmit Start Point (XMTSP in CSR80) sets the pointwhen the transmitter actually attempts to transmit a

frame onto the media. A minimum of “XMTSP” bytesmust be written to the transmit FIFO for the currentframe before transmission of the current frame will be-gin. (When automatically padded packets are beingsent, it is conceivable that the XMTSP is not reachedwhen all of the data has been transferred to the FIFO. Inthis case, the transmission will begin when all of thepacket data has been placed into the transmit FIFO.)

When the entire frame is in the FIFO, attempts at trans-mission of preamble will commence regardless of thevalue in XMTSP. The default value of XMTSP is 10b,meaning 64 bytes full.

Automatic Pad GenerationTransmit frames can be automatically padded to extendthem to 64 data bytes (excluding preamble). This allowsthe minimum frame size of 64 bytes (512 bits) for802.3/Ethernet to be guaranteed with no software inter-vention from the host/controlling process. Setting theAPAD_XMT bit in CSR4 enables the automatic paddingfeature. The pad is placed between the LLC data fieldand FCS field in the 802.3 frame (see Figure 35). FCS isalways added if the frame is padded, regardless of thestate of DXMTFCS. The transmit frame will be paddedby bytes with the value of 00h. The default value ofAPAD_XMT is 0; this will disable auto pad generationafter H_RESET.

It is the responsibility of upper layer software to correctlydefine the actual length field contained in the messageto correspond to the total number of LLC Data bytes en-capsulated in the packet (length field as defined in theISO 8802-3 (IEEE/ANSI 802.3) standard). The lengthvalue contained in the message is not used by thePCnet-32 controller to compute the actual number ofpad bytes to be inserted. The PCnet-32 controller willappend pad bytes dependent on the actual number ofbits transmitted onto the network. Once the last databyte of the frame has completed, prior to appending theFCS, the PCnet-32 controller will check to ensure that544 bits have been transmitted. If not, pad bytes areadded to extend the frame size to this value, and theFCS is then added.

Preamble1010....1010

Sync10101011

DestinationAddress

SourceAddress Length

LLCData Pad FCS

4Bytes

46 — 1500Bytes

2Bytes

6Bytes

6Bytes

8Bits

56Bits

18219B-42

Figure 35. ISO 8802-3 (IEEE/ANSI 802.3) Data Frame


117Am79C965

The 544 bit count is derived from the following:

Minimum frame size 64 bytes 512 bits(excluding preamble, including FCS)

Preamble/SFD size 8 bytes 64 bits

FCS size 4 bytes 32 bits

To be classed as a minimum size frame at the receiver,the transmitted frame must contain:

Preamble + (Min Frame Size + FCS) bits

At the point that FCS is to be appended, the transmittedframe should contain:

Preamble + (Min Frame Size–FCS) bits

64 + (512–32) bits

A minimum length transmit frame from the PCnet-32controller will, therefore, be 576 bits, after the FCS isappended.

The Ethernet specification assumes that minimumlength messages will be at least 64 bytes in length.

Transmit FCS GenerationAutomatic generation and transmission of FCS for atransmit frame depends on the value of DXMTFCS bit inCSR15. When DXMTFCS = 0 the transmitter will gener-ate and append the FCS to the transmitted frame. If theautomatic padding feature is invoked (APAD_XMT isset in CSR4), the FCS will be appended by the PCnet-32controller regardless of the state of DXMTFCS. Notethat the calculated FCS is transmitted most significantbit first. The default value of DXMTFCS is 0 afterH_RESET.

Transmit Exception ConditionsException conditions for frame transmission fall into twodistinct categories. Those which are the result of normalnetwork operation, and those which occur due to abnor-mal network and/or host related events.

Normal events which may occur and which are handledautonomously by the PCnet-32 controller include colli-sions within the slot time with automatic retry. ThePCnet-32 controller will ensure that collisions which oc-cur within 512 bit times from the start of transmission(including preamble) will be automatically retired with nohost intervention. The transmit FIFO ensures this byguaranteeing that data contained within the FIFO willnot be overwritten until at least 64 bytes (512 bits) ofpreamble plus address, length and data fields havebeen transmitted onto the network without encounteringa collision.

If 16 total attempts (initial attempt plus 15 retries) fail, thePCnet-32 controller sets the RTRY bit in the currenttransmit TDTE in host memory (TMD2), gives up owner-ship (resets the OWN bit to zero) for this frame, and

processes the next frame in the transmit ring fortransmission.

Abnormal network conditions include:

Loss of carrier.

Late collision.

SQE Test Error (does not apply to 10BASE-T port)

None of the abnormal network conditions should not oc-cur on a correctly configured 802.3 network, and will bereported if they do.

When an error occurs in the middle of a multi-bufferframe transmission, the error status will be written in thecurrent descriptor. The OWN bit(s) in the subsequentdescriptor(s) will be reset until the STP (the next frame)is found.

Loss of CarrierA loss of carrier condition will be reported if thePCnet-32 controller cannot observe receive activitywhile it is transmitting on the AUI port. After thePCnet-32 controller initiates a transmission it will expectto see data “looped-back” on the DI± pair. This will inter-nally generate a “carrier sense,” indicating that the in-tegrity of the data path to and from the MAU is intact, andthat the MAU is operating correctly. This “carrier sense”signal must be asserted about 6 bit times before the lasttransmitted bit on DO±. If “carrier sense” does not be-come active in response to the data transmission, or be-comes inactive before the end of transmission, the lossof carrier (LCAR) error bit will be set in TMD2 after theframe has been transmitted. The frame will not be re-tried on the basis of an LCAR error.

When the 10BASE-T port is selected, LCAR will be re-ported for every frame transmitted during the Linkfail condition.

Late CollisionA late collision will be reported if a collision conditionoccurs after one slot time (512 bit times) after the trans-mit process was initiated (first bit of preamble com-menced). The PCnet-32 controller will abandon thetransmit process for the particular frame, set Late Colli-sion (LCOL) in the associated TMD2, and process thenext transmit frame in the ring. Frames experiencing alate collision will not be re-tried. Recovery from this con-dition must be performed by upper layer software.

SQE Test ErrorDuring the inter packet gap time following the comple-tion of a transmitted message, the AUI CI± pair is as-serted by some transceivers as a self-test. The integralManchester Encoder/Decoder will expect the SQE TestMessage (nominal 10 MHz sequence) to be returned viathe CI± pair, within a 40 network bit time period after DI±goes inactive (this does not apply if the 10BASE-T portis selected). If the CI± input is not asserted within the 40network bit time period following the completion oftransmission, then the PCnet-32 controller will set the


118 Am79C965

CERR bit in CSR0. CERR will be asserted in 10BASE-Tmode after transmit if T-MAU is in Link Fail state. CERRwill never cause INTR to be activated. It will, however,set the ERR bit in CSR0.

Receive OperationThe receive operation and features of the PCnet-32controller are controlled by programmable options.

Receive Function ProgrammingAutomatic pad field stripping is enabled by setting theASTRP_RCV bit in CSR4. this can provide flexibility inthe reception of messages using the 802.3 frameformat.

All receive frames can be accepted by setting the PROMbit in CSR15. When PROM is set, the PCnet-32 control-ler will attempt to receive all messages, subject to mini-mum frame enforcement. Promiscuous mode over ridesthe effect of the Disable Receive Broadcast bit on re-ceiving broadcast frames.

The point at which the BMU will start to transfer datafrom the receive FIFO to buffer memory is controlled bythe RCVFW bits in CSR80. The default established dur-ing H_RESET is 10b which sets the threshold flag at 64bytes empty.

Automatic Pad StrippingDuring reception of an 802.3 frame the pad field can bestripped automatically.

ASTRP_RCV (CSR4, bit 10) = 1 enables the automaticpad stripping feature. The pad field will be stripped be-fore the frame is passed to the FIFO, thus preserving

FIFO space for additional frames. The FCS field will alsobe stripped, since it is computed at the transmitting sta-tion based on the data and pad field characters, and willbe invalid for a receive frame that has had the pad char-acters stripped.

The number of bytes to be stripped is calculated fromthe embedded length field, as defined in the ISO 8802-3(IEEE/ANSI 802.3) definition, contained in the frame.The length indicates the actual number of LLC databytes contained in the message. Any received framewhich contains a length field less than 46 bytes will havethe pad field stripped (if ASTRP_RCV is set). Receiveframes which have a length field of 46 bytes or greaterwill be passed to the host unmodified.

Note that for some network protocols, the valuepassed in the Ethernet Type and/or 802.3 Length field isnot compliant with either standard and maycause problems.

Figure 36 shows the byte/bit ordering of the receivedlength field for an 802.3 compatible frame format.

Receive FCS CheckingReception and checking of the received FCS is per-formed automatically by the PCnet-32 controller. Notethat if the Automatic Pad Stripping feature is enabled,the FCS for padded frames will be verified against thevalue computed for the incoming bit stream includingpad characters, but the FCS value for a padded framewill not be passed to the host. If an FCS error is detectedin any frame, the error will be reported in the CRC bitin RMD1.

18219B-43

Preamble1010....1010

Sync10101011

DestinationAddress

SourceAddress Length

LLCData Pad FCS

4Bytes

46 — 1500Bytes

2Bytes

6Bytes

6Bytes

8Bits

56Bits

Start of Frameat Time = 0

Increasing Time

Bit0

Bit7

Bit0

Bit7

MostSignificant

Byte

LeastSignificant

Byte

1 — 1500Bytes

45 — 0Bytes

Figure 36. ISO 8802-3 (IEEE/ANSI 802.3) Data Frame


119Am79C965

Receive Exception ConditionsException conditions for frame reception fall into twodistinct categories: Those which are the result of normalnetwork operation, and those which occur due to abnor-mal network and/or host related events.

Normal events which may occur and which are handledautonomously by the PCnet-32 controller are basicallycollisions within the slot time and automatic runt packetrejection. The PCnet-32 controller will ensure that colli-sions which occur within 512 bit times from the start ofreception (excluding preamble) will be automatically de-leted from the receive FIFO with no host intervention.The receive FIFO will delete any frame which is com-posed of fewer than 64 bytes provided that the RuntPacket Accept (RPA bit in CSR124) feature has notbeen enabled. This criterion will be met regardless ofwhether the receive frame was the first (or only) frame inthe FIFO or if the receive frame was queued behind apreviously received message.

Abnormal network conditions include:

FCS error

Late collision

Host related receive exception conditions includeMISS, BUFF, and OFLO. These are described in theBMU section.

Loopback OperationLoopback is a mode of operation intended for systemtesting. In this mode the transmitter and receiver areboth operating at the same time so that the controllerreceives its own transmissions. The controller providestwo types of internal loopback and one type of externalloopback. In internal loopback mode the transmitterdata can be looped back to the receiver at one of twoplaces inside the controller without actually transmittingany data to the external network. The receiver will movethe received data to the external network. The receiverwill move the received data to the next receive buffer,where it can be examined by software. Alternatively, inexternal loopback mode, data can be transmitted to andreceived from the external network.

There are restrictions on loopback operation. ThePCnet-32 controller has only one FCS generator circuit.The FCS generator can be used by the transmitter togenerate the FCS that is appended to the frame, or it canbe used by the receiver to verify the FCS of the receivedframe. It can not be used by the receiver and transmitterat the same time.

If the FCS generator is connected to the receiver, thetransmitter will not append an FCS to the frame, but thereceiver will check for one. The user can, however, cal-culate the FCS value for a frame and include this four-byte number in the transmit buffer.

If the FCS generator is connected to the transmitter, thetransmitter will append an FCS to the frame, but the re-

ceiver will not check it. However, the user can verify theFCS by software.

During loopback the FCS logic can be allocated to thereceiver by setting DXMTFCS = 1 in CSR15.

If DXMTFCS=0, the MAC Engine will calculate and ap-pend the FCS to the transmitted message. The receivemessage passed to the host will therefore contain anadditional 4 bytes of FCS. In this loopback configuration,the receive circuitry cannot detect FCS errors ifthey occur.

If DXMTFCS=1, the last four bytes of the transmit mes-sage must contain the (software generated) FCS com-puted for the transmit data preceding it. The MACEngine will transmit the data without addition of an FCSfield, and the FCS will be calculated and verified at thereceiver.

The loopback facilities of the MAC Engine allow full op-eration to be verified without disturbance to the network.Loopback operation is also affected by the state of theLoopback Control bits (LOOP, MENDECL, and INTL) inCSR15. This affects whether the internal MENDEC isconsidered part of the internal or external loop-back path.

The multicase address detection logic uses the FCSgenerator. Therefore, when in the loopback mode(s),the multicast address detection feature of the MAC En-gine, programmed by the contents of the Logical Ad-dress Filter (LADRF [63:0] in CSRs 8-11) can only betested when DXMTFCS=1, allocating the FCS genera-tor to the receiver. All other features operate identicallyin loopback as in normal operation, such as automatictransmit padding and receive pad stripping.

When performing an internal loopback, no frame will betransmitted to the network. However, when thePCnet-32 controller is configured for internal loopbackthe receiver will not be able to detect network traffic.External loopback tests will transmit frames onto thenetwork when the AUI port is selected. Runt Packet Ac-cept is automatically enabled when any loopback modeis invoked.

Loopback mode can be performed with any frame size.Runt Packet Accept is internally enabled (RPA bit inCSR 124 is not affected) when any loopback mode isinvoked. This is to be backwards compatible to theLANCE (Am7990) software.

When external loopback is performed while the10BASE-T MAU is selected, collision detection is dis-abled. This is necessary, because a collision in a10BASE-T system is defined as activity on the transmit-ter outputs and receiver inputs at the same time, whichis exactly what happens during external loopback.


120 Am79C965

Since a 10BASE-T hub does not normally feed the sta-tion’s transmitter outputs back into the station’s receiverinputs, the use of external loopback in a 10BASE-T sys-tem usually requires some sort of external hardware thatconnects the outputs of the 10BASE-T MAU to itsinputs.

LED SupportThe PCnet-32 controller can support up to 4 LEDs.

LED outputs LNKST, LED1 and LED2 allow for directconnection of an LED and its supporting pull-up device.LED output LEDPRE3 may require an additional bufferbetween the PCnet-32 controller output pin and the LEDand its supporting pull-up device.

Because the LEDPRE3 output is multiplexed with otherPCnet-32 controller functions, it may not always be pos-sible to connect an LED circuit directly to the LEDPRE3pin. For example, when an LED circuit is directly con-nected to the EEDO/LEDPRE3/SRD pin, then it is notpossible for most serial EEPROM devices to sinkenough IOL to maintain a valid low level on the EEDOinput to the PCnet-32 controller. Therefore, in applica-tions that require both an EEPROM and a fourth LED,then it is necessary to buffer the LEDPRE3 circuit fromthe EEPROM-PCnet-32 controller connection. The LEDregisters in the BCR resource space allow each LEDoutput to be programmed for either active high or activelow operation, so that both inverting and non-invertingbuffering choices are possible.

In applications where an EEPROM is not needed, theLEDPRE3 pin may be directly connected to an LED

circuit. The PCnet-32 controller LEDPRE3 pin driver willbe able to sink enough current to properly drive the LEDcircuit.

By default, after H_RESET, the 4 LED outputs are con-figured as shown in Table 40.

Table 40. LED Configuration

Default Default LED Default Drive OutputOutput Interpretation Enable Polarity

LNKST Link Status Enabled Active LOW

LED1 Receive Enabled Active LOW

LED2 Receive Polarity Enabled Active LOW

LEDPRE3 Transmit Enabled Active LOW

For each LED register, each of the status signals isANDed with its enable signal, and these signals are allOR’d together to form a combined status signal. EachLED pin’s combined status signal runs to a pulsestretcher, which consists of a 3-bit shift register clockedat 38 Hz (26 ms). The data input of each shift register isnormally at logic 0. The OR gate output for each LEDregister asynchronously sets all three bits of its shift reg-ister when the output becomes asserted. The invertedoutput of each shift register is used to control an LEDpin. Thus the pulse stretcher provides 2–3 clocks ofstretched LED output, or 52 ms to 78 ms.

Figure 37 shows the LED signal circuit that exists foreach LED pin.

LNKSTLNKST E

RCVMRCVM E

XMTXMT E

RXPOLRXPOL E

RCVRCV E

JABJAB E

18219A-44

COLCOL E

To Pulse Stretcher

Figure 37. On-Chip LED Control Logic


121Am79C965

H_RESET, S_RESET and STOPThere are three different types of RESET operationsthat may be performed on the PCnet-32 device,H_RESET, S_RESET and STOP. These names havebeen used throughout the document. The following is adescription of each type of RESET operation:

H_RESETH_RESET= HARDWARE_RESET is a PCnet-32RESET operation that has been created by the properassertion of the RESET pin of the PCnet-32 device.When the minimum pulse width timing as specified inthe RESET pin description has been satisfied, then aninternal RESET operation will be performed.

H_RESET will RESET all of or some portions of CSR0,3, 4, 15, 58, 80, 82, 100, 112, 114, 122, 124 and 126 todefault values; H_RESET will RESET all of or some por-tions of BCR 2, 4, 5, 6, 7, 18, 19, 20, 21 to default values.H_RESET will cause the microcode program to jump toits RESET state. Following the end of the H_RESET op-eration, the PCnet-32 controller will attempt to read theEEPROM device through the EEPROM microwire inter-face. The H_RESET operation will unconditionallycause all INTR pins to become inactive. (Note that theremay be either 2 or 4 INTR pins, depending upon theJTAGSEL pin setting.) The H_RESET operation will un-conditionally cause the HOLD signal to become deas-serted. H_RESET will reset T-MAU to Link Fail state.

H_RESET is generated by proper assertion of either theRESET or RESET pin, depending upon the mode thathas been selected through the LB/VESA pin.

S_RESETS_RESET = SOFTWARE_RESET is a PCnet-32RESET operation that has been created by a read ac-cess to the RESET REGISTER which is located at offset14h from the PCnet-32 controller I/O base address.

S_RESET will RESET all of or some portions of CSR0,3, 4, 15, 80, 100 and 124 to default values. S_RESETwill RESET NONE of the BCR locations to default

values. S_RESET will cause the microcode program tojump to its RESET state. Following the end of theS_RESET operation, the PCnet-32 controller will NOTattempt to read the EEPROM device. See also the sub-section on RESET Register in the I/O Register Accesssection under Software Access. The S_RESET opera-tion will not cause INTR pins to become inactive.S_RESET will set the T-MAU into Link Fail state.

Note that S_RESET will not cause a deassertion of theHOLD signal, if it happens to be active at the time of theread to the reset register. The HOLD signal will remainactive until the HLDA signal is synchronously sampledas asserted. Following the read of the RESET register,on the next clock cycle after the HLDA signal is synchro-nously sampled as asserted, (except in Am386 mode,when two cycles are needed) the PCnet-32 controllerwill deassert the HOLD signal; No bus master accesseswill have been performed during this brief bus owner-ship period.

STOPSTOP is a PCnet-32 RESET operation that has beencreated by the ASSERTION of the STOP bit in CSR0.That is, a STOP RESET is generated by writing a ONEto the STOP bit of CSR0 when the STOP bit currentlyhas a value of ZERO. If the STOP bit value is currently aONE, and a ONE is rewritten to the STOP bit, then NOSTOP RESET will be generated. The STOP operationwill not cause INTR pins to become inactive.

STOP will RESET all or some portions of CSR0, 3, and 4to default values; STOP will RESET NONE of the BCRlocations to default values. STOP will cause themicrocode program to jump to its RESET state. Follow-ing the end of the STOP operation, the PCnet-32 con-troller will not attempt to read the EEPROM device. Forthe identity of individual CSRs and bit locations that areaffected by STOP, see the individual CSR registerdescriptions. Setting the STOP bit does not affectthe T-MAU.


122 Am79C965

USER ACCESSIBLE REGISTERSThe PCnet-32 controller implements all PCnet-ISA(Am79C960) registers, all LANCE (Am7990) registers,all ILACC (Am79C900) registers, plus a number of addi-tional registers. The PCnet-32 controller registers arecompatible with both the PCnet-ISA (Am79C960) regis-ters and all of the LANCE (Am7990) registers uponpower up. Compatibility to the ILACC set of registersrequires one access to the Software Style register(BCR20, bits 7–0) to be performed. By setting an appro-priate value of the Software Style register (BCR20, bits7–0) the user can select a set of registers that are com-patible with the ILACC set of registers.

Note that all register locations are defined to be 16 bits inwidth when WIO mode is selected. When DWIO mode isselected, all register locations are defined to be 32 bits inwidth. When performing register write operations inDWIO mode, the upper 16 bits should always be writtenas zeros, except APROM locations. When performingregister read operations in DWIO mode, the upper 16bits of I/O resources should always be written as ZE-ROs, except for APROM locations and CSR88. Whenperforming register read operations in DWIO mode, theupper 16 bits of I/O resources should always be re-garded as having undefined values, except for theAPROM locations and CSR88.

PCnet-32 controller registers can be divided into threegroups:

Setup registers: Registers that are intended tobe initialized by the systeminitialization procedure (e.g.BIOS device initialization rou-tine) or by the device driver toprogram the operation of vari-ous PCnet-32 controllerfeatures

Running registers: Registers that are intended tobe used by the device driversoftware once the PCnet-32controller is running to accessstatus information and to passcontrol information

Test registers: Registers that are intended tobe used only for testing and di-agnostic purposes

Below is a list of the registers that fall into each of the firsttwo categories. Those registers that are not included ineither of these lists can be assumed to be intended fordiagnostic purposes.

Setup RegistersThe following is a list of those registers that would typi-cally need to be programmed once during the setup ofthe PCnet-32 controller within a system. The control bitsin each of these registers typically do not need to bemodified once they have been written. However, thereare no restrictions as to how many times these registers

may actually be accessed. Note that if the default powerup values of any of these registers is acceptable to theapplication, then such registers need never be ac-cessed at all. Also note that some of these registers maybe programmable through the EEPROM read opera-tion, and therefore do not necessarily need to be writtento by the system initialization procedure or by the driversoftware.

CRS1 Initialization Address[15:0]CSR2 Initialization Address[31:16]CSR3 Interrupt Masks and Deferral ControlCSR4 Test and Features ControlCSR8 Logical Address Filter [15:0]CSR9 Logical Address Filter [31:16]CSR10 Logical Address Filter [47:32]CSR11 Logical Address Filter [63:48]CSR12 Physical Address Filter [15:0]CSR13 Physical Address Filter [31:16]CSR14 Physical Address Filter [47:32]CSR15 Mode RegisterCSR24 Base Address of Receive Ring LowerCSR25 Base Address of Receive Ring UpperCSR30 Base Address of Transmit Ring LowerCRS31 Base Address of Transmit Ring UpperCSR47 Polling IntervalCSR58 Software StyleCSR76 Receive Ring LengthCSR78 Transmit Ring LengthCSR80 Cycle Register and FIFO Threshold ControlCSR82 Bus Activity TimerCSR100 Memory Error Time-out RegisterCSR122 Receiver Packet Alignment ControlBCR2 MAU configurationBCR16 I/O Base Address LowerBCR17 I/O Base Address UpperBCR18 Bus Size and Burst Control RegisterBCR19 EEPROM Control and Status RegisterBCR20 Software StyleBCR21 Interrupt Control

Running RegistersThe following is a list of those registers that would typi-cally need to be periodically read and perhaps writtenduring the normal running operation of the PCnet-32controller within a system. Each of these registers con-tains control bits or status bits or both.

RAP Register Address Port RegisterCSR0 PCnet-32 Controller Status RegisterCSR4 Test and Features ControlCSR112 Missed Frame CountCSR114 Receive Collision Count


123Am79C965

RAP RegisterThe RAP (Register Address Pointer) register is used togain access to CSR and BCR registers on board thePCnet-32 controller. The value of the RAP indicates theaddress of a CSR or BCR whenever an RDP or BDPaccess is performed. That is to say, RAP serves as apointer to CSR and BDP space.

As an example of RAP use, consider a read access toCSR4. In order to access this register, it is necessary tofirst load the value 0004 into the RAP by performing awrite access to the RAP offset of 12h (12h when WIOmode has been selected, 14h when DWIO mode hasbeen selected). The data for the RAP write would be0004. Then a second access is performed on thePCnet-32 controller, this time to the RDP offset of 10h(for either WIO or DWIO mode). The RDP access is aread access, and since RAP has just been loaded withthe value of 0004, the RDP read will yield the contents ofCSR4. A read of the BDP at this time (offset of 16h whenWIO mode has been selected, 1Ch when DWIO modehas been selected) will yield the contents of BCR4,since the RAP is used as the pointer into both BDP andRDP space.

RAP: Register Address Port

Bit Name Description

31-16 RES Reserved locations. Written aszeros and read as undefined.

15-8 RES Reserved locations. Read andwritten as zeros.

7-0 RAP Register Address Port. The valueof these 8 bits determines whichCSR or BCR will be accessedwhen an I/O access to the RDPor BDP port, respectively, is per-formed. RAP is cleared byH_RESET or S_RESET and isunaffected by the STOP bit.

Control and Status RegistersThe CSR space is accessible by performing accesses tothe RDP (Register Data Port). The particular CSR that isread or written during an RDP access will depend uponthe current setting of the RAP. RAP serves as a pointerinto the CSR space. RAP also serves as the pointer toBCR space, which is described in a later section.

CSR0: PCnet-32 Controller Status



15 ERR Error is set by the ORing ofBABL, CERR, MISS, and MERR.

ERR remains set as long as anyof the error flags are true. ERR isread only. Write operations areignored.

14 BABL Babble is a transmitter time-outerror. It indicates that the trans-mitter has been on the channellonger than the time required tosend the maximum length frame.BABL will be set if 1519 bytes orgreater are transmitted. WhenBABL is set, INTR is asserted ifIENA = 1 and the mask bitBABLM in CSR3 is clear. BABLassertion will set the ERR bit.

BABL is set by the MAC layer andcleared by writing a “1”. Writing a“0” has no effect. BABL is clearedby H_RESET or S_RESET orsetting the STOP bit.

13 CERR Collision Error indicates that thecollision inputs to the AUI portfailed to activate within 20 net-work bit times after chip termi-nated transmission (SQE Test).This feature is a transceiver testfeature. In 10BASE-T modeCERR will be set if a transmis-sion is attempted while theT-MAU is in Link Fail state.

CERR assertion will not result inan interrupt being generated.CERR assertion will set the ERRbit.

CERR is set by the MAC layerand cleared by writing a “1”. Writ-ing a “0” has no effect. CERR iscleared by H_RESET orS_RESET or setting the STOPbit.

12 MISS Missed Frame is set whenPCnet-32 controller has lost anincoming receive frame resultingfrom a Receive Descriptor notbeing available. This bit is theonly immediate indication thatreceive data has been lost sincethere is no current receive de-scriptor to write status to.

When MISS is set, INTR is as-serted if IENA = 1 and the maskbit MISSM in CSR3 is clear.MISS assertion will set the ERRbit.

MISS is set by the Buffer Man-agement Unit and cleared bywriting a “1”. Writing a “0” has noeffect. MISS is cleared byH_RESET or S_RESET or set-ting the STOP bit.


124 Am79C965

11 MERR Memory Error is set whenPCnet-32 controller requests theuse of the system interface busby asserting HOLD and has notreceived HLDA assertion after aprogrammable length of time.The length of time in microsec-onds before MERR is assertedwill depend upon the setting ofthe Bus Time-Out Register(CSR100). The default setting ofCSR100 will give a MERR after51.2 µs of bus latency.

When MERR is set, INTR is as-serted if IENA = 1 and the maskbit MERRM in CSR3 is clear.MERR assertion will set the ERRbit, regardless of the settings ofIENA and MERRM .

MERR is set by the Bus InterfaceUnit and cleared by writing a “1”.Writing a “0” has no effect. MERRis cleared by H_RESET orS_RESET or by setting theSTOP bit.

10 RINT Receive interrupt. RINT is set bythe Buffer Management Unit ofthe PCnet-32 controller after thelast descriptor of a receive pack-et has been updated by writing aZERO to the ownership bit. RINTmay also be set when the first de-scriptor of a receive packet hasbeen updated by writing a ZEROto the ownership bit if theSPRINTEN bit of CSR3 has beenset to a ONE.

When RINT is set, INTR is as-serted if IENA = 1 and the maskbit RINTM in CSR3 is clear.

RINT is cleared by the host bywriting a “1”. Writing a “0” has noeffect. RINT is cleared by H_RE-SET or S_RESET or by settingthe STOP bit.

9 TINT Transmit interrupt is set aftercompletion of a transmit frameand toggling of the OWN bit in thelast buffer in the Transmit De-scriptor Ring.

When TINT is set, INTR is as-serted if IENA = 1 and the maskbit TINTM in CSR3 is clear.

TINT is set by the Buffer Man-agement Unit after the last trans-mit buffer has been updated andcleared by writing a “1”. Writing a“0” has no effect. TINT is clearedby H_RESET or S_RESET orsetting the STOP bit.

8 IDON Initialization Done indicates thatthe initialization sequence hascompleted. When IDON is set,PCnet-32 controller has read theInitialization block from memory.

When IDON is set, INTR is as-serted if IENA = 1 and the maskbit IDONM in CSR3 is clear.

IDON is set by the Buffer Man-agement Unit after the initializa-tion block has been read frommemory and cleared by writing a“1”. Writing a “0” has no effect.IDON is cleared by H_RESET orS_RESET or setting the STOPbit.

7 INTR interrupt Flag indicates that oneor more following interrupt caus-ing conditions has occurred:BABL, MISS, MERR, MFCO,RCVCCO, RINT, RPCO, TINT,IDON, JAB or TXSTRT. and itsassociated mask bit is clear. IfIENA = 1 and INTR is set, INTRwill be active.

INTR is read only. INTR iscleared by H_RESET orS_RESET or by setting theSTOP bit or by clearing all of theactive individual interrupt bitsthat have not been masked out.

6 IENA interrupt Enable allows INTR tobe active if the interrupt Flag isset. If IENA = “0” then INTR willbe disabled regardless of thestate of INTR.

IENA is set by writing a “1” andcleared by writing a “0”. IENA iscleared by H_RESET orS_RESET or setting the STOPbit.

5 RXON Receive On indicates that theReceive function is enabled.RXON is set if DRX (CSR15[0]) =“0” after the START bit is set. IfINIT and START are set to-gether, RXON will not be set untilafter the initialization block hasbeen read in.

RXON is read only. RXON iscleared by H_RESET orS_RESET or setting the STOPbit.

4 TXON Transmit On indicates that theTransmit function is enabled.TXON is set if DTX (CSR15[1]) =“0” after the START bit is set. IfINIT and START are set to-gether, TXON will not be set until


125Am79C965

after the initialization block hasbeen read in.

TXON is read only. TXON iscleared by H_RESET orS_RESET or setting the STOPbit.

3 TDMD Transmit Demand, when set,causes the Buffer ManagementUnit to access the Transmit De-scriptor Ring without waiting forthe poll-time counter to elapse. IfTXON is not enabled, TDMD bitwill be reset and no Transmit De-scriptor Ring access will occur.

TDMD is required to be set if theDPOLL bit in CSR4 is set. SettingTDMD while DPOLL = 0 merelyhastens the PCnet-32 control-ler’s response to a Transmit De-scriptor Ring Entry.

TDMD is set by writing a “1”. Writ-ing a “0” has no effect. TDMD willbe cleared by the Buffer Manage-ment Unit when it fetches aTransmit Descriptor. TDMD iscleared by H_RESET orS_RESET or setting the STOPbit.

2 STOP STOP assertion disables the chipfrom all DMA activity. The chipremains inactive until eitherSTRT or INIT are set. If STOP,STRT and INIT are all set to-gether, STOP will override STRTand INIT.

STOP is set by writing a “1” or byH_RESET or S_RESET. Writinga “0” has no effect. STOP iscleared by setting either STRT orINIT.

1 STRT STRT assertion enablesPCnet-32 controller to send andreceive frames, and performbuffer management operations.Setting STRT clears the STOPbit. If STRT and INIT are set to-gether, PCnet-32 controller in-itialization will be performed first.

STRT is set by writing a “1”. Writ-ing a “0” has no effect. STRT iscleared by H_RESET orS_RESET or by setting theSTOP bit.

0 INIT INIT assertion enables PCnet-32controller to begin the initializa-tion procedure which reads in theinitialization block from memory.Setting INIT clears the STOP bit.If STRT and INIT are set to-gether, PCnet-32 controller in-itialization will be performed first.

INIT is not cleared when the in-itialization sequence has com-pleted.

INIT is set by writing a “1”. Writinga “0” has no effect. INIT is clearedby H_RESET or S_RESET or bysetting the STOP bit.

CSR1: IADR[15:0]



15-0 IADR[15:0] Lower 16 bits of the address ofthe Initialization Block.

Regardless of the value ofSSIZE32(BCR20/CSR58, bit 8)IADR[1:0] must be zero.

This register is aliased withCSR16.

Read/Write accessible onlywhen the STOP bit in CSR0 isset. Unaffected by H_RESET orS_RESET or by setting theSTOP bit.

CSR2: IADR[31:16]



15-8 IADR[31:24] If SSIZE32 is set (BCR20[8]),then the IADR[31:24] bits will beused strictly as the upper 8 bits ofthe initialization block address.

However, if SSIZE32 is reset,then the IADR[31:24] bits will beused to generate the upper 8 bitsof all bus mastering addresses,as required for a 32 bit addressbus. Note that the 16-bit softwarestructures specified by theSSIZE32 = 0 setting will yieldonly 24 bits of address forPCnet-32 controller bus masteraccesses, while the 32-bit hard-ware for which the PCnet-32 con-troller is intended will require 32bits of address. Therefore, when-ever SSIZE32 = 0, theIADR[31:24] bits will be ap-pended to the 24-bit initializationaddress, to each 24-bit descrip-tor base address and to each be-ginning 24-bit buffer address inorder to form complete 32-bit ad-dresses. The upper 8 bits that ex-ist in the descriptor addressregisters and the buffer address


126 Am79C965

registers which are stored onboard the PCnet-32 controllerwill be overwritten with theIADR[31:24] value, so that CSRaccesses to these registers willshow the 32 bit address that in-cludes the appended field.

If SSIZE32 = 1, then software willprovide 32-bit pointer values forall of the shared software struc-tures - i.e. descriptor bases andbuffer addresses, and therefore,

IADR[31:24] will not be written tothe upper 8 bits of any of theseresources, but it will be used asthe upper 8 bits of the initializa-tion address.


7-0 IADR[23:16] Bits 23 through 16 of the addressof the Initialization Block. When-ever this register is written,CSR17 is updated with CSR2’scontents.


CSR3: Interrupt Masks and Deferral Control



15 RES Reserved location. Read andwritten as zero.

14 BABLM Babble Mask. If BABLM is set,the BABL bit in CSR0 will bemasked and unable to set INTRflag in CSR0.

Read/Write accessible always.BABLM is cleared by H_RESETor S_RESET and is not affectedby STOP.

13 RES Reserved location. Read andwritten as zero.

12 MISSM Missed Frame Mask. If MISSM isset, the MISS bit in CSR0 will bemasked and unable to set INTRflag in CSR0.

Read/Write accessible always.MISSM is cleared by H_RESETor S_RESET and is not affectedby STOP.

11 MERRM Memory Error Mask. If MERRMis set, the MERR bit in CSR0 willbe masked and unable to setINTR flag in CSR0.

Read/Write accessible always.MERRM is cleared by H_RESETor S_RESET and is not affectedby STOP.

10 RINTM Receive Interrupt Mask. IfRINTM is set, the RINT bit inCSR0 will be masked and unableto set INTR flag in CSR0.

Read/Write accessible always.RINTM is cleared by H_RESETor S_RESET and is not affectedby STOP.

9 TINTM Transmit interrupt Mask. IfTINTM is set, the TINT bit inCSR0 will be masked and unableto set INTR flag in CSR0.

Read/Write accessible always.TINTM is cleared by H_RESETor S_RESET and is not affectedby STOP.

8 IDONM Initialization Done Mask. IfIDONM is set, the IDON bit inCSR0 will be masked and unableto set INTR flag in CSR0.

Read/Write accessible always.IDONM is cleared by H_RESETor S_RESET and is not affectedby STOP.

7 RES Reserved location. Read andwritten as zeroes.

6 DXSUFLO Disable Transmit Stop on Under-flow error.

When DXSUFLO (CSR3, bit 6) isset to ZERO, the transmitter isturned off when an UFLO erroroccurs (CSR0, TXON = 0).

When DXSUFLO is set to ONE,the PCnet-32 controller grace-fully recovers from an UFLOerror. It scans the transmit de-scriptor ring until it finds the startof a new frame and starts a newtransmission.

Read/Write accessible always.DXSUFLO is cleared byH_RESET or S_RESET and isnot affected by STOP.

5 LAPPEN Look-Ahead Packet ProcessingEnable. When set to a ONE, theLAPPEN bit will cause thePCnet-32 controller to generatean interrupt following the descrip-tor write operation to the firstbuffer of a receive frame. This


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interrupt will be generated inaddition to the interrupt that isgenerated following thedescriptor write operation to thelast buffer of a receive frame. Theinterrupt will be signaled throughthe RINT bit of CSR0.

Setting LAPPEN to a ONE alsoenables the PCnet-32 controllerto read the STP bit of receive de-scriptors. The PCnet-32 control-ler will use the STP information todetermine where it should beginwriting a receive frame’s data.Note that while in this mode, thePCnet-32 controller can write in-termediate frame data to bufferswhose descriptors do not containSTP bits set to ONE. Followingthe write to the last descriptorused by a frame, the PCnet-32controller will scan through thenext descriptor entries to locatethe next STP bit that is set to aONE. The PCnet-32 controllerwill begin writing the next frame’sdata to the buffer pointed to bythat descriptor.

Note that because several de-scriptors may be allocated by thehost for each frame, and not allmessages may need all of the de-scriptors that are allocated be-tween descriptors that containSTP = ONE, then some descrip-tors/buffers may be skipped inthe ring. While performing thesearch for the next STP bit that isset to ONE, the PCnet-32 con-troller will advance through thereceive descriptor ring regard-less of the state of ownershipbits. If any of the entries that areexamined during this search indi-cate PCnet-32 controller owner-ship of the descriptor but alsoindicate STP = “0”, then thePCnet-32 controller will RESETthe OWN bit to ZERO in theseentries. If a scanned entry indi-cates host ownership with STP =“0” then the PCnet-32 controllerwill not alter the entry, but will ad-vance to the next entry.

When the STP bit is found to betrue, but the descriptor that con-tains this setting is not owned bythe PCnet-32 controller, then thePCnet-32 controller will stop ad-vancing through the ring entriesand begin periodic polling of thisentry. When the STP bit is foundto be true, and the descriptor that

contains this setting is owned bythe PCnet-32 controller, then thePCnet-32 controller will stop ad-vancing through the ring entries,store the descriptor informationthat it has just read, and wait forthe next receive to arrive.

This behavior allows the hostsoftware to pre-assign bufferspace in such a manner that the“header” portion of a receiveframe will always be written to aparticular memory area, and the“data” portion of a receive framewill always be written to a sepa-rate memory area. The interruptis generated when the “header”bytes have been written to the“header” memory area.

Read/Write accessible always.The LAPPEN bit will be reset toZERO by H_RESET orS_RESET and will be unaffectedby STOP.

See Appendix D for more infor-mation on the LAPP concept.

4 DXMT2PD Disable Transmit Two Part De-ferral. If DXMT2PD is set, Trans-mit Two Part Deferral will bedisabled.

Read/Write accessible always.DXMT2PD is cleared byH_RESET or S_RESET and isnot affected by STOP.

3 EMBA Enable Modified Back-off Algo-rithm. If EMBA is set, a modifiedback-off algorithm is imple-mented.

Read/Write accessible always.EMBA is cleared by H_RESET orS_RESET and is not affected bySTOP.

2 BSWP Byte Swap. This bit is used tochoose between big and little En-dian modes of operation. WhenBSWP is set to a ONE, big En-dian mode is selected. WhenBSWP is set to ZERO, little En-dian mode is selected.

When big Endian mode is se-lected, the PCnet-32 controllerwill swap the order of bytes onthe data bus during FIFO trans-fers only. Specifically, D31-24becomes Byte0, D23-16 be-comes Byte1, D15-8 becomesByte2 and D7-0 becomes Byte3when big Endian mode is se-lected. When little Endian modeis selected, the order of bytes onthe data bus is: D31-24 is Byte3,


128 Am79C965

D23-16 is Byte2, D15-8 is Byte1and D7-0 is Byte0.

Byte swap only affects datatransfers that involve the FIFOs.Initialization block transfers arenot affected by the setting of theBSWP bit. Descriptor transfersare not affected by the setting ofthe BSWP bit. RDP, RAP andBDP accesses are not affectedby the setting of the BSWP bit.APROM transfers are not af-fected by the setting of the BSWPbit.

BSWP is write/readable regard-less of the state of the STOP bit.

BSWP is cleared by H_RESETor S_RESET and is not affectedby STOP.

1-0 RES Reserved locations. The defaultvalue is ZERO for both locations.Writing a ONE to these bits hasno effect on device function; if aONE is written to these bits, thena ONE will be read back. Existingdrivers may write a ONE to thesebits for compatibility, but newdrivers should write a ZERO tothese bits and should treat theread value as undefined.

CSR4: Test and Features Control



15 ENTST Enable Test Mode operation.Setting ENTST to ONE enablesinternal test functions which areuseful only for stand alone inte-grated circuit testing. In addition,the Runt Packet Accept (RPA) bit(CSR124, bit 3) may be changedonly when ENTST is set to ONE.

To enable RPA, the user mustfirst write a ONE to the ENTSTbit. Next, the user must first writea ONE to the RPA bit (CSR124,bit 3). Finally, the user must writea ZERO to the ENTST bit to takethe device out of test mode op-eration. Once the RPA bit hasbeen set to ONE, the device willremain in the Runt Packet Acceptmode until the RPA bit is clearedto ZERO.

Read/Write accessible. ENTSTis cleared by H_RESET orS_RESET and is unaffected bythe STOP bit.

14 DMAPLUS When DMAPLUS = “1”, disablesthe burst transaction counter,CSR80. If DMAPLUS = “0”, theburst transaction counter isenabled.

Read and Write accessible.DMAPLUS is cleared byH_RESET or S_RESET and isunaffected by the STOP bit.

13 TIMER Timer Enable Register. If TIMERis set, the Bus Activity TimerRegister, CSR82 is enabled. IfTIMER is cleared, the Bus Activ-ity Timer Register is disabled.

Read/Write accessible. TIMER iscleared by H_RESET orS_RESET and is unaffected bythe STOP bit.

12 DPOLL Disable Transmit Polling. IfDPOLL is set, the Buffer Man-agement Unit will disable trans-mit polling. Likewise, if DPOLL iscleared, automatic transmit poll-ing is enabled. If DPOLL is set,TDMD bit in CSR0 must be peri-odically set in order to initiate amanual poll of a transmit descrip-tor. Transmit descriptor pollingwill not take place if TXON is re-set.

Read/Write accessible. DPOLLis cleared by H_RESET orS_RESET and is unaffected bythe STOP bit.

11 APAD_XMT Auto Pad Transmit. When set,APAD_XMT enables the auto-matic padding feature. Transmitframes will be padded to extendthem to 64 bytes including

FCS. The FCS is calculated forthe entire frame including pad,and appended after the pad field.APAD_XMT will override the pro-gramming of the DXMTFCS bit.

Read and Write accessible.APAD_XMT is reset byH_RESET or S_RESET and isunaffected by the STOP bit.

10 ASTRP_RCV Auto Strip Receive. When set,ASTRP_RCV enables the auto-matic pad stripping feature. Thepad and FCS fields will bestripped from receive frames andnot placed in the FIFO.

Read and Write accessible.ASTRP_RCV is reset byH_RESET or S_RESET and isunaffected by the STOP bit.

9 MFCO Missed Frame Counter Overflowinterrupt. Indicates the MPC


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(CSR112) wrapped around. Canbe cleared by writing a 1 to thisbit. Also cleared by H_RESET orS_RESET or setting the STOPbit. Writing a 0 has no effect.

When MFCO is set, INTR is as-serted if IENA = 1 and the maskbit MFCOM is cleared.

When the SWSTYLE register(BCR20[7:0]) has been pro-grammed to the ILACC compati-bility mode, then this bit has nomeaning and the PCnet-32 con-troller will never set the value ofthis bit to ONE.

8 MFCOM Missed Frame Counter OverflowMask. If MFCOM is set, MFCOwill be unable to set INTR inCSR0. Set to a ONE byH_RESET or S_RESET, unaf-fected by the STOP bit.

When the SWSTYLE register(BCR20[7:0]) has been pro-grammed to the ILACC compati-bility mode, then this bit has nomeaning and the PCnet-32 con-troller will set the value of this bitto a ZERO.

7 RES Reserved location. Written aszero and read as zero.

6 RES Reserved location. This bit maybe written to as either a ONE or aZERO, but will always be read asa ZERO. This bit has no effect onPCnet-32 controller operation.

5 RCVCCO Receive Collision Counter Over-flow. Indicates the Receive Colli-sion Counter (CSR114) wrappedaround. Can be cleared by writ-ing a 1 to this bit. Also cleared byH_RESET or S_RESET or bysetting the STOP bit. Writing a 0has no effect.

When RCVCCO is set, INTR isasserted if IENA=1 and the maskbit RCVCCOM is cleared.

When the SWSTYLE register(BCR20[7:0]) has been pro-grammed to the ILACC compati-bility mode, then this bit has nomeaning and PCnet-32 control-ler will not set the value of this bitto ONE.

4 RCVCCOM Receive Collision Counter Over-flow Mask. If RCVCCOM is set,RCVCCO will be unable to setINTR in CSR0. RCVCCOM is setto a ONE by H_RESET or S_RE-SET and is not affected bySTOP.

When the SWSTYLE register(BCR20[7:0]) has been pro-grammed to the ILACC compati-bility mode, then this bit has nomeaning and PCnet-32 control-ler will set the value of this bit to aZERO.

3 TXSTRT Transmit Start status is set when-ever PCnet-32 controller beginstransmission of a frame. WhenTXSTRT is set, INTR is assertedif IENA = 1 and the mask bitTXSTRTM (CSR4 bit 2) iscleared.

TXSTRT is set by the MAC Unitand cleared by writing a “1”, byH_RESET or S_RESET, or set-ting the STOP bit. Writing a “0”has no effect.

2 TXSTRTM Transmit Start Mask. IfTXSTRTM is set, the TXSTRT bitin CSR4 will be masked and un-able to set INTR flag in CSR0.

Read/Write accessible.TXSTRTM is set to a ONE byH_RESET or S_RESET and isnot affected by the STOP bit.

1 JAB Jabber Error is set when thePCnet-32 controller Twisted-pairMAU function exceeds an al-lowed transmission limit. Jabberis set by the T-MAU cell and canonly be asserted in 10BASE-Tmode.

When JAB is set, INTR is as-serted if IENA = 1 and the maskbit JABM (CSR4[0]) is cleared.

JAB is set by the T-MAU circuitand cleared by writing a “1”. Writ-ing a “0” has no effect. JAB is alsocleared by H_RESET orS_RESET or setting the STOPbit.

When the SWSTYLE register(BCR20[7:0]) has been pro-grammed to the ILACC compati-bility mode, then this bit has nomeaning and PCnet-32 control-ler will never set the value of thisbit to ONE.

0 JABM Jabber Error Mask. If JABM isset, the JAB bit in CSR4 will bemasked and unable to set INTRflag in CSR0.

Read/Write accessible. JABM isset to a ONE by H_RESET orS_RESET and is not affected bySTOP.


130 Am79C965

When the SWSTYLE register(BCR20[7:0]) has been pro-grammed to the ILACC compati-bility mode, then this bit has nomeaning and PCnet-32 control-ler will set the value of this bit to aZERO.

CSR6: RX/TX Descriptor Table Length



15-12 TLEN Contains a copy of the transmitencoded ring length (TLEN) fieldread from the initialization blockduring PCnet-32 controller in-itialization. This field is writtenduring the PCnet-32 controller in-itialization routine.

Read accessible only whenSTOP bit is set. Write operationshave no effect and should not beperformed. TLEN is only definedafter initialization. These bits areunaffected by H_RESET,S_RESET, or STOP.

11-8 RLEN Contains a copy of the receiveencoded ring length (RLEN) readfrom the initialization block dur-ing PCnet-32 controller initializa-tion. This field is written duringthe PCnet-32 controller initializa-tion routine.

Read accessible only whenSTOP bit is set. Write operationshave no effect and should not beperformed. RLEN is only definedafter initialization. These bits areunaffected by H_RESET,S_RESET, or STOP.

7-0 RES Reserved locations. Read aszero. Write operations should notbe performed.

CSR8: Logical Address Filter, LADRF[15:0]



15-0 LADRF[15:0] Logical Address Filter,LADRF[15:0]. Defined only afterthe initialization block has beensuccessfully read or a direct I/Owrite has been performed on thisregister.

Read/write accessible only whenSTOP bit is set. These bits are

unaffected by H_RESET,S_RESET, or STOP.




15-0 LADRF[31:16] Logical Address Filter,LADRF[31:16]. Defined only af-ter the initialization block hasbeen successfully read or a directI/O write has been performed onthis register.

Read/write accessible only whenSTOP bit is set. These bits areunaffected by H_RESET,S_RESET, or STOP.




15-0 LADRF[47:32] Logical Address Filter,LADRF[47:32]. Defined only af-ter the initialization block hasbeen successfully read or a directI/O write has been performed onthis register.





15-0 LADRF[63:48] Logical Address Filter,LADRF[63:48]. Defined only af-ter the initialization block hasbeen successfully read or a directI/O write has been performed onthis register



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CSR12: Physical Address Register, PADR[15:0]



15-0 PADR[15:0] Physical Address Register,PADR[15:0]. Defined only afterthe initialization block has beensuccessfully read or a direct I/Owrite has been performed on thisregister. The PADR bits aretransmitted PADR[0] first andPADR[47] last.












CSR15: Mode Register


This register’s fields are loadedduring the PCnet-32 controller in-itialization routine with the corre-sponding Initialization Blockvalues or a direct I/O write hasbeen performed to this register.


15 PROM Promiscuous Mode.

When PROM = “1”, all incomingreceive frames are accepted.

Read/write accessible only whenSTOP bit is set.

14 DRCVBC Disable Receive Broadcast.When set, disables the PCnet-32controller from receiving broad-cast messages. Used for proto-cols that do not supportbroadcast addressing, except asa function of multicast. DRCVBCis cleared by H_RESET orS_RESET (broadcast messageswill be received) and is unaf-fected by STOP.


13 DRCVPA Disable Receive Physical Ad-dress. When set, the physical ad-dress detection (Station or nodeID) of the PCnet-32 controller willbe disabled. Frames addressedto the nodes individual physicaladdress will not be recognized(although the frame may be ac-cepted by the EADI mechanism).


12 DLNKTST Disable Link Status. WhenDLNKTST = “1”, monitoring ofLink Pulses is disabled. WhenDLNKTST = “0”, monitoring ofLink Pulses is enabled. This bitonly has meaning when the10BASE-T network interface isselected.


11 DAPC Disable Automatic Polarity Cor-rection. When DAPC = “1”, the10BASE-T receive polarity rever-sal algorithm is disabled. Like-


132 Am79C965

wise, when DAPC = “0”, thepolarity reversal algorithm isenabled.

This bit only has meaning whenthe 10BASE-T network interfaceis selected.


10 MENDECL MENDEC Loopback Mode. Seethe description of the LOOP bit inCSR15.


9 LRT/TSEL Low Receive Threshold (T-MAUMode only)

Transmit Mode Select (AUIMode only)

LRT Low Receive Threshold. WhenLRT = “1”, the internal twistedpair receive thresholds are re-duced by 4.5 dB below the stan-dard 10BASE-T value(approximately 3/5) and the un-squelch threshold for the RXDcircuit will be 180–312 mV peak.

When LRT = “0”, the unsquelchthreshold for the RXD circuit willbe the standard 10BASE-Tvalue, 300 - 520 mV peak.

In either case, the RXD circuitpost squelch threshold will beone half of the unsquelch thresh-old.

This bit only has meaning whenthe 10BASE-T network interfaceis selected.

Read/write accessible only whenSTOP bit is set. Cleared byH_RESET or S_RESET and isunaffected by STOP.

TSEL TSEL Transmit Mode Select.TSEL controls the levels at whichthe AUI drivers rest when the AUItransmit port is idle. When TSEL= 0, DO+ and DO- yield “zero” dif-ferential to operate transformercoupled loads (Ethernet 2 and802.3). When TSEL = 1, the DO+idles at a higher value with re-spect to DO-, yielding a logicalHIGH state (Ethernet 1).

This bit only has meaning whenthe AUI network interface is se-lected.


8-7 PORTSEL[1:0] Port Select bits allow for softwarecontrolled selection of the net-work medium.

PORTSEL settings of AUI and10BASE-T are ignored when theASEL bit of BCR2 (bit 1) hasbeen set to ONE.

The network port configuration isshown in Table 41.

Table 41. Network Port Configuration

ASEL Link Status NetworkPORTSEL[1:0] (BCR2[1]) (of 10BASE-T) Port

0X 1 Fail AUI

0X 1 Pass 10BASE-T

0 0 0 X AUI

0 1 0 X 10BASE-T

1 0 X X GPSI

1 1 X X Reserved

Refer to the section on GeneralPurpose Serial Interface for de-tailed information on accessingGPSI.


6 INTL Internal Loopback. See the de-scription of LOOP, CSR15-2.


5 DRTY Disable Retry. When DRTY = “1”,PCnet-32 controller will attemptonly one transmission. If DRTY =“0”, PCnet-32 controller will at-tempt 16 retry attempts beforesignaling a retry error. DRTY isdefined when the initializationblock is read.


4 FCOLL Force Collision. This bit allowsthe collision logic to be tested.PCnet-32 controller must be ininternal loopback for FCOLL tobe valid. If FCOLL = “1”, a colli-sion will be forced during loop-back transmission attempts. aRetry Error will ultimately result.If FCOLL = “0”, the Force Colli-sion logic will be disabled.


3 DXMTFCS Disable Transmit CRC (FCS).When DXMTFCS = 0, the


133Am79C965

transmitter will generate and ap-pend a FCS to the transmittedframe. When DXMTFCS = 1, theFCS logic is allocated to the re-ceiver and no FCS is generatedor sent with the transmittedframe. DXMTFCS is overriddenwhen ADD_FCS is set in TMD1.

See also the ADD_FCS bit inTMD1. If DXMTFCS is set andADD_FCS is clear for a particularframe, no FCS will be generated.The value of ADD_FCS is validonly when STP is set. IfADD_FCS is set for a particularframe, the state of DXMTFCS isignored and a FCS will be ap-pended on that frame by thetransmit circuitry.

In loopback mode, this bit deter-mines if the transmitter appendsFCS or if the receiver checks theFCS.

This bit was called DTCR in theLANCE (Am7990).


2 LOOP Loopback Enable allowsPCnet-32 controller to operate infull duplex mode for test pur-poses. When LOOP = “1”, loop-back is enabled. In combinationwith INTL and MENDECL, vari-ous loopback modes are definedin Table 42.

Table 42. Loopback Modes

LOOP INTL MENDECL Loopback Mode

0 X X Non-Loopback

1 0 X External Loopback

1 1 0 Internal Loopback Include MENDEC

1 1 1 Internal Loopback Exclude MENDEC

Read/write accessible only whenSTOP bit is set. LOOP is clearedby H_RESET or S_RESET and isunaffected by the STOP bit.

1 DTX Disable Transmit results inPCnet-32 controller not access-ing the Transmit Descriptor Ringand therefore no transmissionsare attempted. DTX = “0”, will setTXON bit (CSR0 bit 4) if STRT(CSR0 bit 1) is asserted.


0 DRX Disable Receiver results inPCnet-32 controller not access-ing the Receive Descriptor Ringand therefore all receive framedata are ignored. DRX = “0”, willset RXON bit (CSR0 bit 5) ifSTRT (CSR0 bit 1) is asserted.


CSR16: Initialization Block Address Lower


This register is an alias of the lo-cation CSR1. Accesses to/fromthis register are equivalent to ac-cess to CSR1.


15-0 IADR Lower 16 bits of the address ofthe Initialization Block. This reg-ister is an alias of CSR1. When-ever this register is written, CSR1is updated with CSR16’s con-tents.

Read/Write accessible onlywhen the STOP bit in CSR0 isset. Unaffected by RESET.

CSR17: Initialization Block Address Upper


This register is an alias of the lo-cation CSR2. Accesses to/fromthis register are equivalent to ac-cess to CSR2.


15-0 IADR Upper 16 bits of the address ofthe Initialization Block. This reg-ister is an alias of CSR2. When-ever this register is written, CSR2is updated with CSR17’scontents.

Read/Write accessible onlywhen the STOP bit in CSR0 isset. Unaffected by RESET.

CSR18: Current Receive Buffer Address Lower



15-0 CRBA Contains the lower 16 bits of thecurrent receive buffer address at


134 Am79C965

which the PCnet-32 controllerwill store incoming frame data.


CSR19: Current Receive Buffer Address Upper



15-0 CRBA Contains the upper 16 bits of thecurrent receive buffer address atwhich the PCnet-32 controllerwill store incoming frame data.


CSR20: Current Transmit Buffer Address Lower



15-0 CXBA Contains the lower 16 bits of thecurrent transmit buffer addressfrom which the PCnet-32 control-ler is transmitting.


CSR21: Current Transmit Buffer Address Upper



15-0 CXBA Contains the upper 16 bits of thecurrent transmit buffer addressfrom which the PCnet-32 control-ler is transmitting.


CSR22: Next Receive Buffer Address Lower



15-0 NRBA Contains the lower 16 bits of thenext receive buffer address towhich the PCnet-32 controllerwill store incoming frame data.


CSR23: Next Receive Buffer Address Upper



15-0 NRBA Contains the upper 16 bits of thenext receive buffer address towhich the PCnet-32 controllerwill store incoming frame data.


CSR24: Base Address of Receive Ring Lower



15-0 BADR Contains the lower 16 bits of thebase address of the ReceiveRing.


CSR25: Base Address of Receive Ring Upper



15-0 BADR Contains the upper 16 bits of thebase address of the ReceiveRing.


CSR26: Next Receive Descriptor Address Lower



15-0 NRDA Contains the lower 16 bits of thenext RDRE address pointer.


CSR27: Next Receive Descriptor Address Upper




135Am79C965

15-0 NRDA Contains the upper 16 bits of thenext RDRE address pointer.


CSR28: Current Receive Descriptor AddressLower



15-0 CRDA Contains the lower 16 bits of thecurrent RDRE address pointer.


CSR29: Current Receive Descriptor Address Up-per



15-0 CRDA Contains the upper 16 bits of thecurrent RDRE address pointer.


CSR30: Base Address of Transmit Ring Lower



15-0 BADX Contains the lower 16 bits of thebase address of the TransmitRing.


CSR31: Base Address of Transmit Ring Upper


31-16 RES Reserved locations. Read andwritten as zero.

15-0 BADX Contains the upper 16 bits of thebase address of the TransmitRing.


CSR32: Next Transmit Descriptor Address Lower



15-0 NXDA Contains the lower 16 bits of thenext TDRE address pointer.


CSR33: Next Transmit Descriptor Address Upper



15-0 NXDA Contains the upper 16 bits of thenext TDRE address pointer.


CSR34: Current Transmit Descriptor AddressLower



15-0 CXDA Contains the lower 16 bits of thecurrent TDRE address pointer.


CSR35: Current Transmit Descriptor Address Upper



15-0 CXDA Contains the upper 16 bits of thecurrent TDRE address pointer.



136 Am79C965

CSR36: Next Next Receive Descriptor AddressLower



15-0 NNRDA Contains the lower 16 bits of thenext next receive descriptor ad-dress pointer.


CSR37: Next Next Receive Descriptor AddressUpper



15-0 NNRDA Contains the upper 16 bits of thenext next receive descriptor ad-dress pointer.


CSR38: Next Next Transmit Descriptor AddressLower



15-0 NNXDA Contains the lower 16 bits of thenext next transmit descriptor ad-dress pointer.


CSR39: Next Next Transmit Descriptor AddressUpper



15-0 NNXDA Contains the upper 16 bits of thenext next transmit descriptor ad-dress pointer.


CSR40: Current Receive Status and Byte CountLower




11-0 CRBC current Receive Byte Count. Thisfield is a copy of the BCNT field ofRMD2 of the current receive de-scriptor.


CSR41: Current Receive Status and Byte CountUpper



15-8 CRST Current Receive Status. Thisfield is a copy of bits 15:8 ofRMD1 of the current receive de-scriptor.



CSR42: Current Transmit Status and Byte CountLower




11-0 CXBC current Transmit Byte Count.This field is a copy of the BCNTfield of TMD2 of the current trans-mit descriptor.



137Am79C965

CSR43: Current Transmit Status and Byte CountUpper



15-8 CXST Current Transmit Status. Thisfield is a copy of bits 15:8 ofTMD1 of the current transmit de-scriptor.



CSR44: Next Receive Status and Byte CountLower




11-0 NRBC Next Receive Byte Count. Thisfield is a copy of the BCNT field ofRMD2 of the next receive de-scriptor.


CSR45: Next Receive Status and Byte Count Upper



15-8 NRST Next Receive Status. This field isa copy of bits 15:8 of RMD1 of thenext receive descriptor.



CSR46: Poll Time Counter



15-0 POLL Poll Time Counter. This counteris incremented by the PCnet-32controller microcode and is usedto trigger the descriptor ring

polling operation of the PCnet-32controller.


CSR47: Polling Interval



15-0 POLLINT Polling Interval. This registercontains the time that thePCnet-32 controller will wait be-tween successive polling opera-tions. The POLLINT value isexpressed as the two’s comple-ment of the desired interval,where each bit of POLLINT rep-resents 1 BCLK period of time(486 and VL-Bus modes; 2 BCLK386 mode). POLLINT[3:0] are ig-nored. (POLLINT[16] is impliedto be a one, so POLLINT[15] issignificant, and does not repre-sent the sign of the two’s comple-ment POLLINT value.)

The default value of this registeris 0000. This corresponds to apolling interval of 65,536 BCLKperiods (486 and VL-Bus modes;131,072 BCLK 386 mode). ThePOLLINT value of 0000 iscrxeated during the microcodeinitialization routine, and there-fore might not be seen whenreading CSR47 after H_RESETor S_RESET.

If the user desires to program avalue for POLLINT other than thedefault, then the correct proce-dure is to first set INIT only inCSR0. Then, when the initializa-tion sequence is complete, theuser must set STOP in CSR0.Then the user may write toCSR47 and then set STRT inCSR0. In this way, the defaultvalue of 0000 in CSR47 will beoverwritten with the desired uservalue.

If the user does NOT use thestandard initialization procedure(standard implies use of an in-itialization block in memory andsetting the INIT bit of CSR0), butinstead, chooses to write directlyto each of the registers that areinvolved in the INIT operation,then it is imperative that the user


138 Am79C965

also write 0000 0000 to CSR47as part of the alternative initiali-zation sequence.


CSR48: Temporary Storage 2 Lower



15-0 TMP2 Lower 16 bits of a TemporaryStorage location.


CSR49: Temporary Storage 2 Upper



15-0 TMP2 Upper 16 bits of a TemporaryStorage location.











































139Am79C965

CSR58: Software Style


This register is an alias of the lo-cation BCR20. Accesses to/fromthis register are equivalent to ac-cesses to BCR20.


9 CSRPCNET CSR PCnet-ISA configurationbit. When set, this bit indicatesthat the PCnet-32 controller reg-ister bits of CSR4 and CSR3 willmap directly to the CSR4 andCSR3 bits of the PCnet-ISA(Am79C960) device. Whencleared, this bit indicates thatPCnet-32 controller register bitsof CSR4 and CSR3 will map di-rectly to the CSR4 and CSR3 bitsof the ILACC (Am79C900)device.

The value of CSRPCNET is de-termined by the PCnet-32 con-troller. CSRPCNET is read onlyby the host.

The PCnet-32 controller uses thesetting of the Software Style reg-ister (BCR20[7:0]/CSR58[7:0])to determine the value for this bit.

CSRPCNET is set to a ONE byH_RESET or S_RESET and isnot affected by STOP.

8 SSIZE32 Software Size 32 bits. When set,this bit indicates that thePCnet-32 controller utilizes AMD79C900 (ILACC) software struc-tures. In particular, InitializationBlock and Transmit and Receivedescriptor bit maps are affected.When cleared, this bit indicatesthat the PCnet-32 controller util-izes AMD PCnet-ISA softwarestructures. Note: Regardless ofthe setting of SSIZE32, the In-itialization Block must always be-gin on a double-word boundary.

The value of SSIZE32 is deter-mined by the PCnet-32 control-ler. SSIZE32 is read only by thehost.

The PCnet-32 controller uses thesetting of the Software Style reg-ister (BCR20, bits 7-0) to deter-mine the value for this bit.SSIZE32 is cleared by H_RESETor S_RESET and is not affectedby STOP.

If SSIZE32 is reset, then bitsIADR[31:24] of CSR2 will beused to generate values for theupper 8 bits of the 32 bit addressbus during master accesses initi-ated by the PCnet-32 controller.This action is required, since the16-bit software structures speci-fied by the SSIZE32=0 settingwill yield only 24 bits of addressfor PCnet-32 controller bus mas-ter accesses.

If SSIZE32 is set, then the soft-ware structures that are commonto the PCnet-32 controller andthe host system will supply a full32 bits for each address pointerthat is needed by the PCnet-32controller for performing masteraccesses.

The value of the SSIZE32 bit hasno effect on the drive of the upper8 address pins. The upper 8 ad-dress pins are always driven, re-gardless of the state of theSSIZE32 bit.

Note that the setting of theSSIZE32 bit has no effect on thedefined width for I/O resources.I/O resource width is determinedby the state of the DWIO bit.

7-0 SWSTYLE Software Style register. Thevalue in this register determinesthe “style” of I/O and memory re-sources that are used by thePCnet-32 controller. The S/W re-source style selection will affectthe interpretation of a few bitswithin the CSR space and thewidth of the descriptors and in-itialization block. See Table 43.

All PCnet-32 controller CSR bitsand BCR bits and all descriptor,buffer and initialization block en-tries not cited in the table aboveare unaffected by the SoftwareStyle selection and are thereforealways fully functional as speci-fied in the BCR and CSR sec-tions.


The SWSTYLE register will con-tain the value 00h followingH_RESET or S_RESET and willbe unaffected by STOP.


140 Am79C965

Table 43. Software Resource Style Selection

SWSTYLE[7:0](Hex) Style Name CSRPCNET SSIZE32 Altered Bit Interpretations

00 LANCE/ 1 0 ALL CSR4 bits will function as defined in the CSR4 section.PCnet-ISA TMD1[29] functions as ADD_FCS

01 ILACC 0 1 CSR4[9:8], CSR4[5:4] and CSR4[1:0] will have no function, but will be writeable and readable.

CSR4[15:10], CSR4[7:6] and CSR4[3:2] will function as defined in the CSR4 section. TMD1[29] becomes NO_FCS.

02 PCnet-32 1 1 ALL CSR4 bits will function as defined in the CSR4 section. TMD1[29] functions as ADD_FCS

All other Reserved Undefined Undefined Undefinedcombinations

CSR59: IR Register



15-0 IRREG Contains the value 0105.

This register always contains thesame value. It is not writeable.

Read accessible only whenSTOP bit is set.

CSR60: Previous Transmit Descriptor AddressLower



15-0 PXDA Contains the lower 16 bits of theprevious TDRE address pointer.PCnet-32 controller has the ca-pability to stack multiple transmitframes.


CSR61: Previous Transmit Descriptor AddressUpper



15-0 PXDA Contains the upper 16 bits of theprevious TDRE address pointer.PCnet-32 controller has the ca-pability to stack multiple transmitframes.


CSR62: Previous Transmit Status and Byte CountLower




Accessible only when STOP bitis set.

11-0 PXBC Previous Transmit Byte Count.This field is a copy of the BCNTfield of TMD2 of the previoustransmit descriptor.


CSR63: Previous Transmit Status and Byte CountUpper



15-8 PXST Previous Transmit Status. Thisfield is a copy of bits 15:8 ofTMD1 of the previous transmitdescriptor.



Accessible only when STOP bitis set.


141Am79C965

CSR64: Next Transmit Buffer Address Lower



15-0 NXBA Contains the lower 16 bits of thenext transmit buffer address fromwhich the PCnet-32 controllerwill transmit an outgoing frame.


CSR65: Next Transmit Buffer Address Upper



15-0 NXBA Contains the upper 16 bits of thenext transmit buffer address fromwhich the PCnet-32 controllerwill transmit an outgoing frame.


CSR66: Next Transmit Status and Byte CountLower




Accessible only when STOP bit isset.

11-0 NXBC Next Transmit Byte Count. Thisfield is a copy of the BCNT field ofTMD2 of the next transmit de-scriptor.


CSR67: Next Transmit Status and Byte CounterUpper



15-8 NXST Next Transmit Status. This fieldis a copy of bits 15:8 of TMD1 ofthe next transmit descriptor.



Accessible only when STOP bit isset.

CSR68: Transmit Status Temporary StorageLower



15-0 XSTMP Lower 16 bits of a TransmitStatus Temporary Storage loca-tion.


CSR69: Transmit Status Temporary Storage Upper



15-0 XSTMP Transmit Status Temporary Stor-age location.


CSR70: Temporary Storage Lower





CSR71: Temporary Storage Upper





CSR72: Receive Ring Counter



15-0 RCVRC Receive Ring Counter location.Contains a Two’s complement


142 Am79C965

binary number used to numberthe current receive descriptor.This counter interprets the valuein CSR76 as pointing to the firstdescriptor. a counter value ofzero corresponds to the last de-scriptor in the ring.


CSR74: Transmit Ring Counter



15-0 XMTRC Transmit Ring Counter location.Contains a Two’s complementbinary number used to numberthe current transmit descriptor.This counter interprets the valuein CSR78 as pointing to the firstdescriptor. A counter value ofzero corresponds to the last de-scriptor in the ring.


CSR76: Receive Ring Length



15-0 RCVRL Receive Ring Length. Containsthe two’s complement of the re-ceive descriptor ring length. Thisregister is initialized during thePCnet-32 controller initializationroutine based on the value in theRLEN field of the initializationblock. However, this register canbe manually altered. the actualreceive ring length is defined bythe current value in this register.The ring length can be defined asany value from 1 to 65535.


CSR78: Transmit Ring Length



15-0 XMTRL Transmit Ring Length. Containsthe two’s complement of thetransmit descriptor ring length.This register is initialized during

the PCnet-32 controller initializa-tion routine based on the value inthe TLEN field of the initializationblock. However, this register canbe manually altered. the actualtransmit ring length is defined bythe current value in this register.The ring length can be defined asany value from 1 to 65535.


CSR80: Burst and FIFO Threshold Control



15-14 RES Reserved locations. Read asones and written as zero.

13-12 RCVFW[1:0] Receive FIFO Watermark.RCVFW controls the point atwhich receive DMA is requestedin relation to the number of re-ceived bytes in the receive FIFO.RCVFW specifies the number ofbytes which must be present(once the frame has been veri-fied as a non-runt) before receiveDMA is requested. Note howeverthat in order for receive DMA tobe performed for a new frame, atleast 64 bytes must have beenreceived. This effectively avoidshaving to react to receive frameswhich are runts or suffer a colli-sion during the slot time (512 bittimes). If the Runt Packet Acceptfeature is enabled, receive DMAwill be requested as soon aseither the RCVFW threshold isreached, or a complete validreceive frame is detected (re-gardless of length). RCVFW isset to a value of 10 (64 bytes) af-ter H_RESET or S_RESET andis unaffected by STOP.

RCVFW[1:0] Bytes Received

00 16

01 32

10 64

11 Reserved


Certain combinations of water-mark programming and LINBC(BCR18[2-0]) programming maycreate situations where no linearbursting is possible, or where the


143Am79C965

FIFO may be excessively read orexcessively written. Such combi-nations are declared as illegal.

Combinations of watermark set-tings and LINBC settings mustobey the following relationship:

watermark (in bytes) ≥ LINBC (inbytes)

Combinations of watermark andLINBC settings that violate thisrule may cause unexpected be-havior.

11-10 XMTSP[1:0] Transmit Start Point. XMTSPcontrols the point at which pre-amble transmission attemptscommence in relation to the num-ber of bytes written to the trans-mit FIFO for the current transmitframe. When the entire frame isin the FIFO, transmission willstart regardless of the value inXMTSP. XMTSP is given a valueof 10 (64 bytes) after H_RESETor S_RESET and is unaffectedby STOP. Regardless ofXMTSP, the FIFO will not inter-nally over write its data until atleast 64 bytes (or the entire frameif <64 bytes) have been transmit-ted onto the network. This en-sures that for collisions within theslot time window, transmit dataneed not be re-written to thetransmit FIFO, and re-tries will behandled autonomously by theMAC. This bit is read/write ac-cessible only when the STOP bitis set.

XMTSP[1:0] Bytes Written

00 4

01 16

10 64

11 112

9-8 XMTFW[1:0] Transmit FIFO Watermark.XMTFW specifies the point atwhich transmit DMA stops,based upon the number of writecycles that could be performed tothe transmit FIFO without FIFOoverflow. Transmit DMA is al-lowed at any time when the num-ber of write cycles specified bySMTFW could be executed with-out causing transmit FIFO over-flow. XMTFW is set to a value of00b (8 cycles) after H_RESET orS_RESET and is unaffected bySTOP. Read/write accessibleonly when STOP bit is set.

XMTFW[1:0] Write Cycles

00 8

01 16

10 32

11 Reserved

Certain combinations of water-mark programming and LINBCprogramming may create situ-ations where no linear bursting ispossible, or where the FIFO maybe excessively read or exces-sively written. Such combina-tions are declared as illegal.



Combinations of watermark andLINBC settings that violate thisrule may cause unexpected be-havior.

7-0 DMACR[7:0] DMA Cycle Register. This regis-ter contains the maximum allow-able number of transfers tosystem memory that the Bus In-terface will perform during asingle DMA cycle. The CycleRegister is not used to limit thenumber of transfers during De-scriptor transfers. A value of zerowill be interpreted as one trans-fer. During H_RESET or S_RE-SET a value of 16 is loaded in theBURST register. If theDMAPLUS bit in CSR4 is set, theDMA Cycle Register is disabled.When the ENTST bit in CSR4 isset, all writes to this register willautomatically perform a decre-ment cycle.

When the Cycle Register timesout in the middle of a linear burst,the linear burst will continue untila legal starting address isreached, and then the PCnet-32controller will relinquish the bus.

Therefore, if linear bursting is en-abled, and the user wishes thePCnet-32 controller to limit busactivity to desired_max transfers,then the Cycle Register shouldbe programmed to a value of:

Burst count setting = (de-sired_max DIV (length of linearburst in transfers)) x length of lin-ear burst in transfers where DIVis the operation that yields the


144 Am79C965

INTEGER portion of the ÷operation.

Note: If either Linear Burst Writeis enabled, the value has to begreater than or equal to 4.

Read/write accessible only whenthe STOP bit is set.

CSR82: Bus Activity Timer



15-0 DMABAT Bus Activity Timer Register. If theTIMER bit in CSR4 is set, thisregister contains the maximumallowable time that PCnet-32controller will take up on the sys-tem bus during FIFO data trans-fers for a single DMA cycle. TheBus Activity Timer Register doesnot limit the number of transfersduring Descriptor transfers.

The DMABAT value is inter-preted as an unsigned numberwith a resolution of 0.1 µs. For in-stance, a value of 51 µs would beprogrammed with a value of 510.If the TIMER bit in CSR4 is set,DMABAT is enabled and must beinitialized by the user. TheDMABAT register is undefineduntil written. When the ENTST bitin CSR4 is set, all writes to thisregister will automatically per-form a decrement cycle.

If the user has NOT enabled theLinear Burst function and wishesthe PCnet-32 controller to limitbus activity to MAX_TIME µs,then the Burst Timer should beprogrammed to a value of:

MAX_TIME- [(11 + 4w) x (BCLKperiod)],

where w = wait states. If the user has enabled the Linear

Burst function and wishes thePCnet-32 controller to limit busactivity to MAX_TIME µs, thenthe Burst Timer should be pro-grammed to a value of:

MAX_TIME- [((3+lbs) x w + 10 +lbs) x (BCLK period)],

where w = wait states and lbs =linear burst size in number oftransfers per sequence.

This is because the PCnet-32controller may use as much as

one “linear burst size” plus threetransfers in order to complete thelinear burst before releasing thebus.

As an example, if the linear burstsize is four transfers, and thenumber of wait states for the sys-tem memory is two, and theBCLK period is 30 ns and theMAX time allowed on the bus is3 µs, then the Burst Timer shouldbe programmed for:

MAX_TIME- [((3+lbs) x w + 10 +lbs) x (BCLK period)],

3 ms - [(3 + 4) x 2 +10 + 4) x (30ns)] = 3 ms - (28 x 30 ns) = 3 - 0.84ms = 2.16 ms.

Then, if the PCnet-32 controller’sBus ActivityTimer times out after2.16 µs when the PCnet- 32 con-troller has completed all but thelast three transfers of a linearburst, the PCnet-32 controllermay take as much as 0.84 µs tocomplete the bursts and releasethe bus. The bus release will oc-cur at 2.16 + 0.84 = 3 µs.

A value of zero will in theDMABAT register with theTIMER bit in CSR4 set to ONEwill produce single linear burstsequences per bus master pe-riod when programmed for linearburst mode, and will yield sets ofthree transfers when not pro-grammed for linear burst mode.

The Bus Activity Timer is set to avalue of 00h after H_RESET orS_RESET and is unaffected bySTOP.


CSR84: DMA Address Lower



15-0 DMABA DMA Address Register.

This register contains the lower16 bits of the address of systemmemory for the current DMA cy-cle. The Bus Interface Unit con-trols the Address Register byissuing increment commands toincrement the memory addressfor sequential operations. TheDMABA register is undefined


145Am79C965

until the first PCnet-32 controllerDMA operation. When theENTST bit in CSR4 is set, allwrites to this register will auto-matically perform an incrementcycle.


CSR85: DMA Address Upper



15-0 DMABA DMA Address Register.

This register contains the upper16 bits of the address of systemmemory for the current DMA cy-cle. The Bus Interface Unit con-trols the Address Register byissuing increment commands toincrement the memory addressfor sequential operations. TheDMABA register is undefined un-til the first PCnet-32 controllerDMA operation. When theENTST bit in CSR4 is set, allwrites to this register will auto-matically perform an incrementcycle.


CSR86: Buffer Byte Counter



15-12 RES Reserved, Read and written withones.

11-0 DMABC DMA Byte Count Register. Con-tains a Two’s complement binarynumber of the current size of theremaining transmit or receivebuffer in bytes. This register is in-cremented by the Bus InterfaceUnit. The DMABC register is un-defined until written. WhenENTST (CSR4.15) is asserted,all writes to this register will auto-matically perform an incrementcycle.


CSR88: Chip ID Lower


This register is exactly the sameas the Chip ID register in theJTAG description.

31 - 28 Version. This 4-bit pattern is sili-con-revision dependent.

27 - 12 Part number. The 16-bit code forthe PCnet-32 controller is0010 0100 0011 0000b.

11 - 1 Manufacturer ID. The 11-bitmanufacturer code for AMD is00000000001b. This code is perthe JEDEC Publication 106-A.

0 Always a logic 1.

CSR89: Chip ID Upper


The lower 16 bits of this registerare exactly the same as the up-per 16 bits of the Chip ID registerin the JTAG description, whichare exactly the same as the up-per 16 bits of CSR88.

31 - 16 Reserved locations. Read as un-defined.

15 - 12 Version. This 4-bit pattern is sili-con-revision dependent.

11 - 0 Upper 12 bits of the PCnet-32controller part number, i.e.0010 0100 0011b.

CSR92: Ring Length Conversion



15-0 RCON Ring Length Conversion Regis-ter. This register performs a ringlength conversion from an en-coded value as found in the in-itialization block to a Two’scomplement value used for inter-nal counting. By writing bits15-12 with an encoded ringlength, a Two’s complementedvalue is read. The RCON registeris undefined until written.



146 Am79C965

CSR94: Transmit Time Domain ReflectometryCount




9-0 XMTTDR Time Domain Reflectometry re-flects the state of an internalcounter that counts from the startof transmission to the occurrenceof loss of carrier. TDR is incre-mented at a rate of 10 MHz.

Read accessible only whenSTOP bit is set. Write operationsare ignored. XMTTDR is clearedby H_RESET or S_RESET.

CSR96: Bus Interface Scratch Register 0 Lower



15-0 SCR0 This register is shared betweenthe Buffer Management Unit andthe Bus Interface Unit. All De-scriptor Data communicationsbetween the BIU and BMU arewritten and read through SCR0and SCR1 registers. The SCR0register is undefined until written.


CSR97: Bus Interface Scratch Register 0 Upper



15-0 SCR0 This register is shared betweenthe Buffer Management Unit andthe Bus Interface Unit. All De-scriptor Data communicationsbetween the BIU and BMU arewritten and read through SCR0and SCR1 registers. The SCR0register is undefined until written.


CSR98: Bus Interface Scratch Register 1 Lower



15-0 SCR1 This register is shared betweenthe Buffer Management Unit andthe Bus Interface Unit. All De-scriptor Data communicationsbetween the BIU and BMU arewritten and read through SCR0and SCR1 registers.


CSR99: Bus Interface Scratch Register 1 Upper



15-0 SCR1 This register is shared betweenthe Buffer Management Unit andthe Bus Interface Unit. All De-scriptor Data communicationsbetween the BIU and BMU arewritten and read through SCR0and SCR1 registers.


CSR100: Bus Time-out



15-0 MERRTO This register contains the valueof the longest allowable bus la-tency (interval between assertionof HOLD and assertion of HLDA)that a slave device may insertinto a PCnet-32 controller mastertransfer. If this value of bus la-tency is exceeded, then a MERRwill be indicated in CSR0, bit 11,and an interrupt may be gener-ated, depending upon the settingof the MERRM bit (CSR3, bit 11)and IENA bit (CSR0[6]).

The value in this register is inter-preted as a number of XTAL1÷2


147Am79C965

clock periods. (I.e. the value inthis register is given in 0.1 µs in-crements.) For example, thevalue 0200h (512 decimal) willcause a MERR to be indicated af-ter 51.2 µs of bus latency.

A value of zero will allow an infi-nitely long bus latency. I.e. avalue of zero will never give a bustime-out error. A non-zero valueis interpreted as an unsignednumber of BCLK cycles.

This register is set to 0200 byH_RESET or S_RESET and isunaffected by STOP.


CSR104: SWAP Register Lower



15-0 SWAP This register performs word andbyte swapping depending upon if32-bit or 16-bit internal write op-erations are performed. This reg-ister is used internally by theBIU/BMU as a word or byteswapper. The register is exter-nally accessible for test reasonsonly. CSR104 holds the lower 16bits and CSR105 holds the upper16 bits.


CSR105: SWAP Register Upper



15-0 SWAP This register performs word andbyte swapping depending upon if32-bit or 16-bit internal write op-erations are performed. This reg-ister is used internally by theBIU/BMU as a word or byteswapper. The register is exter-nally accessible for test reasonsonly. CSR104 holds the lower 16bits and CSR105 holds the upper16 bits.


CSR108: Buffer Management Scratch Lower



15-0 BMSCR The Buffer Management Scratchregister is used for assemblingReceive and Transmit Status.This register is also used as theprimary scan register for BufferManagement Test Modes.BMSCR register is undefined un-til written.


CSR109: Buffer Management Scratch Upper



15-0 BMSCR The Buffer Management Scratchregister is used for assemblingReceive and Transmit Status.This register is also used as theprimary scan register for BufferManagement Test Modes.BMSCR register is undefined un-til written.


CSR112: Missed Frame Count



15-0 MFC Missed Frame Count. Indicatesthe number of missed frames.

MFC will roll over to a count ofzero from the value 65535. TheMFCO bit of CSR4 (bit 8) will beset each time that this occurs.

This register is always readableand is cleared by H_RESET orS_RESET or STOP.

A write to this register performsan increment when the ENTSTbit in CSR4 is set.


148 Am79C965

CSR114: Receive Collision Count



15-0 RCC Receive Collision Count. Indi-cates the total number of colli-sions encountered by thereceiver since the last reset of thecounter.

RCC will roll over to a count ofzero from the value 65535. TheRCVCCO bit of CSR4 (bit 5) willbe set each time that this occurs.

The RCC value is read accessi-ble at all times, regardless of thevalue of the STOP bit. Write op-erations are ignored. RCC iscleared by H_RESET orS_RESET or by setting theSTOP bit.

A write to this register performsan increment when the ENTSTbit in CSR4 is set.

CSR122: Receive Frame Alignment Control



15-1 RES Reserved locations, written aszeros and read as undefined.

0 RCVALGN Receive Frame Align. When set,this bit forces the data field of ISO8802-3 (IEEE/ANSI 802.3)frames to align to 0 MOD 4 ad-dress boundaries (i.e. doubleword aligned addresses). It isimportant to note that this featurewill only function correctly if all re-ceive buffer boundaries aredoubleword aligned and all re-ceive buffers have 0 MOD 4lengths. In order to accomplishthe data alignment, the PCnet-32controller simply inserts twobytes of random data at the be-ginning of the receive packet (i.e.before the ISO 8802-3 (IEEE/ANSI 802.3) destination addressfield). The MCNT field reported tothe receive descriptor will not in-clude the extra two bytes.

RCVALGN is cleared byH_RESET or S_RESET and isnot affected by STOP.


CSR124: Buffer Management Test


This register is used to place theBMU/BIU into various test modeto support Test/Debug. This reg-ister is writeable only when theENTST bit in CSR4 and theSTOP bit of CSR0 are both set.The functions controlled by thisregister are enabled only if theENTST bit is set.

ENTST should be set before any-thing in CSR124 can be pro-grammed, including RUNTACC.

ENTST must be reset after writ-ing to CSR124 before writing toany other register. If it is done,the PCnet-32 controller will notrun.

All bits in this register or clearedby H_RESET or S_RESET andare not affected by STOP.



4 GPSIEN This bit places the PCnet-32 con-troller in the GPSI mode. Thismode will reconfigure the SystemInterface Address Pins so thatthe GPSI port is exposed. This al-lows bypassing the MENDEC-T-MAU logic. The GPSI modemay also be enabled by testshadow bits setting of BCR18,bits 4 and 3 as in Table 44.

See Table 45 for pin reconfigura-tion in GPSI mode.

Note that when the GPSI mode isinvoked, only the lower 24 bits ofthe address bus are available.During Software RelocatableMode the LED2 pin must bepulled LOW. IOAW24(BCR21[8]) must be set to allowslave operations. During masteraccesses in GPSI mode, thePCnet-32 controller will not drivethe upper 8 bits of the addressbus with address information.

3 RPA Runt Packet Accept. This bitforces the receive logic to acceptrunt packets (packets shorterthan 64 bytes). The state of theRPA bit can be changed onlywhen the device is in the testmode (when the ENTST bit inCSR4 is set to ONE). To enable


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RPA, software must first write aONE to the ENTST bit. Next, soft-ware must write a ONE to theRPA bit. Finally, software mustwrite a ZERO to the ENTST bit totake the device out of test modeoperation. Once the RPA bit has

been set to ONE, the device willremain in the Runt Packet Acceptmode until the RPA bit is clearedto ZERO.



TSTSHDWValue PVALID Operating

(BCR18[4:3]) (BCR19[15]) GPSIEN Mode

00 X 0 NormalOperating

Mode

10 1 X GPSI Mode

01 1 0 Reserved

11 1 X Reserved


Mode

XX 0 1 GPSI Mode












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Bus Configuration RegistersThe Bus Configuration Registers (BCR) are used to pro-gram the configuration of the bus interface and otherspecial features of the PCnet-32 controller that are notrelated to the IEEE 8802-3 MAC functions. The BCRsare accessed by first setting the appropriate RAP value,and then by performing a slave access to the BDP.

All BCR registers are 16 bits in width in WIO mode and32 bits in width in DWIO mode. The upper 16 bits of allBCR registers is undefined when in DWIO mode. Thesebits should be written as ZEROs and should be treatedas undefined when read. The “Default” value given forany BCR is the value in the register after H_RESET, andis hexadecimal unless otherwise stated. BCR register

values are unaffected by S_RESET and are unaffectedby the assertion of the STOP bit.

Note that several registers have no default value. BCR3and BCR8-BCR15 are reserved and have undefinedvalues. BCR2, BCR16, BCR17 and BCR21 are not ob-servable without first being programmed, either throughthe EEPROM read operation or through the SoftwareRelocatable Mode. Therefore, the only observable val-ues for these registers are those that have been pro-grammed and a default value is not applicable. SeeTable 46.

Writes to those registers marked as “Reserved” willhave no effect. Reads from these locations will produceundefined values.

Table 46. Bus Configuration Registers

RAP DefaultAddr. Mnemonic (Hex) Name User EEPROM SRM

0 MSRDA 0005 Master Mode Read Active No No No

1 MSWRA 0005 Master Mode Write Active No No No

2 MC N/A* Miscellaneous Configuration Yes Yes Yes

3 Reserved N/A No No No

4 LNKST 00C0 Link Status (Default) Yes No No

5 LED1 0084 Receive (Default) Yes No No

6 LED2 0088 Receive Polarity (Default) Yes No No

7 LED3 0090 Transmit (Default) Yes No No

8–15 Reserved N/A No No No

16 IOBASEL N/A* I/O Base Address Lower Yes Yes Yes

17 IOBASEU N/A* I/O Base Address Upper Yes Yes Yes

18 BSBC 2101 Burst Size and Bus Control Yes Yes No

19 EECAS 0002 EEPROM Control and Status Yes No No

20 SWSTYLE 0000 Software Style Yes No No

21 INTCON N/A* Interrupt Control Yes Yes Yes

Key: SRM = Software Relocatable Mode

* Registers marked with an asterisk (*) have no default value, since they are not observable without first being programmed,either through the EEPROM read operation or through the Software Relocatable Mode. Therefore, the only observable val-ues for these registers are those that have been programmed and a default value is not applicable.

Programmability

BCR0: Master Mode Read Active



15-0 MSRDA Reserved locations. AfterH_RESET, the value in this

register will be 0005. The set-tings of this register will have noeffect on any PCnet-32 controllerfunction.

Writes to this register have no ef-fect on the operation of thePCnet-32 controller and will notalter the value that is read.


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BCR1: Master Mode Write Active



15-0 MSWRA Reserved locations. After H_RE-SET, the value in this register willbe 0005. The settings of this reg-ister will have no effect on anyPCnet-32 controller function.

Writes to this register have no ef-fect on the operation of thePCnet-32 controller and will notalter the value that is read.

BCR2: Miscellaneous Configuration


Note that all bits in this registerare programmable through theEEPROM PREAD operation andthrough the Software Relo-catable Mode operation.


15 RES Reserved location. Written andread as zero.

14 T-MAULOOP When set, this bit allows externalloopback packets to pass ontothe network through the T-MAUinterface, if the T-MAU interfacehas been selected. If the T-MAUinterface has not been selected,then this bit has no effect.

This bit is reset to ZERO byH_RESET and is unaffected byS_RESET or STOP.

13-9 RES Reserved locations. Written andread as zero.

8 IESRWE IEEE Shadow Ram Write En-able. The PCnet-32 controllercontains a shadow RAM onboard for storage of the IEEE ad-dress following the serialEEPROM read operation. Ac-cesses to APROM I/O Re-sources will be directed towardthis RAM. When IESRWE is setto a ONE, then 32-bit and 16-bitwrite access to the shadow RAMwill be enabled.

When IESRWE is set to a ZERO,then 32-bit and 16-bit write ac-cess to the shadow RAM will bedisabled.

At no time are 8- bit write ac-cesses to the shadow RAMallowed.


7 INTLEVEL interrupt Level. This bit allows theinterrupt output signals to be pro-grammed for edge or level-sensi-tive applications.

When INTLEVEL is set to aZERO, the selected interrupt pinis configured for edge sensitiveoperation. In this mode, an inter-rupt request is signaled by a highlevel driven on the selected inter-rupt pin by the PCnet-32 control-ler. When the interrupt is cleared,the selected interrupt pin isdriven to a low level by thePCnet-32 controller. This modeis intended for systems that donot allow interrupt channels to beshared by multiple devices.

When INTLEVEL is set to a ONE,the selected interrupt pin is con-figured for level sensitive opera-tion. In this mode, an interruptrequest is signaled by a low leveldriven on the selected interruptpin by the PCnet-32 controller.When the interrupt is cleared, theselected interrupt pin is floatedby the PCnet-32 controller andallowed to be pulled to a highlevel by an external pull-up de-vice. This mode is intended forsystems which allow the interruptsignal to be shared by multipledevices.

This bit is reset to ZERO byH_RESET and is unaffected byR_RESET or STOP.

6-4 RES Reserved locations. Written andread as zero.

3 EADISEL EADI Select. When set, this bitconfigures three of the four LEDoutputs to function as the outputsof an EADI interface. LED1 be-comes SFBD, LED2 becomesSRDCLK and LEDPRE3 be-comes SRD. LNKST continues tofunction as an LED output. In ad-dition to these reassignments,the INTR2 pin will be reassignedto function as the EAR pin.


2 AWAKE Auto-Wake. If LNKST is set andAWAKE = “1”, the 10BASE-T re-ceive circuitry is active duringsleep and listens for Link Pulses.LNKST indicates Link Status and


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goes active if the 10BASE-T portcomes of out of “link fail” state.This LNKST pin can be used byexternal circuitry to re-enable thePCnet-32 controller and/or otherdevices.

When AWAKE = “0”, the Auto-Wake circuitry is disabled. Thisbit only has meaning when the10BASE-T network interface isselected.


1 ASEL Auto Select. When set, thePCnet-32 controller will auto-matically select the operatingmedia interface port, unless theuser has selected GPSI modethrough appropriate program-ming of the PORTSEL bits of theMode Register (CSR15). If GPSImode has not been selected andASEL has been set to a ONE,then when the 10BASE-T trans-ceiver is in the link pass state(due to receiving valid frame dataand/or Link Test pulses or theDLNKTST bit is set), the10BASE-T port will be used. IfGPSI mode has not been se-lected and ASEL has been set toa ONE, then when the 10BASE-Tport is in the link fail state, the AUIport will be used. Switching be-tween the ports will not occur dur-ing transmission, to avoid anytype of fragment generation.

When ASEL is set to ONE, LinkBeat Pulses will be transmittedon the 10BASE-T port, regard-less of the state of Link Status.When ASEL is reset to ZERO,Link Beat Pulses will only betransmitted on the 10BASE-Tport when the PORTSEL bits ofthe Mode Register (CSR15)have selected 10BASE-T as theactive port.

When ASEL is set to a ZERO,then the selected network portwill be determined by the settingsof the PORTSEL bits of CSR15.

The ASEL bit is reset to ONE byH_RESET and is unaffected byS_RESET or STOP.

The network port configurationare as follows:

ASEL Link Status NetworkPORTSEL(1:0) (BCR2[1]) (of 10BASE-T) Port

0X 1 0 AUI

0X 1 1 10BASE-T

0 0 0 X AUI

0 1 0 X 10BASE-T

1 0 X X GPSI

1 1 X X Reserved

0 RES Reserved location. The defaultvalue of this bit is a ZERO. Writ-ing a ONE to this bit has no effecton device function. Existing driv-ers may write a ONE to this bit,but new drivers should write aZERO to this bit.

BCR4: Link Status LED


BCR4 controls the function(s)that the LNKST pin displays. Mul-tiple functions can be simultane-ously enabled on this LED pin.The LED display will indicate thelogical OR of the enabled func-tions. BCR4 defaults to LinkStatus (LNKST) with pulsestretcher enabled (PSE = 1) andis fully programmable.

The default setting afterH_RESET for the LNKST regis-ter is 00C0h. The LNKST registervalue is unaffected by S_RESETor STOP.


15 LEDOUT This bit indicates the current(non-stretched) value of the LEDoutput pin. A value of ONE in thisbit indicates that the OR of theenabled signals is true.

The logical value of the LEDOUTstatus signal is determined by thesettings of the individual StatusEnable bits of the LED register(Bits 6-0).

This bit is READ only by the host,and is unaffected by H_RESETor S_RESET or STOP.

This bit is valid only if the networklink status is PASS.


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14 LEDPOL LED Polarity. When this bit hasthe value ZERO, then the LEDpin will be driven to a LOW levelwhenever the OR of the enabledsignals is true and the LED pinwill be floated and allowed to floathigh whenever the OR of the en-abled signals is false (i.e. theLED output will be an Open Drainoutput and the output value willbe the inverse of the LEDOUTstatus bit).

When this bit has the value ONE,then the LED pin will be driven toa HIGH level whenever the OR ofthe enabled signals is true andthe LED pin will be driven to aLOW level whenever the OR ofthe enabled signals is false (i.e.the LED output will be a TotemPole output and the output valuewill be the same polarity as theLEDOUT status bit).

The setting of this bit will not af-fect the polarity of the LEDOUTbit for this register.

13 LEDDIS LED Disable. This bit is used todisable the LED output. WhenLEDDIS has the value ONE, thenthe LED output will always befloated. When LEDDIS has thevalue ZERO, then the LED out-put value will be governed by theLEDOUT and LEDPOL values.

12-8 RES Reserved locations. Written asZEROs, read as undefined.

7 PSE Pulse Stretcher Enable. Extendsthe LED illumination time foreach new occurrence of the en-abled function for this LEDoutput.

A value of 0 disables the function.A value of 1 enables the function.

6 LNKSTE Link Status Enable. Indicates thecurrent link status on the TwistedPair interface. When this bit isset, a value of ONE will bepassed to the LEDOUT signal toindicate that the link status stateis PASS. A value of ZERO will bepassed to the LEDOUT signal toindicate that the link status stateis FAIL.

A value of 0 disables the signal. Avalue of 1 enables the signal.

5 RCVME Receive Match status Enable. In-dicates receive activity on thenetwork that has passed the ad-dress match function for thisnode. All address matching

modes are included: Physical,Logical filtering, Promiscuous,Broadcast, and EADI.


4 XMTE Transmit status Enable. Indi-cates PCnet-32 controller trans-mit activity.


3 RXPOLE Receive Polarity status Enable.Indicates the current ReceivePolarity condition on the TwistedPair interface. A value of ONE in-dicates that the polarity of theRXD± pair has been reversed. Avalue of ZERO indicates that thepolarity of the RXD± pair has notbeen reversed.

Receive polarity indication isvalid only if the LNKST bit ofBCR4 indicates link PASSstatus.


2 RCVE Receive status Enable. Indicatesreceive activity on the network.


1 JABE Jabber status Enable. Indicatesthat the PCnet-32 controller isjabbering on the network.


0 COLE Collision status Enable. Indi-cates collision activity on the net-work. When the AUI port isselected, collision activity duringthe 4.0 µs internal following atransmit completion (SQE inter-nal) will not activate the LEDOUTbit.


BCR5: LED1 Status


BCR5 controls the function(s)that the LED1 pin displays. Multi-ple functions can be simultane-ously enabled on this LED pin.The LED display will indicate thelogical OR of the enabled func-tions. BCR5 defaults to ReceiveStatus (RCV) with pulse


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stretcher enabled (PSE = 1) andis fully programmable.

The default setting afterH_RESET for the LED1 registeris 0084h. The LED1 registervalue is unaffected by S_RESETor STOP.



The logical value of the LEDOUTstatus signal is determined by thesettings of the individual StatusEnable bits of the LED register(Bits 6-0).

This bit is READ only by the host,and is unaffected by H_RESETS_RESET or STOP.





13 LEDDIS LED Disable. This bit is used todisable the LED output. WhenLEDDIS has the value ONE, thenthe LED output will always befloated. When LEDDIS has thevalue ZERO, then the LED out-put value will be governedby the LEDOUT and LEDPOLvalues.

12-8 RES Reserved locations. Write as ZE-ROs, read as undefined.

7 PSE Pulse Stretcher Enable. Extendsthe LED illumination time foreach new occurrence of the en-abled function for this LED out-put.




5 RCVME Receive Match status Enable. In-dicates receive activity on thenetwork that has passed the ad-dress match function for thisnode. All address matchingmodes are included: Physical,Logical filtering, Promiscuous,Broadcast, and EADI.










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BCR6: LED2 Status


BCR6 controls the function(s)that the LED2 pin displays. Multi-ple functions can be simultane-ously enabled on this LED pin.The LED display will indicate thelogical OR of the enabled func-tions. BCR6 defaults to twistedpair MAU Receive Polarity(RCVPOL) with pulse stretcherenabled (PSE = 1) and is fullyprogrammable.

The default setting afterH_RESET for the LED2 registeris 0088h. The LED2 registervalue is unaffected by S_RESETor STOP.



The logical value of the LEDOUTstatus signal is determined by thesettings of the individual StatusEnable bits of the LED register(Bits 11-8 and 5-0).



14 LEDPOL LED Polarity. When this bit hasthe value ZERO, then the LEDpin will be driven to a LOW levelwhenever the OR of the enabledsignals is true and the LED pinwill be floated and allowed to float

high whenever the OR of the en-abled signals is false (i.e. theLED output will be an Open Drainoutput and the output value willbe the inverse of the LEDOUTstatus bit).



13 LEDDIS LED Disable. This bit is used todisable the LED output. WhenLEDDIS has the value ONE, thenthe LED output will always befloated. When LEDDIS has thevalue ZERO, then the LED out-put value will be governed by theLEDOUT and LEDPOLvalues.


7 PSE Pulse Stretcher Enable. Extendsthe LED illumination time foreach new occurrence of the en-abled function for this LED out-put.






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BCR7: LED3 Status


BCR7 controls the function(s)that the LEDPRE3 pin displays.Multiple functions can be simul-taneously enabled on this LEDpin. The LED display will indicatethe logical OR of the enabledfunctions. BCR7 defaults toTransmit Status (XMT) withpulse stretcher enabled (PSE =1) and is fully programmable.

The default setting afterH_RESET for the LED3 registeris 0090h. The LED3 register

value is unaffected by S_RESETor STOP.



The logical value of the LEDOUTstatus signal is determined by thesettings of the individual StatusEnable bits of the LED register(Bits 11-8 and 5-0).






13 LEDDIS LED Disable. This bit is used todisable the LED output. WhenLEDDIS has the value ONE, thenthe LED output will always befloated. When LEDDIS has thevalue ZERO, then the LED out-put value will be governed by theLEDOUT and LEDPOLvalues.


7 PSE Pulse Stretcher Enable. Extendsthe LED illumination time foreach new occurrence of the en-


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abled function for this LEDoutput.

















BCR16: I/O Base Address Lower


Note that all bits in this registerare programmable through theEEPROM PREAD operation andthrough the SoftwareRelocatable Mode operation.


15-5 IOBASEL I/O Base Address Lower 16 bits.These bits are used to determinethe location of the PCnet-32 con-troller in all of I/O space. Theyfunction as bits 15 through 5 ofthe I/O address of the PCnet-32controller. Note that the lowestfive bits of the PCnet-32 control-ler I/O space are not programma-ble. These bits are assumed tobe ZEROs. This means that it isnot possible to locate thePCnet-32 controller on a spacethat does not begin on a 32-byteblock boundary. The value ofIOBASEL is determined in eitherof two ways:

1. The IOBASEL value may beset during the EEPROM read.

2. If no EEPROM exists, or ifthere is an error detected inthe EEPROM data, then thePCnet-32 controller will enterSoftware Relocatable Mode,and a specific sequence ofwrite accesses to I/O address378h will cause the IOBASELvalue to be updated. Refer tothe Software RelocatableMode section of this docu-ment for more details.

A direct write access to the I/OBase Address Lower registermay be performed.


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IOBASEL is not affected byS_RESET or STOP.

4-0 RES Reserved locations. Written asZEROs, read as undefined.

BCR17: I/O Base Address Upper


Note that all bits in this registerare programmable through theEEPROM PREAD operation andsoftware relocatable mode.


15-0 IOBASEU I/O Base Address Upper 16 bits.These bits are used to determinethe location of the PCnet-32 con-troller in all of I/O space. Theyfunction as bits 31 through 16 ofthe I/O address of the PCnet-32controller. The value ofIOBASEU is determined in eitherof two ways:

1. The IOBASEU value may beset during the EEPROM read.

2. If no EEPROM exists, or ifthere is an error detected inthe EEPROM data, then thePCnet-32 controller will enterSoftware Relocatable Mode,and a specific sequence ofwrite accesses to I/O address378h will cause the IOBASEUvalue to be updated. Refer tothe Software RelocatableMode section of this docu-ment for more details.

A direct write access to the I/OBase Address Upper registermay be performed.

IOBASEU is not affected byS_RESET or STOP.

BCR18: Burst Size and Bus Control


Note that all bits in this registerare programmable through theEEPROM PREAD operation.


15-11 CLL Cache Line Length. These bitsare used to determine how oftena cache invalidation cycle needsto be performed when GenerateCache Invalidation Cycles hasbeen activated by setting the

GCIC bit (bit 10 of BCR18) to aone. CLL values are interpretedas multiples of 4 bytes. For ex-ample, a CLL value of 00001bmeans the cache line length is 4bytes and a cache invalidationcycle (assertion of EADS) will beperformed every 4 bytes. A CLLvalue of 00010b means thecache line length is 8 bytes, and acache invalidation cycle will beperformed every 8 bytes. A CLLvalue of 00100 means the cacheline length is 16 bytes. A value of00000 means that the cache linesize is “infinite”. In other words, asingle EADS assertion will beperformed on the first access atthe beginning of each bus mas-tership period (write accessesonly) and no subsequent EADSassertions will be made duringthis bus mastership period.

Cache invalidation cycles areperformed only during PCnet-32controller bus master write ac-cesses.

Some CLL values are reserved(see chart below).

The portion of the Address Busthat will be floated at the time ofan address hold operation(AHOLD asserted) will be deter-mined by the value of the CacheLine Length register. The follow-ing chart lists all of the legal val-ues of CLL showing the portion ofthe Address Bus that will becomefloated during an address holdoperation:

Portion of Address Bus Floated CLL Value During AHOLD

00000 None

00001 A31-A2

00010 A31-A3


00100 A31-A4


01000 A31-A5

01001 –01111 Reserved CLL Values

10000 A31-A6

10001– 11111 Reserved CLL Values

Note that the default value of CLLafter RESET is 00100b. All timingdiagrams in this document are


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drawn with the assumption thatthis is the value of CLL.

When VESA VL-Bus mode is se-lected, then the LEADS pin func-tions as if CLL = 00001bregardless of the actual CLLsetting.

CLL is set to 00100b byH_RESET and is not affected byS_RESET or STOP.

10 GCIC/IWBACK Generate Cache Invalidation Cy-cles. Ignore WBACK signal.

GCIC Generate Cache Invalidation Cy-cles. When this bit is set and theAm486 mode has been selected,then the PCnet-32 controller as-sumes that the host system con-tains a cache, but the hostsystem does not snoop the localbus master accesses of thePCnet-32 controller, and there-fore, that cache invalidation cy-cles must be generated by thePCnet-32 controller for PCnet-32controller master accesses.PCnet-32 controller will not per-form snoops to invalidate cachelines for local bus accesses thatother local bus masters mayhave executed. When GCIC is aZERO, the PCnet-32 controllerassumes that logic in the hostsystem will create the cache in-validation cycles that may benecessary as a result ofPCnet-32 controller local busmaster accesses. The cache in-validation logic performs its func-tions according to the GCIC andCLL bits, regardless of the set-ting of the Am486/Am386 pin.

IWBACK Ignore WBACK signal. When thisbit is set and the VESA VL-BusMode has been selected, thenthe PCnet-32 device will operateas though the WBACK input pinis always held HIGH, eventhough the real value of theWBACK input may change. Thisfunction is provided to allow thePCnet-32 device to operate insystems which violate VESA VL-Bus WBACK operation by eitherfloating this pin or by always driv-ing this pin LOW.

LEADS is always asserted witheach assertion of ADS whenVESA VL-Bus mode has beenselected, regardless of the set-ting of the GCIC/IWBACK bit.

GCIC/IWBACK is cleared byH_RESET and is not affected byS_RESET or STOP.

9 PRPCNET Priority PCnet. This bit is used toset the priority of the daisy chainarbitration logic that resideswithin the PCnet-32 controller.When PRPCNET = 1, the priorityof the daisy chain logic is set toPCnet-32 controller highest pri-ority, External device lowest pri-ority. When PRPCNET = 0, thepriority of the daisy chain logic isset to External device highest pri-ority, PCnet-32 controller lowestpriority. In the case PRPCNET =0, where the PCnet- 32 controllerhas lower priority than the exter-nal device and the PCnet-32 con-troller is preempted due to aHOLDI request from the externaldevice, the PCnet-32 controllerwill complete the current se-quence of accesses and thenpass the HLDA to the externaldevice by asserting the HLDAOsignal. The HOLD output signalfrom the PCnet-32 controller willnot change state during theHLDAO hand-off. If the PCnet-32controller is performing a linearburst, then the PCnet-32 control-ler will complete the linear burstand then pass the HLDA to theexternal device through theHLDAO signal. For more detailson exact timing of preemptionevents, see the individual de-scriptions of the various DMAtransfers.

PRPCNET is cleared byH_RESET and is not affected byS_RESET or STOP.

The default setting for this bit willbe PRPCNET = 0. This defaultvalue reflects the nature of theCPU’s handling of a HOLD re-quest (i.e. the CPU has lowestpriority). By making this the de-fault setting, the PCnet-32 con-troller response to HOLDI is asclose as possible to the timing ofthe CPU response to HOLD, sothat minimal design difficulty willbe created by inserting thePCnet-32 controller into the sys-tem as the mediating device be-tween the CPU and the extensionbus chipset.


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8 RES Reserved bit. Must be written asa ONE. Will be read as a ONE.

This reserved location is SET byH_RESET and is not affected byS_RESET or STOP.

7 DWIO Double Word I/O. When set, thisbit indicates that the PCnet-32controller is programmed forDWIO mode. When cleared, thisbit indicates that the PCnet-32controller is programmed forWord I/O mode. This bit affectsthe I/O Resource Offset map andit affects the defined width of thePCnet-32 controller’s I/O re-sources. See the DWIO and WIOsections for more details.

The PCnet-32 controller will setDWIO if it detects a double wordwrite access to offset 10h fromthe PCnet-32 controller I/O BaseAddress (corresponding to theRDP resource). A double wordwrite access to offset 10h is theonly way that the DWIO bit canbe set. DWIO cannot be set by adirect write to BCR18.

Once the DWIO bit has been setto a ONE, only a H_RESET canreset it to a ZERO.

DWIO is read only by the host.

DWIO is cleared by H_RESETand is not affected by S_RESETor STOP.

6 BREADE Burst Read Enable. When set,this bit enables Linear Burstingduring memory read accesses,where Linear Bursting is definedto mean that only the first transferin the current bus arbitration willcontain an address cycle. Subse-quent transfers will consist ofdata only. However, the entireaddress bus will still be drivenwith appropriate values duringthe subsequent cycles, but ADSwill not be asserted. Whencleared, this bit prevents the partfrom performing linear burstingduring read accesses. In no casewill the part linearly burst a de-scriptor access or an initializationaccess.

BREADE is cleared byH_RESET and is not affected byS_RESET or STOP.

Burst Read activity is not allowedwhen the BCLK frequency is >33MHz. Linear bursting is disabledin VL-Bus systems that operateabove this frequency by connect-

ing the VLBEN pin to either ID(3)(for VL-Bus version 1.0 systems)or ID(4) AND ID(3) AND ID(1)AND ID(0) (for VL-Bus version1.1 or 2.0 systems). InAm486-style systems that haveBCLK frequencies above33 MHz, disabling the linearburst capability is ideally carriedout through EEPROM bit pro-gramming, since the EEPROMprogramming can be setup for aparticular machine’s architec-ture. When the VLBEN pin hasbeen reset to a ZERO, then theBREADE bit will be forced to avalue of ZERO. Any attempt tochange this value by writing tothe BREADE bit location willhave no effect.

5 BWRITE Burst Write Enable. When set,this bit enables Linear Burstingduring memory write accesses,where Linear Bursting is definedto mean that only the first transferin the current bus arbitration willcontain an address cycle. Subse-quent transfers will consist ofdata only. However, the entireaddress bus will still be drivenwith appropriate values duringthe subsequent cycles, but ADSwill not be asserted. Whencleared, this bit prevents the partfrom performing linear burstingduring write accesses. In no casewill the part linearly burst a de-scriptor access or an initializationaccess.

BWRITE is cleared by H_RESETand is not affected by S_RESETor STOP.

Burst Write activity is not allowedwhen the BCLK frequency is >33MHz. Linear bursting is disabledin VL-Bus systems that operateabove this frequency by connect-ing the VLBEN pin to either ID(3)(for VL-Bus version 1.0 systems)or ID(4) AND ID(3) AND ID(1)AND ID(0) (for VL-Bus version1.1 or 2.0 systems). InAm486-style systems that haveBCLK frequencies above 33MHz, disabling the linear burstcapability is ideally carried outthrough EEPROM bit program-ming, since the EEPROM pro-gramming can be setup for aparticular machine’s architec-ture. When the VLBEN pin hasbeen reset to a ZERO, then theBWRITE bit will be forced to a


161Am79C965

value of ZERO. Any attempt tochange this value by writing tothe BWRITE bit location will haveno effect.

4-3 TSTSHDW Test Shadow bits. These bits areused to place the PCnet-32 con-troller into GPSI mode. BCR18[3]must be set to ZERO. The oper-ating modes possible are indi-cated in Table 47.

See Table 48 for pin reconfigura-tion in GPSI mode.


TSTSHDWValue PVALID GPSIEN Operating

(BCR18[4:3]) (BCR19[15]) (CSR124[4]) Mode

00 X 0 NormalOperating

Mode

10 1 X GPSI Mode

01 1 0 Reserved

11 1 X Reserved


Mode

XX 0 1 GPSI Mode

Note that when the GPSI mode isinvoked, only the lower 24 bits ofthe address bus are available.IOAW24 (BCR21[8]) must beset to allow slave operations.During master accesses in GPSImode, the PCnet-32 controller

will not drive the upper 8 bitsof the address bus with addressinformation.

These bits are not writeable, re-gardless of the setting of theENTST bit in CSR4. Values mayonly be programmed to these bitsthrough the EEPROM read op-eration.

BCR18[4:3] are set to 0 byH_RESET and are unaffected byS_RESET or STOP.

2-0 LINBC[2:0] Linear Burst Count. The 3-bitvalue in this register sets the up-per limit for the number of trans-fer cycles in a Linear Burst. Thislimit determines how often thePCnet-32 controller will assertthe ADS signal during linearburst transfers. Each time thatthe interpreted value of LINBCtransfers is reached, thePCnet-32 controller will assertthe ADS signal with a new validaddress. The LINBC valueshould contain only one activebit. LINBC values with more thanone active bit may produce pre-dictable results, but such valueswill not be compatible with futureAMD network controllers. TheLINBC entry is shifted by two bitsbefore being used by thePCnet-32 controller. For exam-ple, the value LINBC[2:0] = 010 isunderstood by the PCnet-32 con-troller to mean 01000 = 8. There-fore, the value LINBC[2:0] = 010will cause the PCnet-32 control-ler to issue a new ADS every












162 Am79C965

01000b = 8 transfers. ThePCnet-32 controller may linearlyburst fewer than the value repre-sented by LINBC, due to otherconditions that cause the burst toend prematurely. Therefore,LINBC should be regarded as anupper limit to the length of linearburst.

Note that linear burst operationwill only begin on certain ad-dresses. The general rule for lin-ear burst starting addresses is:

A[31:0] MOD (LINBC x 16) = 0. Table 49 illustrates all possible

starting address values for all le-gal LINBC values (only 1, 2, and4 are legal; other values are re-served). Note that A[31:8] aredon’t care values for all ad-dresses. (A[1:0] do not existwithin a 32 bit system, however,they are valid bits within thebuffer pointer field of descriptorword 0.)

Table 49. Linear Burst Cycles

Linear Burst Beginning

LBS = Linear AddressesBurst Size Size of (A[31:6] =

(No. of Burst Don’t Care)LINBC[2:0] Transfers) (Byte) A[5:0] =

1 4 16 00, 10, 20, 30

2 8 32 00, 20

4 16 64 00

Due to the beginning address re-strictions just given, it can beshown that some portion of theaddress bus will be held stablethroughout each linear burst se-quence, while the lowest portionof the address bus will changevalue with each new cycle. Theportion of the address bus thatwill be held stable during a linearburst access is given in Table 50.

Table 50. Linear Burst Address Bus

Portion of Address Bus Stable LINBC Value During Linear Burst

001 A[31:4]

010 A[31:5]

100 A[31:6]

The assertion of RDYRTN in theplace of BRDY within a linearburst cycle will cause the linearburst to be interrupted. In that

case, the PCnet-32 controller willrevert to ordinary two-cycletransfers, except that BLAST willremain deasserted to show thatlinear bursting is being requestedby the PCnet-32 controller. Thissituation is defined as interruptedlinear burst cycles. If BRDY issampled as asserted (withoutalso sampling RDYRTN assertedduring the same access) duringinterrupted linear burst cycles,then linear bursting will resume.

There are several events whichmay cause early termination oflinear burst. Among those eventsare: no more data available fortransfer in either a buffer or in theFIFO or if either the Cycle Regis-ter (CSR80) or the Bus ActivityTimer Register (CSR82) timesout. In any of these cases, thePCnet-32 controller will end theLinear Burst by asserting BLASTand then releasing the bus. APartial Linear Burst may havebeen sent out before the asser-tion of BLAST, where “Partial Lin-ear Burst” refers to the casewhere the number of data wordstransferred between the last as-serted ADS and the assertion ofBLAST is less than LINBC.

The value on the address bus willbe updated with appropriate val-ues every clock cycle during lin-ear burst operations, eventhough ADS will not be assertedduring every clock cycle.

Certain combinations of water-mark programming and LINBCprogramming may create situ-ations where no linear bursting ispossible, or where the FIFO maybe excessively read or exces-sively written. Such combina-tions are declared as illegal.



Combinations of watermark andLINBC settings that violate thisrule may cause unexpectedbehavior.

LINBC is set to the value of 001by H_RESET and is not affectedby S_RESET or STOP. Thisgives a default linear burst lengthof 4 transfers = 001 x 4.


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BCR19: EEPROM Control and Status



15 PVALID EEPROM Valid status bit. Thisbit is read only by the host. Avalue of ONE in this bit indicatesthat a PREAD operation has oc-curred, and that 1) there is anEEPROM connected to thePCnet-32 controller microwire in-terface pins and 2) the contentsread from the EEPROM havepassed the checksum verifica-tion operation.

A value of ZERO in this bit indi-cates that the contents of theEEPROM are different from thecontents of the applicablePCnet-32 controller on-boardregisters and/or that the check-sum for the entire 36 bytes ofEEPROM is incorrect or that noEEPROM is connected to themicrowire interface pins.

PVALID is set to ZERO duringH_RESET and is unaffected byS_RESET or the STOP bit. How-ever, following the H_RESET op-eration, an automatic read of theEEPROM will be performed. Justas is true for the normal PREADcommand, at the end of this auto-matic read operation, thePVALID bit may be set to ONE.Therefore, H_RESET will set thePVALID bit to ZERO at first, butthe automatic EEPROM read op-eration may later set PVALID to aONE.

If PVALID becomes ZERO fol-lowing an EEPROM read opera-tion (either automaticallygenerated after H_RESET, or re-quested through PREAD), thenall EEPROM-programmableBCR locations will be reset totheir H_RESET values.

If no EEPROM is present at theEESK, EEDI and EEDO pins,then all attempted PREAD com-mands will terminate early andPVALID will NOT be set. This ap-plies to the automatic read of theEEPROM after H_RESET aswell as to host-initiated PREADcommands.

14 PREAD EEPROM Read command bit.When this bit is set to a ONE bythe host, the PVALID bit

(BCR19[15]) will immediately bereset to a ZERO and then thePCnet-32 controller will performa read operation of 36 bytes fromthe EEPROM through themicrowire interface. TheEEPROM data that is fetchedduring the read will be stored inthe appropriate internal registerson board the PCnet-32 control-ler. Upon completion of theEEPROM read operation, thePCnet-32 controller will assertthe PVALID bit. EEPROM con-tents will be indirectly accessibleto the host through I/O read ac-cesses to the Address PROM(offsets 0h through Fh) andthrough I/O read accesses toother EEPROM programmableregisters. Note that I/O read ac-cesses from these locations willnot actually access the EEPROMitself, but instead will access thePCnet-32 controller’s internalcopy of the EEPROM contents.I/O write accesses to these loca-tions may change the PCnet-32controller register contents, butthe EEPROM locations will notbe affected. EEPROM locationsmay be accessed directlythrough BCR19.

At the end of the read operation,the PREAD bit will automaticallybe reset to a ZERO by thePCnet-32 controller and PVALIDwill bet set, provided that anEEPROM existed on themicrowire interface pins and thatthe checksum for the entire 36bytes of EEPROM was correct.

Note that when PREAD is set to aONE, then the PCnet-32 control-ler will no longer respond to I/Oaccesses directed toward it, untilthe PREAD operation has com-pleted successfully.

If a PREAD command is given tothe PCnet-32 controller but noEEPROM is attached to themicrowire interface pins, then thePREAD command will terminateearly, the PREAD bit will becleared to a ZERO and thePVALID bit will remain reset witha value of ZERO. The PCnet-32controller will then enter Soft-ware Relocatable Mode to awaitfurther programming. This ap-plies to the automatic read of theEEPROM after H_RESET as


164 Am79C965

well as to host initiated PREADcommands. EEPROM program-mable locations on board thePCnet-32 controller will be set totheir default values by such anaborted PREAD operation. Forexample, if the aborted PREADoperation immediately followedthe H_RESET operation, thenthe final state of the EEPROMprogrammable locations will beequal to the H_RESET program-ming for those locations.

If a PREAD command is given tothe PCnet-32 controller and theauto-detection pin (EESK/LED1/SFBD) indicates that noEEPROM is present, then theEEPROM read operation will stillbe attempted.

Note that at the end of the H_RE-SET operation, a read of theEEPROM will be performedautomatically. This H_RESET-generated EEPROM read func-tion will not proceed if theauto-detection pin (EESK/LED1/SFBD) indicates that noEEPROM is present. Instead,Software Relocatable Mode willbe entered immediately.

PREAD is set to ZERO duringH_RESET and is unaffected byS_RESET or STOP.

PREAD is only writeable whenthe STOP bit is set to ONE.

13 EEDET EEPROM Detect. This bit indi-cates the sampled value of the

EESK/LED1/SFBD pin at the endof H_RESET. The value of this bitis independent whether or not anEEPROM is actually present atthe EEPROM interface. It is onlya function of the sampled value ofthe EESK/LEDI/SFBD pin at theend of H_RESET.

The value of this bit is determinedat the end of the H_RESET op-eration. It is unaffected byS_RESET or STOP.

This bit is not writeable. It is readonly.

Table 51 indicates the possiblecombinations of EEDET and theexistence of an EEPROM andthe resulting operations that arepossible on the EEPROMmicrowire interface.

12-5 RES Reserved locations. Written asZERO, read as undefined.

4 EEN EEPROM port enable. When thisbit is set to a one, it causes thevalues of EBUSY, ECS, ESK andEDI to be driven onto theSHFBUSY, EECS, EESK andEEDI pins, respectively. Whenthis bit is reset to a zero, then theSHFBUSY pin will be driven withthe inverse of the PVALID (bit 15of BCR19) value. PVALID is setto “ONE” if the EEPROM readwas successful. It is set to“ZERO” otherwise. If EEN = 0

Table 51. EEDET Effects on EEPROM Operation

EEDET Value EEPROM Result of Automatic EEPROM Read (BCR19[3]) Connected? Result if PREAD is set to ONE Operation Following H_RESET

0 No EEPROM read operation is attempted. First TWO EESK clock cyclesEntire read sequence will occur, are generated, then EEPROMchecksum failure will result, PVALID read operation is aborted and is reset to ZERO. PVALID is reset to ZERO.

0 Yes EEPROM read operation is attempted. First TWO EESK clock cycles are Entire read sequence will occur, generated, then EEPROM read checksum operation will pass, PVALID operation is aborted and PVALID is is set to ONE. reset to ZERO.

1 No EEPROM read operation is attempted. EEPROM read operation is attempted. Entire read sequence will occur, Entire read sequence will occur, checksum failure will result, PVALID checksum failure will result, is reset to ZERO. PVALID is reset to ZERO.

1 Yes EEPROM read operation is attempted. EEPROM read operation is attempted. Entire read sequence will occur, Entire read sequence will occur, checksum operation will pass, PVALID checksum operation will pass, is set to ONE. PVALID is set to ONE.


165Am79C965

and no EEPROM read function iscurrently active, then EECS willbe driven LOW. When EEN = 0and no EEPROM read function iscurrently active, EESK and EEDIpins will be driven by the LEDregisters BCR5 and BCR4, re-spectively. See Table 52.

EEN is set to ZERO byH_RESET and is unaffected byS_RESET or STOP.

3 EBUSY EEPROM BUSY. This bit con-trols the value of the SHFBUSYpin of the PCnet-32 controllerwhen the EEN bit is set to ONEand the PREAD bit is set toZERO. This bit is used to indicateto external EEPROM-program-mable logic that an EEPROM ac-cess is occurring.

When user programming of theEEPROM is desired through theBCR19 EEPROM Port, thenEBUSY should be set to ONEbefore EEN is set to ONE insystems where EEPROM-pro-grammable external logic exists.At the end of the EEPROM pro-gramming operation, EBUSYshould either remain set at ONEuntil after EEN is set to ZERO, orthe user may reset EBUSY toZERO with EEN = 1 immediatelyfollowing a read of EEPROMbyte locations 35 and 36, whichshould be the last accesses per-formed during BCR19 accessesto the EEPROM. A programmedPREAD operation following theBCR19 EEPROM programmingaccesses will cause theSHFBUSY pin to become LOW ifthe EEPROM checksum isverified.

EBUSY has no effect on the out-put value of the SHFBUSY pin

unless the PREAD bit is set toZERO and the EEN bit is set toONE.

EBUSY is set to ZERO byH_RESET and is unaffected byS_RESET or STOP.

2 ECS EEPROM Chip Select. This bit isused to control the value of theEECS pin of the microwire inter-face when the EEN bit is set toONE and the PREAD bit is set toZERO. If EEN = “1” and PREAD= “0” and ECS is set to a ONE,then the EECS pin will be forcedto a HIGH level at the rising edgeof the next BCLK following bitprogramming. If EEN = “1” andPREAD = “0” and ECS is set to aZERO, then the EECS pin will beforced to a LOW level at the risingedge of the next BCLK followingbit programming.

ECS has no effect on the outputvalue of the EECS pin unless thePREAD bit is set to ZERO andthe EEN bit is set to ONE.

ECS is set to ZERO byH_RESET and is unaffected byS_RESET or STOP.

1 ESK EEPROM Serial Clock. This bitand the EDI/EDO bit are used tocontrol host access to theEEPROM. Values programmedto this bit are placed onto theEESK pin at the rising edge of thenext BCLK following bit program-ming, except when the PREADbit is set to ONE or the EEN bit isset to ZERO. If both the ESK bitand the EDI/EDO bit values arechanged during one BCR19 writeoperation, while EEN = 1, thensetup and hold times of the EEDIpin value with respect to theEESK signal edge are notguaranteed.

Table 52. EEPROM Enable

PREAD orReset Auto Read in

Pin Progress EEN EECS SHFBUSY EESK EEDI

High X X 0 1 Z Z

Low 1 X Active 1 Active Active

Low 0 1 From ECS From EBUSY From ESK Bit From EEDI BitBit of BCR19 Bit of BCR19 of BCR19 of BCR19

Low 0 0 0 PVALID LED1 LNKST


166 Am79C965

ESK has no effect on the EESKpin unless the PREAD bit is set toZERO and the EEN bit is set toONE.

ESK is reset to ONE byH_RESET and is unaffected byS_RESET or STOP.

0 EDI/EDO EEPROM Data In / EEPROMData Out. Data that is written tothis bit will appear on the EEDIoutput of the microwire interface,except when the PREAD bit is setto ONE or the EEN bit is set toZERO. Data that is read from thisbit reflects the value of the EEDOinput of the microwire interface.

EDI/EDO has no effect on theEEDI pin unless the PREAD bit isset to ZERO and the EEN bit isset to ONE.

EDI/EDO is reset to ZERO byH_RESET and is unaffected byS_RESET or STOP.

BCR20: Software Style


This register is an alias of the lo-cation CSR58. Accesses to/fromthis register are equivalent to ac-cesses to CSR58.

31-10 RES Reserved locations. Written asZEROs and read as undefined.

9 CSRPCNET CSR PCnet-ISA configurationbit. When set, this bit indicatesthat the PCnet-32 controller reg-ister bits of CSR4 and CSR3 willmap directly to the CSR4 andCSR3 bits of the PCnet-ISA(Am79C960) device. Whencleared, this bit indicates thatPCnet-32 controller register bitsof CSR4 and CSR3 will map di-rectly to the CSR4 and CSR3 bitsof the ILACC (Am79C900)device.

The value of CSRPCNET isdetermined by the PCnet-32 con-troller. CSRPCNET is read onlyby the host.

The PCnet-32 controller uses thesetting of the Software Style reg-ister (BCR20[7:0]) to determinethe value for this bit.

CSRPCNET is set by H_RESETand is not affected by S_RESETor STOP.

8 SSIZE32 Software Size 32 bits. When set,this bit indicates that thePCnet-32 controller utilizes AMD79C900 (ILACC) software struc-tures. In particular, InitializationBlock and Transmit and Receivedescriptor bit maps are affected.When cleared, this bit indicatesthat the PCnet-32 controller util-izes AMD PCnet-ISA softwarestructures. Note: Regardless ofthe setting of SSIZE32, the In-itialization Block must always be-gin on a double-word boundary.

The value of SSIZE32 is deter-mined by the PCnet-32 control-ler. SSIZE32 is read only by thehost.

The PCnet-32 controller uses thesetting of the Software Style reg-ister (BCR20[7:0]/CSR58[7:0])to determine the value for this bit.SSIZE32 is cleared by H_RESETand is not affected by S_RESETor STOP.

If SSIZE32 is reset, then bitsIADR[31:24] of CSR2 will beused to generate values for theupper 8 bits of the 32 bit addressbus during master accesses initi-ated by the PCnet-32 controller.This action is required, since the16-bit software structures speci-fied by the SSIZE32=0 settingwill yield only 24 bits of addressfor PCnet-32 controller bus mas-ter accesses.

If SSIZE32 is set, then the soft-ware structures that are commonto the PCnet-32 controller andthe host system will supply a full32 bits for each address pointerthat is needed by the PCnet-32controller for performing masteraccesses.

The value of the SSIZE32 bit hasno effect on the drive of the upper8 address pins. The upper 8 ad-dress pins are always driven, re-gardless of the state of theSSIZE32 bit.

Note that the setting of theSSIZE32 bit has no effect on thedefined width for I/O resources.I/O resource width is determinedby the state of the DWIO bit.

7-0 SWSTYLE Software Style register. Thevalue in this register determinesthe “style” of I/O and memory


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resources that shall be used bythe PCnet-32 controller. TheSoftware Style selection will af-fect the interpretation of a fewbits within the CSR space andthe width of the descriptors andinitialization block. See Table 53.

All PCnet-32 controller CSR bitsand BCR bits and all descriptor,buffer and initialization block en-tries not cited in the table aboveare unaffected by the SoftwareStyle selection and are thereforealways fully functional as speci-fied in the CSR and BCR and de-scriptor sections.


The SWSTLYE register will con-tain the value 00h followingH_RESET and is not affected byS_RESET or STOP.

BCR21: Interrupt Control


Note that all bits in this registerare programmable through theEEPROM PREAD operation andsoftware relocatable mode.


8 IOAW24 I/O Address Width 24 bits. Whenset to a ONE, the IOAW24 bit willcause the PCnet-32 controller toignore the upper 8 bits of the ad-dress bus when determiningwhether an I/O address matchesPCnet-32 controller I/O space.When IOAW24 is set to a ZERO,then the PCnet-32 controller willexamine all 32 bits of the addressbus when determining whether

an I/O address matchesPCnet-32 controller I/O space.


The IOAW24 bit will be reset toZERO by H_RESET and is notaffected by S_RESET or STOP.

7 REJECTDIS Reject Disable. When set to aONE, the REJECTDIS bit willcause the EAR function of theEADI interface to be disabled.Specifically, the INTR2 pin willretain its function as INTR2 andwill not function as EAR , regard-less of the setting of the BCR2EADISEL bit. When reset to aZERO, the REJECTDIS bit willallow the INTR2 pin to be rede-fined to function as EAR of theEADI interface when theEADISEL bit of BCR2 has beenset to a ONE.


The REJECTDIS bit will be resetto ZERO by H_RESET and is notaffected by S_RESET or STOP.


1-0 INTSEL interrupt Select. The value ofthese bits determines which ofthe interrupt pins will be the ac-tive interrupt. Table 55 indicateswhich interrupt will be selectedfor each combination of INTSELand JTAGSEL values.

Interrupt pins that are not se-lected will be floated.

The INTSEL register will containthe value 00 following H_RESETand is not affected by S_RESETor STOP.


168 Am79C965

Table 53. Software Style Selection

SWSTYLE[7:0](Hex) Style Name CSRPCNET SSIZE32 Altered Bit Interpretations

00 LANCE/ 1 0 ALL CSR4 bits will function as defined in the CSR4 section.PCnet-ISA TMD1[29] functions as ADD_FCS

01 ILACC 0 1 CSR4[9:8], CSR4[5:4] and CSR4[1:0] will have no function, but will be writeable and readable.

CSR4[15:10], CSR4[7:6] and CSR4[3:2] will function as defined in the CSR4 section. TMD1[29] becomes NO_FCS.

02 PCnet-32 1 1 ALL CSR4 bits will function as defined in the CSR4 section. TMD1[29] functions as ADD_FCS

All other Reserved Undefinedcombinations

Table 54. Interrupt Select

SelectedINTSEL[1:0] JTAGSEL interrupt Pin

00 0 INTR1

01 0 INTR2

10 0 INTR3

11 0 INTR4

00 1 INTR1

01 1 INTR2

10 1 INTR1

11 1 INTR2

Initialization BlockWhen SSIZE32=0 (BCR20/CSR58, bit 8) the softwarestructures are defined to be 16 bits wide and the initiali-zation block looks as shown in Table 55. WhenSSIZE32=1, the software structures are defined to be32 bits wide and the initialization block looks as shown inTable 56. Regardless of the value of SSIZE32, the in-itialization block must be aligned to a double wordboundary, i.e. CSR1[1:0] and CSR16[1:0] must be setto ZERO.

Note that the PCnet-32 device performs doubleword ac-cesses to read the initialization block. This statement isalways true, regardless of the setting of the SSIZE32 bit.

Table 55. Initialization Block (when SSIZE = 0)

Address Bits 15-13 Bit 12 Bits 11-8 Bits 7-4 Bits 3-0

IADR+00 MODE 15-00

IADR+02 PADR 15-00

IADR+04 PADR 31-16

IADR+06 PADR 47-32

IADR+08 LADRF 15-00

IADR+0A LADRF 31-16

IADR+0C LADRF 47-32

IADR+0E LADRF 63-48

IADR+10 RDRA 15-00

IADR+12 RLEN 0 RES

IADR+14 TDRA 15-00

IADR+16 TLEN 0 RES TDRA 23-16

RDRA 23-16


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Table 56. Initialization Block (when SSIZE = 1)

Bits Bits Bits Bits Bits Bits Bits Bits Address 31-28 27-24 23-20 19-16 15-12 11-8 7-4 3-0

IADR+00 TLEN RES RLEN RES MODE

IADR+04

IADR+08 RES PADR 47-32

IADR+0C

IADR+10

IADR+14

IADR+18

PADR 31–00

LADR 31–00

LADR 63–32

RDRA 31–00

TDRA 31-00

RLEN and TLENWhen SSIZE32 = 0 (BCR20[8]), then the software struc-tures are defined to be 16 bits wide, and the RLEN andTLEN fields in the initialization block are 3 bits wide, oc-cupying bits 15,14, and 13 and the value in these fieldsdetermines the number of Transmit and Receive De-scriptor Ring Entries (DRE) which are used in the de-scriptor rings. Their meaning is shown in Table 57.

Table 57. Descriptor Ring Entries (SSIZE32 = 0)

R/TLEN No. of DREs

000 1

001 2

010 4

011 8

100 16

101 32

110 64

111 128

If a value other than those listed in the above table isdesired, CSR76 and CSR78 can be written after initiali-zation is complete. See the description of the appropri-ate CSRs.

When SSIZE32=1 (BCR20[8]), then the software struc-tures are defined to be 32 bits wide, and the RLEN andTLEN fields in the initialization block are 4 bits wide, oc-cupying bits 15,14, 13, and 12, and the value in thesefields determines the number of Transmit and ReceiveDescriptor Ring Entries (DRE) which are used in the de-scriptor rings. Their meaning is is shown in Table 58.

If a value other than those listed in the above table isdesired, CSR76 and CSR78 can be written after initiali-zation is complete. See the description of the appropri-ate CSRs.

Table 58. Descriptor Ring Entries (SSIZE = 1)

R/TLEN No. of DREs

0000 1

0001 2

0010 4

0011 8

0100 16

0101 32

0110 64

0111 128

1000 256

1001 512

11XX 512

1X1X 512

RDRA and TDRATDRA and RDRA indicate where the transmit and re-ceive descriptor rings, respectively, begin. Each DREmust be located at 0 MOD 16 address values whenSSIZE32 = 1 (BCR20[8]). Each DRE must be located at0 MOD 8 address values when SSIZE32 = 0(BCR20[8]).

LADRFThe Logical Address Filter (LADRF) is a 64-bit mask thatis used to accept incoming Logical Addresses. If the firstbit in the incoming address (as transmitted on the wire)is a “1”, the address is deemed logical. If the first bit is a“0”, it is a physical address and is compared against thephysical address that was loaded through the initializa-tion block.

A logical address is passed through the CRC generator,producing a 32 bit result. The high order 6 bits of theCRC is used to select one of the 64 bit positions in theLogical Address Filter. If the selected filter bit is set, theaddress is accepted and the frame is placed intomemory. See Figure 38.


170 Am79C965

18219B-44

47 1 0

RECEIVED MESSAGEDESTINATION ADDRESS

1CRCGEN

SEL

31 26 0

MUXMATCH

MATCH

PACKET ACCEPTED

PACKET REJECTED

63 0

6

64

LOGICALADDRESS

FILTER(LADRF)

32-BIT RESULTANT CRC

MATCH MATCH=1: PACKET ACCEPTEDMATCH=0: PACKET REJECTED

Figure 38. Address Match Logic

The Logical Address Filter is used in multicast address-ing schemes. The acceptance of the incoming framebased on the filter value indicates that the message maybe intended for the node. It is the node’s responsibility todetermine if the message is actually intended for thenode by comparing the destination address of the storedmessage with a list of acceptable logical addresses.

If the Logical Address Filter is loaded with all zeroes andpromiscuous mode is disabled, all incoming logical ad-dresses except broadcast will be rejected.

The Broadcast address, which is all ones, does not gothrough the Logical Address Filter and is handled asfollows:

If the Disable Broadcast Bit is cleared, the broadcastaddress is accepted

If the Disable Broadcast Bit is set and promiscuousmode is enabled, the broadcast address is accepted.

If the Disable Broadcast Bit is set and promiscuousmode is disabled, the broadcast address is rejected.

If external loopback is used, the FCS logic must be allo-cated to the receiver (by setting the DXMTFCS bit inCSR15, and clearing the ADD_FCS bit in TMD1) whenusing multicast addressing.

PADRThis 48-bit value represents the unique node addressassigned by the ISO 8802-3 (IEEE/ANSI 802.3) andused for internal address comparison. PADR[0] is thefirst address bit transmitted on the wire, and must bezero. The six hex-digit nomenclature used by the ISO8802-3 (IEEE/ANSI 802.3) maps to the PCnet-32 con-troller PADR register as follows: the first byte comprisesPADR[7:0], with PADR[0] being the least significant bitof the byte. The second ISO 8802-3 (IEEE/ANSI 802.3)byte maps to PADR[15:8], again from LS bit to MS bit,

and so on. The sixth byte maps to PADR[47:40], the LSbit being PADR[40].

MODEThe mode register in the initialization block is copied intoCSR15 and interpreted according to the description ofCSR15.

Receive DescriptorsWhen SSIZE32 = 0 (BCR20[8]), then the software struc-tures are defined to be 16 bits wide, and receive descrip-tors look as shown in Table 59.

Table 59. Receive Descriptor (SSIZE32 = 0)

DescriptorDesignation

Address Bits 15-0 Bits 15-8 Bits 7-0

CRDA+00 RMD0 RMD0[15:0]

CRDA+02 RMD1 RMD1[31:24] RMD0[23:16]



PCnet-32Descriptor Designation

LANCE/PCnet-ISA

PCnet-32 reference names within the table above referto the descriptor definitions given in text below. Sincethe text descriptions are for 32-bit descriptors, the tableabove shows the mapping of the 32-bit descriptors intothe 16-bit descriptor space. Since 16-bit descriptors area subset of the 32-bit descriptors, some portions of the32-bit descriptors may not appear in Table 59.

When SSIZE32 = 1 (BCR 20[8]), then the softwarestructures are defined to be 32 bits wide, and receivedescriptors look as shown in Table 60.


171Am79C965

Table 60. Receive Descriptor (SSIZE32 =1)

PCnet-32Descriptor

Designation

Address Bits 31-24 Bits 23-16 Bits 15-8 Bits 7-0 Bits 31-0

CRDA+00 *NA RMD1[7:0] RMD0[15:8] RMD0[7:0] RMD0

CRDA+04 RMD1[15:8] *NA RMD2[15:8] RMD2[7:0] RMD1

CRDA+08 *NA *NA RMD3[15:8] RMD3[7:0] RMD2

CRDA+0C *NA *NA *NA *NA RMD3

LANCE/PCnet-ISADescriptor Designation

*NA = These 8 bits do not exist in any LANCE descriptor.

The Receive Descriptor Ring Entries (RDREs) are com-posed of four receive message descriptors (RMD0–RMD3). Together they contain the following information:

The address of the actual message data buffer inuser (host) memory.

The length of that message buffer.

Status information indicating the condition of thebuffer. The eight most significant bits of RMD1(RMD1[31:24]) are collectively termed the STATUSof the receive descriptor.

RMD0


31-0 RBADR RECEIVE BUFFER ADDRESS.This field contains the address ofthe receive buffer that is associ-ated with this descriptor.

RMD1


31 OWN This bit indicates that the de-scriptor entry is owned by thehost (OWN=0) or by thePCnet-32 controller (OWN=1).The PCnet-32 controller clearsthe OWN bit after filling the bufferpointed to by the descriptor entry.The host sets the OWN bit afteremptying the buffer. Once thePCnet-32 controller or host hasrelinquished ownership of abuffer, it must not change anyfield in the descriptor entry.

30 ERR ERR is the OR of FRAM, OFLO,CRC, or BUFF. ERR is set by thePCnet-32 controller and clearedby the host.

29 FRAM FRAMING ERROR indicatesthat the incoming frame con-tained a non-integer multiple ofeight bits and there was an FCS

error. If there was no FCS erroron the incoming frame, thenFRAM will not be set even if therewas a non integer multiple ofeight bits in the frame. FRAM isnot valid in internal loopbackmode. FRAM is valid only whenENP is set and OFLO is not.FRAM is set by the PCnet-32controller and cleared by thehost.

28 OFLO OVERFLOW error indicates thatthe receiver has lost all or part ofthe incoming frame, due to an in-ability to store the frame in amemory buffer before the inter-nal FIFO overflowed. OFLO isvalid only when ENP is not set.OFLO is set by the PCnet-32controller and cleared by thehost.

27 CRC CRC indicates that the receiverhas detected a CRC (FCS) erroron the incoming frame. CRC isvalid only when ENP is set andOFLO is not. CRC is set by thePCnet-32 controller and clearedby the host.

26 BUFF BUFFER ERROR is set any timethe PCnet-32 controller does notown the next buffer while datachaining a received frame. Thiscan occur in either of two ways:

1) The OWN bit of the nextbuffer is zero.

2) FIFO overflow occurred be-fore the PCnet-32 controllerreceived the STATUS(RMD1[31:24]) of the next de-scriptor.

If a Buffer Error occurs, an Over-flow Error may also occur inter-nally in the FIFO, but will not bereported in the descriptor statusentry unless both BUFF andOFLO errors occur at the same


172 Am79C965

time. BUFF is set by thePCnet-32 controller and clearedby the host.

25 STP START OF PACKET indicatesthat this is the first buffer used bythe PCnet-32 controller for thisframe. It is used for data chainingbuffers. STP is set by thePCnet-32 controller and clearedby the host.

24 ENP END OF PACKET indicates thatthis is the last buffer used by thePCnet-32 controller for thisframe. It is used for data chainingbuffers. If both STP and ENP areset, the frame fits not one bufferand there is no data chaining.ENP is set by the PCnet-32 con-troller and cleared by the host.

23-16 RES Reserved locations. These loca-tions should be read and writtenas ZEROs.

15-12 ONES These four bits must be writtenas ONES. They are written by thehost and unchanged by thePCnet-32 controller.

11-0 BCNT BUFFER BYTE COUNT is thelength of the buffer pointed to bythis descriptor, expressed as thetwo’s complement of the lengthof the buffer. This field is writtenby the host and unchanged bythe PCnet-32 controller.

RMD2


31-24 RCC Receive Collision Count. Indi-cates the accumulated number ofcollisions on the network sincethe last frame was successfullyreceived, excluding collisionsthat occurred during transmis-sions from this node. ThePCnet-32 controller implementa-tion of this counter may not becompatible with the ILACC RCCdefinition. If network statistics are

to be monitored, then CSR114should be used for the purpose ofmonitoring Receive collisions in-stead of these bits.

23-16 RPC Runt Packet Count. Indicates theaccumulated number of runtsthat were addressed to this nodesince the last time that a receivepacket was successfully re-ceived and its correspondingRMD2 ring entry was written toby the PCnet-32 controller. In or-der to be included in the RPCvalue, a runt must be longenough to meet the minimum re-quirement of the internal addressmatching logic. The minimum re-quirement for a runt to pass theinternal address matchingmechanism is: 18 bits of validpreamble plus a valid SFD de-tected, followed by 7 bytes offrame data. This requirement isunvarying, regardless of the ad-dress matching mechanisms inforce at the time of reception (i.e.physical, logical, broadcast orpromiscuous). The PCnet-32controller implementation of thiscounter may not be compatiblewith the ILACC RPC definition.

15-12 ZEROs This field is reserved. PCnet-32controller will write ZEROs tothese locations.

11-0 MCNT MESSAGE Byte COUNT is thelength in bytes of the receivedmessage, expressed as an un-signed binary integer. MCNT isvalid only when ERR is clear andENP is set. MCNT is written bythe PCnet-32 controller andcleared by the host.

RMD3


31-0 RES Reserved locations. All bits mustbe ZEROs.


173Am79C965

Transmit DescriptorsWhen SSIZE32 = 0 (BCR 20[8]), then the softwarestructures are defined to be 16 bits wide, and transmitdescriptors look as shown in Table 61.

PCnet-32 reference names within the table above referto the descriptor definitions given in text below. Sincethe text descriptions are for 32-bit descriptors, the tableabove shows the mapping of the 32-bit descriptors intothe 16-bit descriptor space. Since 16-bit descriptors area subset of the 32-bit descriptors, some portions of the32-bit descriptors may not appear in Table 61.

When SSIZE32 = 1 (BCR 20[8]), then the softwarestructures are defined to be 32 bits wide, and transmitdescriptors look as shown in Table 62.

Table 61. Transmit Descriptor (SSIZE32 = 0)

LANCEDescriptor

Designation

Address Bits 15-0 Bits 15-8 Bits 7-0

CRDA+00 TMD0 TMD0[15:0]

CRDA+02 TMD1 TMD1[31:24] TMD0[23:16]



PCnet-32Descriptor Designation

Table 62. Transmit Descriptor (SSIZE32 = 1)

PCnet-32Descriptor

Designation

Address Bits 31-24 Bits 23-16 Bits 15-8 Bits 7-0 Bits 31-0

CTDA+00 *NA TMD1[7:0] TMD0[15:8] TMD0[7:0] TMD0

CTDA+04 TMD1[15:8] *NA TMD2[15:8] TMD2[7:0] TMD1

CTDA+08 TMD3[15:8] TMD3[7:0] *NA *NA TMD2

CTDA+0C *NA *NA *NA *NA TMD3

LANCEDescriptor Designation

*NA = These 8 bits do not exist in any LANCE descriptor.

The Transmit Descriptor Ring Entries (TDREs) are com-posed of 4 transmit message descriptors (TMD0-TMD3). Together they contain the following information:

The address of the actual message data buffer inuser or host memory.

The length of the message buffer.

Status information indicating the condition of thebuffer. The eight most significant bits of TMD1(TMD1[31:24]) are collectively termed the STATUSof the transmit descriptor.

TMD0


31-0 TBADR Transmit Buffer address. Thisfield contains the address of thetransmit buffer that is associatedwith this descriptor.

TMD1


31 OWN This bit indicates that the de-scriptor entry is owned by thehost (OWN=0) or by thePCnet-32 controller (OWN=1).

The host sets the OWN bit afterfilling the buffer pointed to by thedescriptor entry. The PCnet-32controller clears the OWN bit af-ter transmitting the contents ofthe buffer. Both the PCnet-32controller and the host must notalter a descriptor entry after it hasrelinquished ownership.

30 ERR ER is the OR of UFLO, LCOL,LCAR, or RTRY. ERR is set bythe PCnet-32 controller andcleared by the host. This bit is setin the current descriptor when theerror occurs, and therefore maybe set in any descriptor of achained buffer transmission.

29 ADD_FCS / Bit 29 functions as ADD_FCSNO_FCS when programmed for the default

I/O style of PCnet-ISA and whenprogrammed for the I/O stylePCnet-32 controller. Bit 29 func-tions as NO_FCS when pro-grammed for the I/O style ILACC.

ADD_FCS ADD_FCS dynamically controlsthe generation of FCS on a frameby frame basis. It is valid only ifthe STP bit is set. WhenADD_FCS is set, the state ofDXMTFCS is ignored and


174 Am79C965

transmitter FCS generation is ac-tivated. When ADD_FCS = 0,FCS generation is controlled byDXMTFCS. ADD_FCS is set bythe host, and unchanged by thePCnet-32 controller. This was areserved bit in the LANCE(Am7990). This function differsfrom the ILACC function for thisbit.

NO_FCS NO_FCS dynamically controlsthe generation of FCS on a frameby frame basis. It is valid only ifthe ENP bit is set. WhenNO_FCS is set, the state ofDXMTFCS is ignored and trans-mitter FCS generation is deacti-vated. When NO_FCS = 0, FCSgeneration is controlled byDXMTFCS. NO_FCS is set bythe host, and unchanged by thePCnet-32 controller. This was areserved bit in the LANCE(Am7990). This function is identi-cal to the ILACC function for thisbit.

28 MORE MORE indicates that more thanone re-try was needed to trans-mit a frame. The value of MOREis written by the PCnet-32 con-troller. This bit has meaning onlyif the ENP bit is set.

27 ONE ONE indicates that exactly onere-try was needed to transmit aframe. ONE flag is not valid whenLCOL is set. The value of theONE bit is written by thePCnet-32 controller. This bit hasmeaning only if the ENP bit is set.

26 DEF DEFERED indicates that thePCnet-32 controller had to deferwhile trying to transmit a frame.This condition occurs if the chan-nel is busy when the PCnet-32controller is ready to transmit.DEF is set by the PCnet-32 con-troller and cleared by the host.

25 STP START OF PACKET indicatesthat this is the first buffer to beused by the PCnet-32 controllerfor this frame. It is used for datachaining buffers. The STP bitmust be set in the first buffer ofthe frame, or the PCnet-32 con-troller will skip over the descriptorand poll the next descriptor(s)until the OWN and STP bits areset.

STP is set by the host and un-changed by the PCnet-32controller.

24 ENP END OF PACKET indicates thatthis is the last buffer to be used bythe PCnet-32 controller for thisframe. It is used for data chainingbuffers. If both STP and ENP areset, the frame fits into one bufferand there is no data chaining.ENP is set by the host andunchanged by the PCnet-32controller.

23-16 RES Reserved locations.

15-12 ONES Must be Ones. This field is writ-ten by the host and unchangedby the PCnet-32 controller.

11-0 BCNT BUFFER BYTE COUNT is theusable length of the bufferpointed to by this descriptor, ex-pressed as the two’s comple-ment of the length of the buffer.This is the number of bytes fromthis buffer that will be transmittedby the PCnet-32 controller. Thisfield is written by the host and un-changed by the PCnet-32 con-troller. There are no minimumbuffer size restrictions.

TMD2


31 BUFF BUFFER ERROR is set by thePCnet-32 controller during trans-mission when the PCnet- 32 con-troller does not find the ENP flagin the current buffer and does notown the next buffer. This can oc-cur in either of two ways:

1. The OWN bit of the nextbuffer is zero.

2. FIFO underflow occurred be-fore the PCnet-32 controllerobtained the STATUS byte(TMD1[31:24]) of the nextdescriptor. BUFF is set by thePCnet-32 controller andcleared by the host. BUFF er-ror will turn off the transmitter(CSR0, TXON = 0).

If a Buffer Error occurs, an Un-derflow Error will also occur.BUFF is not valid when LCOL orRTRY error is set during transmitdata chaining. BUFF is set by thePCnet-32 controller and clearedby the host.

30 UFLO UNDERFLOW ERROR indi-cates that the transmitter hastruncated a message due to datalate from memory. UFLO indi-


175Am79C965

cates that the FIFO has emptiedbefore the end of the frame wasreached. Upon UFLO error, thetransmitter is turned off (CSR0,TXON = 0). UFLO is set by thePCnet-32 controller and clearedby the host.

29 EXDEF EXCESSIVE DEFERRAL. Indi-cates that the transmitter has ex-perienced Excessive Deferral onthis transmit frame, where Ex-cessive Deferral is defined in ISO8802-3 (IEEE/ANSI 802.3) .

28 LCOL LATE COLLISION indicates thata collision has occurred after theslot time of the channel haselapsed. The PCnet-32 control-ler does not re-try on late colli-sions. LCOL is set by thePCnet-32 controller and clearedby the host.

27 LCAR LOSS OF CARRIER is set in AUImode when the carrier is lost dur-ing an PCnet-32 controller-initi-ated transmission. The PCnet-32controller does not re-try uponloss of carrier. It will continue totransmit the whole frame untildone. In 10BASE-T mode LCARwill be set when the T-MAU is inLink Fail state. LCAR is not validin Internal Loopback Mode.LCAR is set by the PCnet-32controller and cleared by thehost.

26 RTRY RETRY ERROR indicates thatthe transmitter has failed after 16attempts to successfully transmita message, due to repeated colli-sions on the medium. If DRTY = 1in the MODE register, RTRY willset after 1 failed transmission at-tempt. RTRY is set by the

PCnet-32 controller and clearedby the host.

25-16 TDR TIME DOMAIN REFLEC-TOMETRY reflects the state ofan internal PCnet-32 controllercounter that counts at a 10 MHzrate from the start of a transmis-sion to the occurrence of a colli-sion or loss of carrier. This valueis useful in determining the ap-proximate distance to a cablefault. The TDR value is written bythe PCnet-32 controller and isvalid only if RTRY is set.

Note that 10 MHz gives very lowresolution and in general has notbeen found to be particularly use-ful. This feature is here primarilyto maintain full compatibility withthe LANCE (Am7990).

15-4 RES Reserved locations.

3-0 TRC TRANSMIT RETRY COUNT. In-dicates the number of transmitretries of the associated packet.The maximum count is 15. How-ever, if a RETRY error occurs,the count will roll over to zero. Inthis case only, the Transmit RetryCount value of zero should be in-terpreted as meaning 16. TRC iswritten by the PCnet-32 control-ler into the last transmit descrip-tor of a frame, or when an errorterminates a frame. Valid onlywhen OWN = 0.

TMD3


31-0 RES Reserved locations. All bits mustbe ZEROs.


176 Am79C965

Register SummaryCSRs — Control and Status Registers

Default Value AfterRAP H_RESETAddr Symbol (Hex) Comments Use

00 CSR0 xxxx 0004 PCnet-32 Controller Status R

01 CSR1 xxxx xxxx Lower IADR: maps to location 16 S

02 CSR2 xxxx xxxx Upper IADR: maps to location 17 S

03 CSR3 xxxx 0000 Interrupt Masks and Deferral Control S

04 CSR4 xxxx 0115 Test and Features Control R

05 CSR5 xxxx 0000 Reserved T

06 CSR6 xxxx xxxx RXTX: RX/TX Descriptor Table Length T


08 CSR8 xxxx xxxx LADR0: Logical Address Filter — LADRF[15:0] T




12 CSR12 xxxx xxxx PADR0: Physical Address Register — PADR[15:0][ T

13 CSR13 xxxx xxxx PADR1: Physical Address Register — PADR[31:16] T

14 CSR14 xxxx xxxx PADR2: Physical Address Register — PADR[47:32] T

15 CSR15 See Register Desc. MODE: Mode Register S

16 CSR16 xxxx xxxx IADR: Base Address of INIT Block Lower (Copy) T

17 CSR17 xxxx xxxx IADR: Base Address of INIT Block Upper (Copy) T

18 CSR18 xxxx xxxx CRBA: Current RCV Buffer Address Lower T

19 CSR22 xxxx xxxx CRBA: Current RCV Buffer Address Upper T

20 CSR20 xxxx xxxx CXBA: Current XMT Buffer Address Lower T

21 CSR21 xxxx xxxx CXBA: Current XMT Buffer Address Upper T

22 CSR22 xxxx xxxx NRBA: Next RCV Buffer Address Lower T

23 CSR23 xxxx xxxx NRBA: Next RCV Buffer Address Upper T

24 CSR24 xxxx xxxx BADR: Base Address of RCV Ring Lower S

25 CSR25 xxxx xxxx BADR: Base Address of RCV Ring Upper S

26 CSR26 xxxx xxxx NRDA: Next RCV Descriptor Address Lower T

27 CSR27 xxxx xxxx NRDA: Next RCV Descriptor Address Upper T

28 CSR28 xxxx xxxx CRDA: Current RCV Descriptor Address Lower T

29 CSR29 xxxx xxxx CRDA: Current RCV Descriptor Address Upper T

30 CSR30 xxxx xxxx BADX: Base Address of XMT Ring Lower S

31 CSR31 xxxx xxxx BADX: Base Address of XMT Ring Upper S

32 CSR32 xxxx xxxx NXDA: Next XMT Descriptor Address Lower T

33 CSR33 xxxx xxxx NXDA: Next XMT Descriptor Address Upper T

34 CSR34 xxxx xxxx CXDA: Current XMT Descriptor Address Lower T

35 CSR35 xxxx xxxx CXDA: Current XMT Descriptor Address Upper T

36 CSR36 xxxx xxxx NNRDA: Next Next Receive Descriptor Address Lower T

Key: x = undefined R = Running Register S = Setup Register T = Test Register


177Am79C965

Register Summary (continued)CSRs — Control and Status Registers


37 CSR37 xxxx xxxx NNRDA: Next Next Receive Descriptor Address Upper T

38 CSR38 xxxx xxxx NNXDA: Next Next Transmit Descriptor Address Lower T

39 CSR39 xxxx xxxx NNXDA: Next Next Transmit Descriptor Address Upper T

40 CSR40 xxxx xxxx CRBC: Current RCV Status and Byte Count Lower T

41 CSR41 xxxx xxxx CRBC: Current RCV Status and Byte Count Upper T

42 CSR42 xxxx xxxx CXBC: Current XMT Status and Byte Count Lower T

43 CSR43 xxxx xxxx CXBC: Current XMT Status and Byte Count Upper T

44 CSR44 xxxx xxxx NRBC: Next RCV Status and Byte Count Lower T

45 CSR45 xxxx xxxx NRBC: Next RCV Status and Byte Count Upper T

46 CSR46 xxxx xxxx POLL: Poll Time Counter T

47 CSR47 xxxx xxxx PI: Polling Interval S

48 CSR48 xxxx xxxx TMP2: Temporary Storage Lower T

49 CSR48 xxxx xxxx TMP2: Temporary Storage Upper T









58 CSR58 See Register Desc. SWS: Software Style S

59 CSR59 xxxx 0105 IR: IR Register T

60 CSR60 xxxx xxxx PXDA: Previous XMT Descriptor Address Lower T

61 CSR61 xxxx xxxx PXDA: Previous XMT Descriptor Address Upper T

62 CSR62 xxxx xxxx PXBC: Previous XMT Status and Byte Count Lower T

63 CSR63 xxxx xxxx PXBC: Previous XMT Status and Byte Count Upper T

64 CSR64 xxxx xxxx NXBA: Next XMT Buffer Address Lower T

65 CSR65 xxxx xxxx NXBA: Next XMT Buffer Address Upper T

66 CSR66 xxxx xxxx NXBC: Next XMT Status and Byte Count Lower T

67 CSR67 xxxx xxxx NXBC: Next XMT Status and Byte Count Upper T

68 CSR68 xxxx xxxx XSTMP: XMT Status Temporary Storage Lower T

69 CSR69 xxxx xxxx XSTMP: XMT Status Temporary Storage Upper T

70 CSR70 xxxx xxxx RSTMP: RCV Status Temporary Storage Lower T

71 CSR71 xxxx xxxx RSTMP: RCV Status Temporary Storage Upper T

72 CSR72 xxxx xxxx RCVRC: RCV Ring Counter T



178 Am79C965



73 CSR73 xxxx xxxx Reserved T

74 CSR74 xxxx xxxx XMTRC: XMT Ring Counter T


76 CSR76 xxxx xxxx RCVRL: RCV Ring Length S


78 CSR78 xxxx xxxx XMTRL: XMT Ring Length S


80 CSR80 xxxx E810 Burst and FIFO Threshold Control S


82 CSR82 xxxx 0000 DMABAT: Bus Acitivty Timer S


84 CSR84 xxxx xxxx DMABA: DMA Address Lower T

85 CSR85 xxxx xxxx DMABA: DMA Address Upper T

86 CSR86 xxxx xxxx DMABC: Buffer Byte Counter T


88 CSR88 0243 0003 Chip ID Lower T

89 CSR89 xxxx 0243 Chip ID Upper T



92 CSR92 xxxx xxxx RCON: Ring Length Conversion T


94 CSR94 xxxx 0000 XMTTDR: Transmit Time Domain Reflectometry Count T


96 CSR96 xxxx xxxx SCR0: BIU Scratch Register 0 Lower T

97 CSR97 xxxx xxxx SCR0: BIU Scratch Register 0 Upper T

98 CSR98 xxxx xxxx SCR1: BIU Scratch Register 1 Lower T

99 CSR99 xxxx xxxx SCR1: BIU Scratch Register 1 Upper T

100 CSR100 xxxx 0200 Bus Time-Out S




104 CSR104 xxxx xxxx SWAP: Swap Register Lower T

105 CSR105 xxxx xxxx SWAP: Swap Register Upper T



108 CSR108 xxxx xxxx BMSCR: BMU Scratch Register Lower T

109 CSR109 xxxx xxxx BMSCR: BMU Scratch Register Upper T



179Am79C965





112 CSR112 xxxx 0000 Missed Frame Count R


114 CSR114 xxxx 0000 Receive Collision Count R








122 CSR122 See Register Desc. Receive Frame Alignment Control S


124 CSR124 See Register Desc. BMU Test T






180 Am79C965

Register Summary (continued)BCR — Bus Configuration Registers

RAP DefaultAddr. Mnemonic (Hex) Name User EEPROM SRM

0 MSRDA 0005 Master Mode Read Active No No No

1 MSWRA 0005 Master Mode Write Active No No No

2 MC N/A* Miscellaneous Configuration Yes Yes Yes

3 Reserved N/A No No No

4 LNKST 00C0 Link Status (Default) Yes No No

5 LED1 0084 Receive (Default) Yes No No

6 LED2 0088 Receive Polarity (Default) Yes No No

7 LED3 0090 Transmit (Default) Yes No No

8–15 Reserved N/A No No No

16 IOBASEL N/A* I/O Base Address Lower Yes Yes Yes

17 IOBASEU N/A* I/O Base Address Upper Yes Yes Yes

18 BSBC 2101 Burst Size and Bus Control Yes Yes No

19 EECAS 0002 EEPROM Control and Status Yes No No

20 SWSTYLE 0000 Software Style Yes No No

21 INTCON N/A* Interrupt Control Yes Yes Yes

Key: SRM = Software Relocatable Mode

* Registers marked with an asterisk (*) have no default value, since they are not observable without first being programmed,either through the EEPROM read operation or through the Software Relocatable Mode. Therefore, the only observable val-ues for these registers are those that have been programmed and a default value is not applicable.

Programmability


181Am79C965

ABSOLUTE MAXIMUM RATINGSStorage Temperature –65°C to +150°C. . . . . . . . . . .

Ambient Temperature Under Bias –65°C to +125°C. . . . . . . . . . . . . . . . . . .

Supply Voltage to AVssor DVSS (AVDD, DVDD) –0.3 V to +6.0 V. . . . . . . . . . .

Stresses above those listed under Absolute Maximum Rat-ings may cause permanent device failure. Functionality at orabove these limits is not implied. Exposure to Absolute Maxi-mum Ratings for extended periods may affect device reliabil-ity. Programming conditions may differ.

OPERATING RANGESCommercial (C) Devices

Temperature (TA) 0°C to +70°C. . . . . . . . . . . . . . . . .

Supply Voltages(AVDD, DVDD) 5 V ±5%. . . . . . . . . . . . . . . . . . . . . . . .

All inputs within the range: AVSS – 0.5 V ≤ Vin ≤. . . . . AVDD + 0.5 V, or

DVSS – 0.5 V ≤ Vin ≤DVDD + 0.5 V

Operating ranges define those limits between which the func-tionality of the device is guaranteed.

DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwisespecifiedParameter Symbol Parameter Description Test Conditions Min Max Unit

Digital Input Voltage

VIL Input LOW Voltage 0.8 V

VIH Input HIGH Voltage 2.0 V

Digital Ouput Voltage

VOL Output LOW Voltage IOL1 = 8 mA, IOL2 = 4 mA 0.45 V(Notes 1 and 5)

VOH Output HIGH Voltage (Note 2) IOH = –4 mA (Note 5) 2.4 V

Digital Input Leakage Current

IIX Input Leakage Current (Note 3) VDD = 5 V, VIN = 0 V –10 10 µA

Digital Ouput Leakage Current

IOZL Output Low Leakage VOUT = 0 V –10 µACurrent (Note 4)

IOZH Output High Leakage VOUT = VDD 10 µACurrent (Note 4)

Crystal Input

VILX XTAL1 Input LOW VIN = External Clock –0.5 0.8 VThreshold Voltage

VILHX XTAL1 Input HIGH VIN = External Clock VDD–0.8 VDD + 0.5 V Threshold Voltage


IIAXD Input Current at DI+ –1 V < VIN < AVDD +0.5 V –500 +500 µA and DI–

IIAXC Input Current at –1 V < VIN < AVDD +0.5 V –500 +500 µACI+ and CI–

VAOD Differential Output Voltage RL = 78 Ω 630 1200 mV |(DO+)–(DO–)|

VAODOFF Transmit Differential Output RL = 78 Ω (Note 9) –40 +40 mV Idle Voltage

Active

Sleep

Active

Sleep

IILX XTAL1 Input LOW Current

IIHX XTAL1 Input HIGH Current

VIN = 0 V

VIN = VDD

0

–10 +10

µA

µA

120

400

µA

µA

–120

0


182 Am79C965

DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwisespecified (continued)Parameter Symbol Parameter Description Test Conditions Min Max Unit

Attachment Unit Interface (Continued)

IAODOFF Transmit Differential RL = 78 Ω (Note 8) –1 +1 mA Output Idle Current

VCMT Transmit Output Common RL = 78 Ω 2.5 AVDD V Mode Voltage

VODI DO± Transmit Differential RL = 78 Ω (Note 7) 25 mV Output Voltage Imbalance

VATH Receive Data Differential –35 35 mV Input Threshold

VASQ DI± and CI± Differential –275 –160 mV Input Threshold (Squelch)

VIRDVD DI± and CI± Differential –1.5 +1.5 V Mode Input Voltage Range

VICM DI± and CI± Input Bias IIN = 0 mA AVDD–3.0 AVDD–1.0 V Voltage

VOPD DO± Undershoot Voltage at (Note 9) –100 mV Zero Differential on Transmit Return to Zero (ETD)


IIRXD Input Current at RXD± AVSS < VIN < AVDD –500 500 µA

RRXD RXD± Differential Input 10 KΩ Resistance

VTIVB RXD+, RXD– Open Circuit IIN = 0 mA AVDD – 3.0 AVDD – 1.5 V Input Voltage (Bias)

VTIDV Differential Mode Input AVDD = 5 V –3.1 +3.1 V Voltage Range (RXD±)

VTSQ+ RXD Positive Squelch Sinusoid Threshold (Peak) 5 MHz ≤ f ≤10 MHz 300 520 mV

VTSQ– RXD Negative Squelch Sinusoid Threshold (Peak) 5 MHz ≤ f ≤10 MHz –520 –300 mV

VTHS+ RXD Post-Squelch Sinusoid Positive Threshold (Peak) 5 MHz ≤ f ≤10 MHz 150 293 mV

VTHS– RXD Post-Squelch Sinusoid Negative Threshold (Peak) 5 MHz ≤ f ≤10 MHz –293 –150 mV

VLTSQ+ RXD Positive Squelch LRT = LOW 180 312 mV Threshold (Peak)

VLTSQ– RXD Negative Squelch LRT = LOW –312 –180 mV Threshold (Peak)

VLTHS+ RXD Post-Squelch Positive LRT = LOW 90 176 mV Threshold (Peak)

VLTHS– RXD Post-Squelch LRT = LOW –176 –90 mV Negative Threshold (Peak)


183Am79C965

DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwisespecified (continued)Parameter Symbol Parameter Description Test Conditions Min Max Unit

Twisted Pair Interface (continued)

VRXDTH RXD Switching Threshold (Note 4) –35 35 mV

VTXH TXD± and TXP± Output DVSS = 0 V DVDD – 0.6 DVDD V HIGH Voltage

VTXL TXD± and TXP± Output DVDD = +5 V DVSS DVSS + 0.6 V LOW Voltage

VTXI TXD± and TXP± –40 +40 mV Differential Output Voltage Imbalance

VTXOFF TXD± and TXP± Idle 40 mV Output Voltage

RTX TXD± Differential Driver (Note 4) 40 Ω Output Impedance

TXP± Differential Driver (Note 4) 80 Ω Output Impedance

IEEE 1149.1 (JTAG) Test Port

VIL TCK, TMS, TDI 0.8 V

VIH TCK, TMS, TDI 2.0 V

VOL TDO IOL = 2.0 mA 0.4 V

VOH TDO IOH = –0.4 mA 2.4 V

IIL TCK, TMS, TDI VDD = 5.5 V, VI = 0.5 V –200 µA

IIH TCK, TMS, TDI VDD =5.5 V, VI = 2.7V –100 µA

IOZ TDO VOUT = 0 V, VOUT = VDD –10 +10 µA

Power Supply Current

IDD Active Power Supply Current XTAL1 = 20 MHz 100 mA

IDDCOMA Coma Mode Power SLEEP active 200 µASupply Current

IDDSNOOZE Snooze Mode Power AWAKE bit set active 10 mASupply Current

Pin Capacitance

CIN Input Pin Capacitance FC = 1 MHz (Note 6) 10 pF

CO I/O or Output Pin Capacitance FC = 1 MHz (Note 6) 10 pF

CCLK BCLK Pin Capacitance FC = 1 MHz (Note 6) 10 pF

Notes:

1. IOL1 = 8 mA applies to all output and I/O pins except HOLD and LDEV. IOL2 = 4 mA applies to HOLD and LDEV only.

2. VOH does not apply to open-drain output pins.

3. IIX applies to all input only pins except DI±, CI±, and XTAL1.

4. IOZL and IOZH apply to all three-state output pins and bi-directional pins.

5. Outputs are CMOS and will be driven to rail if the load is not resistive.

6. Parameter not tested; value determined by characterization.

7. Tested, but to values in excess of limits. Test accuracy not sufficient to allow screening guard bands.

8. Correlated to other tested parameters – not tested directly.

9. Test not implemented to data sheet specification.


184 Am79C965

SWITCHING CHARACTERISTICS: BUS INTERFACETest Conditions

Parameter (CL = 50 pF Symbol Parameter Description Unless Otherwise Noted) Min Max Unit

Clock Timing

CLK Frequency 1 33 MHz

t1 CLK Period 30 1000 ns

t2 CLK High time @ 2.0 V 14 ns

t3 CLK Low Time @ 0.8 V 14 ns

t4 CLK Fall Time 2.0 V to 0.8 V (Note 1) 3 ns

t5 CLK Rise Time 0.8 V to 2.0 V (Note 1) 3 ns

Output and Float Delay Timing

t6 A2–A31, BE0-BE3, M/IO, D/C, 3 12 nsW/R, ADS, HOLD, HLDAO, INTR, EADS, RDY Valid Delay

t7 A2–A31, BE0-BE3, M/IO, D/C, 18 nsW/R, ADS, RDY Float Delay

t8 ns

t8a BLAST Valid Delay 3 12 ns

t9 BLAST Float Delay 18 ns

t10 D0–D31 Data Valid Delay 3 12 ns

t11 D0–D31 Data Float Delay 18 ns

t12 (This symbol is not used)

t13 (This symbol is not used)

Setup and Hold Timing

t14 LBS16 Setup time 5 ns

t15 LBS16 Hold Time 2 ns

t16 BRDY, RDYRTN Setup Time 5 ns

t17 BRDY, RDYRTN Hold Time 2 ns

t18 HOLDI, AHOLD, HLDA, SLEEP 6 nsSetup Time

t18a BOFF Setup Time 8 ns

t19 HOLDI, BOFF, AHOLD, HLDA, 2 nsSLEEP Hold Time

t20 RESET, CLKRESET 5 nsSetup Time

t21 RESET, CLKRESET 2 nsHold Time

t22 D0–D31, A2–A31, BE0-BE3, 4 nsADS, M/IO, D/C, W/R Setup Time

t23 D0–D31, A2–A31, BE0-BE3, 2 nsADS, M/IO, D/C, W/R Hold Time


185Am79C965

SWITCHING CHARACTERISTICS: BUS INTERFACE (continued)Test Conditions

Parameter (CL = 50 pF Symbol Parameter Description Unless Otherwise Noted) Min Max Unit

JTAG (IEEE 1149.1) Test Signal Timing

t24 TCK Frequency 10 MHz

t25 TCK Period 100 ns

t26 TCK High Time @ 2.0 V 45 ns

t27 TCK Low Time @ 0.8 V 45 ns

t28 TCK Rise Time 4 ns

t29 TCK Fall Time 4 ns

t30 TDI, TMS Setup Time 16 ns

t31 TDI, TMS Hold Time 10 ns

t32 TDO Valid Delay 3 60 ns

t33 TDO Float Delay 50 ns

t34 All Outputs (Non-Test) 3 25 nsValid Delay

t35 All Outputs (Non-Test) 36 nsFloat Delay

t36 All Inputs (Non-Test)) 8 nsSetup Time

t37 All Inputs (Non-Test) Hold Time 7 ns

LDEV Timing

t38 ADS Asserted to LDEV 20 nsAsserted

t39 LDEV Valid Pulse Width tBCLK

Data Bus Activation Timing (Slave)

t40 Data Bus Driven After ADS 1 BCLKSampled Asserted

HOLD Inactive Timing

t41 HOLD Deasserted to HOLD 2 BCLK –15 nsAsserted

EEPROM Timing

t42 EESK Frequency (Note 2) 650 kHz

t43 EESK HIGH Time (Note 2) 780 ns

t44 EESK LOW Time (Note 2) 780 ns

t45 EECS, EEDI, SHFBUSY (Note 2) –15 +15 nsValid Output Delay from EESK

t46 EECS LOW Time (Note 2) 1550 ns

t47 EEDO Setup Time to EESK 50 ns

t48 EEDO Hold Time to EESK 0 ns

Notes:1. Not 100% tested; guaranteed by design characterization.

2. Parameter value is given for automatic EEPROM read operation. When EEPROM port (BCR19) is used to access theEEPROM, software is responsible for meeting EEPROM timing requirements.


186 Am79C965

SWITCHING CHARACTERISTICS: 10BASE-T INTERFACEParameter

Symbol Parameter Description Test Conditions Min Max Unit

Transmit Timing

tTETD Transmit Start of Idle 250 350 ns

tTR Transmitter Rise Time (10% to 90%) 5.5 ns

tTF Transmitter Fall Time (90% to 10%) 5.5 ns

tTM Transmitter Rise and FallTime Mismatch 1 ns

tPERLP Idle Signal Period 8 24 ms

tPWLP Idle Link Pulse Width (Note 1) 75 120 ns

tPWPLP Predistortion Idle Link Pulse (Note 1) 45 55 nsWidth

tJA Transmit Jabber Activation Time 20 150 ms

tJR Transmit Jabber Reset Time 250 750 ms

tJREC Transmit Jabber Recovery Time 1.0 µs(minimum time gap between transmitted frames to prevent jabber activation)

Receive Timing

tPWNRD RXD Pulse Width Not to Turn VIN > VTHS (min) 136 – nsOff Internal Carrier Sense

tPWROFF RXD Pulse Width to Turn Off VIN > VTHS (min) 200 ns

tRETD Receive Start of Idle 200 ns

tRCVON RCV Asserted Delay TRON - 50 TRON + 100 ns

tRCVOFF RCV De-Asserted Delay 20 62 ms

Collision Detection and SQE Test

tCOLON COL Asserted Delay 750 900 ns

tCOLOFF COL De-Asserted Delay 20 62 ms

Note:1. Not tested; parameter guaranteed by characterization.


187Am79C965

SWITCHING CHARACTERISTICS: AUI

Notes:

1. DI pulses narrower than tPWODI (min) will be rejected; pulses wider than tPWODI (max) will turn internal DI carrier sense on.

2. DI pulses narrower than tPWKDI (min) will maintain internal DI carrier sense on; pulses wider than tPWKDI (max) will turninternal DI carrier sense off.

3. CI pulses narrower than tPWOCI (min) will be rejected; pulses wider than tPWOCI (max) will turn internal CI carrier sense on.

4. CI pulses narrower than tPWKCI (min) will maintain internal CI carrier sense on; pulses wider than tPWKCI (max) will turninternal CI carrier sense off.

ParameterSymbol Parameter Description Test Conditions Min Max Unit

AUI Port

tDOTR DO+,DO- rise time (10% to 90%) 2.5 5.0 ns

tDOTF DO+,DO- fall time (90% to 10%) 2.5 5.0 ns

tDORM DO+,DO- rise and fall time mismatch – 1.0 ns

tDOETD DO+/- End of Transmission 200 375 ns

tPWODI DI pulse width accept/reject |VIN| > |VASQ| 15 45 nsthreshold (Note 1)

tPWKDI DI pulse width maintain/turn-off |VIN| > |VASQ| 136 200 nsthreshold (Note 2)

tPWOCI CI pulse width accept/reject |VIN| > |VASQ| 10 26 nsthreshold (Note 3)

tPWKCI CI pulse width maintain/turn-off |VIN| > |VASQ| 90 160 nsthreshold (Note 4)

Internal MENDEC Clock Timing

tX1 XTAL1 period VIN = External Clock 49.995 50.005 ns

tX1H XTAL1 HIGH pulse width VIN = External Clock 20 ns

tX1L XTAL1 LOW pulse width VIN = External Clock 20 ns

tX1R XTAL1 rise time VIN = External Clock 5 ns

tX1F XTAL1 fall time VIN = External Clock 5 ns


188 Am79C965

SWITCHING CHARACTERISTICS: GPSI

Notes:1. CLSN must be asserted for a continuous period of 110 nsec or more. Assertion for less than 110 nsec period may or may

not result in CLSN recognition.

2. RXCRS should meet jitter requirements of IEEE 802.3 specification.

3. CLSN assertion before 51.2 µsec will be indicated as a normal collision. CLSN assertion after 51.2 µsec will beconsidered as a Late Receive Collision.

ParameterSymbol Parameter Description Test Conditions Min Max Unit

Transmit Timing

tGPT1 STDCLK period (802.3 Compliant) 99.99 100.01 ns

tGPT2 STDCLK High Time 40 60 ns

tGPT3 TXDAT and TXEN delay from ↑ STDCLK 0 70 ns

tGPT4 RXCRS setup before ↑ STDCLK (Last Bit) 210 ns

tGPT5 RXCRS hold after ↓ TXEN 0 ns

tGPT6 CLSN active time to trigger collision (Note 1) 110 ns

tGPT7 CLSN active to ↓ RXCRS to prevent 0 nsLCAR assertion

tGPT8 CLSN active to ↓ RXCRS for SQE 0 4.0 µsHearbeat Window

tGPT9 CLSN active to ↑ RXCRS for normal collision 0 51.2 µs

Receive Timing

tGPR1 SRDCLK period (Note 2) 80 120 ns

tGPR2 SRDCLK High Time (Note 2) 30 80 ns

tGPR3 SRDCLK Low Time (Note 2) 30 80 ns

tGPR4 RXDAT and RXCRS setup to ↑ SRDCLK 15 ns

tGPR5 RXDAT hold after ↑ SRDCLK 15 ns

tGPR6 RXCRS hold after ↓ SRDCLK 0 ns

tGPR7 CLSN active to first ↑ SRDCLK (Collision Recognition) 0 ns

tGPR8 CLSN active to ↑ SRDCLK for (Note 3) 51.2 µsAddress Type Designation Bit

tGPR9 CLSN setup to last ↑ SRDCLK for 210 nsCollision Recognition

tGPR10 CLSN active 110 ns

tGPR11 CLSN inactive setup to first ↑ SRDCLK 300 ns

tGPR12 CLSN inactive hold to last ↑ SRDCLK 300 ns


189Am79C965

SWITCHING CHARACTERISTICS: EADIParameter Symbol Parameter Description Test Conditions Min Max Unit

tEAD1 SRD setup to ↑ SRDCLK 40 ns

tEAD2 SRD hold to ↑ SRDCLK 40 ns

tEAD3 SF/BD change to ↓ SRDCLK –15 +15 ns

tEAD4 EAR deassertion to ↑ 50 nsSRDCLK (first rising edge)

tEAD5 EAR assertion after SFD 0 51,090 nsevent (packet rejection)

tEAD6 EAR assertion 110 ns


190 Am79C965

KEY TO SWITCHING WAVEFORMS

KS000010

Must BeSteady

MayChangefrom H to L

MayChangefrom L to H

Does Not Apply

Don’t CareAny ChangePermitted

Will BeSteady

Will BeChangingfrom H to L

Will Be Changing from L to H

ChangingStateUnknown

Center Line is HighImpedance“Off” State

WAVEFORM INPUTS OUTPUTS

SWITCHING TEST CIRCUITS

CL

VTHRESHOLD

IOL

IOH

Normal and Three-State Outputs

18219B-46

Sense Point


191Am79C965

SWITCHING TEST CIRCUITS

AVDD

DO+

154 Ω100 pF

DO–

AVSS

52.3 Ω

Test Point

18219B-47

AUI DO Switching Test Circuit

DVDD

TXD+

294 Ω100 pF

TXD–

DVSS

294 Ω

Test Point

Includes TestJig Capacitance

18219B-48

TXD Switching Test Circuit

DVDD

TXP+

715 Ω100 pF

TXP–

DVSS

715 Ω

Test Point

Includes TestJig Capacitance

18219B-49

TXP Outputs Test Circuit


192 Am79C965

ESTIMATED OUTPUT VALID DELAY VS. LOAD CAPACITANCENote that this graph represents change in output delayfor estimated conditions.

MAX+4

Notes: This graph will not be linear outside of the CL range shown.

MAX = maximum value given in A.C. characteristics table.

MAX+2

MAX+6

MAX

MAX–2

Max

imum

out

put d

elay

(ns

)

50

CL (pF)

75 100 125 15025

18219B-50

Output Delay Versus Load Capacitance Under Estimated Conditions

SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE

18219B-51

BCLK0.8V1.5V2.0V

t2

t4

t1

t5

t3

0.8V

BCLK Waveform


193Am79C965


18219B-52

BCLK

t10

A2-A31, BE0-BE3, M/IO,D/C, W/R, ADS,

HOLD, HLDAO, INTR,RDY, EADS

Tx Tx Tx

Min Max

Valid n Valid n+1

D0-D31

Min Max

Valid n Valid n+1

t6

t8a

BLAST

Min Max

Valid n Valid n+1

Output Valid Delay Timing

18219B-53

BCLK

t10

A2-A31, BE0-BE3, M/IO,D/C, W/R, ADS

Tx Tx Tx

Min

Valid n

D0-D31 Valid n

t6

t8a

BLAST Valid n

t7

Min

Mint9

t11

Maximum Float Delay Timing


194 Am79C965


BCLK

t15

LBS16

t14

HOLDI, AHOLD,HLDA, SLEEP

RESET,CLKRESET

A2-A31, BE0-BE3,ADS, D/C,M/IO, W/R

t18

Tx Tx

t19

t20 t21

t22 t23

BOFF

t18a t1918219B-54

Input Setup and Hold Timing

18219B-55

BCLK

t23

D0-D31

T2 Tx

RDY,BRDY,

RDYRTN

t22

t16 t17

Ready and Data Setup and Hold Timing


195Am79C965


18219B-56

TCK0.8V1.5V2.0V

t26

t29

t25

t28

t27

0.8V

JTAG (IEEE 1149.1) TCK Waveform

Figure 27: Test signal timing.

TCK

TDI, TMS

TDO

t31

OutputSignals

t25

t30

t32

t34

t37t36

InputSignals

t35t35

t33

18219B-57

JTAG (IEEE 1149.1) Test Signal Timing


196 Am79C965


18219B-58

BCLK

t38

ADS

Tx Tx Tx

LDEV

Min Max

A2-A31, BE0-BE3,M/IO, D/C, W/R, RDY Valid PCnet-32 Address

t39

D0-D31 Valid PCnet-32 Data

t40

LDEV Timing and Data Bus Activation Timing

18219B-59

BCLK

HLDA

Tx Tx Tx

HOLD

t41

HOLD Inactive Timing


197Am79C965


18219B-60

EECS

EESK

EEDI

SHFBUSY

EEDO

0 1 1 0 A5 A4 A3 A2 A1 A0

D15 D14 D13 D2 D3 D0

Falling transition on SHFBUSY after 17th word read if thechecksum adjust byte in byte 1Fh of EEPROM is correct.

Automatic EEPROM Read Functional Timing

18219B-61

EESK

t44t43

t45

t47

t48

EEDO Stable

EEDI

SHFBUSY

EECS

t46

Automatic EEPROM Read Timing


198 Am79C965

SWITCHING WAVEFORMS: 10BASE-T INTERFACE

TXD+

TXP+

TXD–

TXP–

XMT

tTR tTF

tTETD

18219B-62

Transmit Timing

TXD+

tPERLPtPWLP

tPWPLP

TXP+

TXD–

TXP–

18219B-63

Idle Link Test Pulse


199Am79C965

SWITCHING WAVEFORMS: 10BASE-T INTERFACE

RXD±

VTSQ+

VTSQ–

VTHS–

VTHS+

18219B-64

Receive Thresholds (LRT = 0)

RXD±

VLTSQ+

VLTSQ–

VLTHS–

VLTHS+

18219B-65

Receive Thresholds (LRT = 1)


200 Am79C965

SWITCHING WAVEFORMS: AUI

tXI

tDOTR tDOTF

tX1H

tX1L tX1F tX1R

1 1

0

1

XTAL1

ISTDCLK(Note 1)

ITXDAT+(Note 1)

DO+

DO–

DO±

0

1

1

ITXEN(Note 1)

18219B-66

Note 1:Internal signal and is shown for clarification only.

Transmit Timing—Start of Packet

Typical > 200 nstDOETD

XTAL1

ISTDCLK(Note 1)

ITXEN(Note 1)

ITXDAT+(Note 1)

DO+

DO–

DO±

0

1

0

01 0

Bit (n–2) Bit (n–1) Bit (n)

1

18219B-67


Transmit Timing—End of Packet (Last Bit = 0)


201Am79C965


Typical > 250 nstDOETD

XTAL1

ITXEN(Note 1)

ITXDAT+(Note 1)

DO+

DO–

DO±

0

1 1

01

Bit (n–2) Bit (n–1) Bit (n)

1

ISTDCLK(Note 1)

18219B-68


Transmit Timing—End of Packet (Last Bit = 1)


202 Am79C965


DI+/–

VASQ

tPWODI

tPWKDI

tPWKDI

18219B-69

Receive Timing Diagram

CI+/–

VASQ

tPWOCItPWKCI

tPWKCI

18219B-70

Collision Timing Diagram

tDOETD

DO+/–40 mV

100 mV max.0 V

80 Bit Times18219B-71

Port DO ETD Waveform


203Am79C965

SWITCHING WAVEFORMS: GPSI

Transmit Clock

(STDCLK)

Transmit Data

(TXDAT)

Transmit Enable (TXEN)

Carrier Present

(RXCRS)(Note 1)

Collision(CLSN)

(Note 2)

(First Bit Preamble)

tGPT1tGPT2

tGPT3

tGPT3 tGPT3

tGPT7 tGPT8

tGPT9 tGPT6

tGPT5

(Last Bit )

Notes:1. If RXCRS is not present during transmission, LCAR bit in TMD2 will be set.

2. If CLSN is not present during or shortly after transmission, CERR in CSR0 will be set.

tGPT4

18219B-72

Transmit Timing

Receive Clock

(SRDCLK)

(First Bit Preamble) (Address Type Designation Bit) (Last Bit)tGPR1

tGPR2 tGPR3

tGPR4 tGPR5 tGPR5

tGPR6

tGPR7

tGPR8 tGPR9

tGPR10

tGPR11tGPR12

(No Collision)

Receive Data

(RXDAT)

Carrier Present

(RXCRS)

Collision (CLSN),

Active

Collision (CLSN),Inactive

tGPR4

18219B-73

Receive Timing


204 Am79C965

SWITCHING WAVEFORMS: EADI

EAR

SRDCLK

SRD

SF/BDtEAD4

tEAD1tEAD2

One Zero One SFD Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 8 Bit 0 Bit 7 Bit 8

tEAD3 tEAD3

tEAD5tEAD6

Preamble Data Field

Reject

Accept

18219B-74

EADI Reject Timing

A-1Am79C965

PCnet-32 Compatible MediaInterface Modules

APPENDIX A

PCnet-32 COMPATIBLE 10BASE-TFILTERS AND TRANSFORMERSThe table below provides a sample list of PCnet-32compatible 10BASE-T filter and transformer modules

available from various vendors. Contact the respectivemanufacturer for a complete and updated listing ofcomponents.

Filters Filters Filters Filtersand Transformers Transformers Transformers

Manufacturer Part No. Package Transformers and Choke Dual Choke Dual Chokes

Bel Fuse A556-2006-DE 16-pin 0.3” DIL √

Bel Fuse 0556-2006-00 14-pin SIP √

Bel Fuse 0556-2006-01 14-pin SIP √

Bel Fuse 0556-6392-00 16-pin 0.5” DIL √

Halo Electronics FD02-101G 16-pin 0.3” DIL √



PCA Electronics EPA1990A 16-pin 0.3” DIL √

PCA Electronics EPA2013D 16-pin 0.3” DIL √

PCA Electronics EPA2162 16-pin 0.3” SIP √

Pulse Engineering PE-65421 16-pin 0.3” DIL √

Pulse Engineering PE-65434 16-pin 0.3” SIL √

Pulse Engineering PE-65445 16-pin 0.3” DIL √

Pulse Engineering PE-65467 12-pin 0.5” SMT √

Valor Electronics PT3877 16-pin 0.3” DIL √

Valor Electronics FL1043 16-pin 0.3” DIL √

PCnet-32 Compatible AUI IsolationTransformersThe table below provides a sample list of PCnet-32compatible AUI isolation transformers available from

various vendors. Contact the respective manufacturerfor a complete and updated listing of components.

Manufacturer Part No. Package Description

Bel Fuse A553-0506-AB 16-pin 0.3” DIL 50 µH

Bel Fuse S553-0756-AE 16-pin 0.3” SMD 75 µH

Halo Electronics TD01-0756K 16-pin 0.3” DIL 75 µH

Halo Electronics TG01-0756W 16-pin 0.3” SMD 75 µH

PCA Electronics EP9531-4 16-pin 0.3” DIL 50 µH

Pulse Engineering PE64106 16-pin 0.3” DIL 50 µH

Pulse Engineering PE65723 16-pin 0.3” SMT 75 µH

Valor Electronics LT6032 16-pin 0.3” DIL 75 µH

Valor Electronics ST7032 16-pin 0.3” SMD 75 µH

AMD

A-2 Am79C965

PCnet-32 Compatible DC/DC ConvertersThe table below provides a sample list of PCnet-32compatible DC/DC converters available from various

vendors. Contact the respective manufacturer for acomplete and updated listing of components.

Manufacturer Part No. Package Voltage Remote On/Off

Halo Electronics DCU0-0509D 24-pin DIP 5/-9 No

Halo Electronics DCU0-0509E 24-pin DIP 5/-9 Yes

PCA Electronics EPC1007P 24-pin DIP 5/-9 No

PCA Electronics EPC1054P 24-pin DIP 5/-9 Yes

PCA Electronics EPC1078 24-pin DIP 5/-9 Yes

Valor Electronics PM7202 24-pin DIP 5/-9 No

Valor Electronics PM7222 24-pin DIP 5/-9 Yes

MANUFACTURER CONTACTINFORMATIONContact the following companies for further infor-mation on their products:

Bel Fuse Phone: (201) 432-0463 852-328-5515 33-1-69410402FAX: (201) 432-9542 852-352-3706 33-1-69413320

Halo Electronics Phone: (415) 969-7313 65-285-1566FAX: (415) 367-7158 65-284-9466

PCA Electronics Phone: (818)-892-0761 852-553-0165 33-1-44894800(HPC in Hong Kong) FAX: (818)-894-5791 852-873-1550 33-1-42051579

Pulse Engineering Phone: (619) 674-8100 852-425-1651 353-093-24107FAX: (619) 675-8262 852-480-5974 353-093-24459

Valor Electronics Phone: (619) 537-2500 852-513-8210 49-89-6923122FAX: (619) 537-2525 852-513-8214 49-89-6926542

Company U.S. and Domestic Asia Europe

B-1Am79C965

Recommendation for Power andGround Decoupling

APPENDIX B

The mixed analog/digital circuitry in the PCnet-32 makeit imperative to provide noise-free power and groundconnections to the device. Without clean power andground connections, a design may suffer from high biterror rates or may not function at all. Hence, it is highlyrecommended that the guidelines presented here arefollowed to ensure a reliable design.

Decoupling/Bypass Capacitors: Adequate decouplingof the power and ground pins and planes is required byall PCnet-32 designs. This includes both low-frequencybulk capacitors and high frequency capacitors. It is rec-ommended that at least one low-frequency bulk (e.g.22 µF) decoupling capacitor be used in the area of thePCnet-32 device. The bulk capacitor(s) should be con-nected directly to the power and ground planes. In addi-tion, at least 8 high frequency decoupling capacitors(e.g. 0.1 µF multilayer ceramic capacitors) should beused around the periphery of the PCnet-32 device toprevent power and ground bounce from affecting deviceoperation. To reduce the inductance between the powerand ground pins and the capacitors, the pins should beconnected directly to the capacitors, rather than throughthe planes to the capacitors. The suggested connectionscheme for the capacitors is shown in the figure below.Note also that the traces connecting these pins to thecapacitors should be as wide as possible to reduce in-ductance (15 mils is desirable).

PCnet

Vdd

Vss

CAP

CAP

PCnet

Vdd

Vss

CAP

PCnet

Vdd

Vss

Via to the Power Plane

Via to the Ground Plane

Correct Correct Incorrect

The most critical pins in the layout of a PCnet-32 designare the 4 analog power and 2 analog ground pins,AVDD[1-4] and AVSS[1-2], respectively. All of thesepins are located in one corner of the device, the “analogcorner”. Specific functions and layout requirements ofthe analog power and ground pins are given below.

AVSS1 and AVDD3: These pins provide the power andground for the Twisted Pair and AUI drivers. In additionAVSS1 serves as the ground for the logic interfaces inthe 20 MHz Crystal Oscillator. Hence, these pins can bevery noisy. A dedicated 0.1 µF capacitor between thesepins is recommended.

AVSS2 and AVDD2: These pins are the most criticalpins on the PCnet-32 device because they provide thepower and ground for the phase-lock loop (PLL) portionof the chip. The voltage-controlled oscillator (VCO) por-tion of the PLL is sensitive to noise in the 60 kHz –200 kHz range. To prevent noise in this frequency rangefrom disrupting the VCO, it is strongly recommendedthat the low-pass filter shown below be implemented onthese pins.

VDD plane33 µF to 10 µF

AVDD2

AVSS2

PCnetTM

1 Ω to 10 Ω

VSS plane

To determine the value for the resistor and capacitor,the formula is:

R * C ≥ 88

where R is in ohms and C is in microfarads. Some possi-ble combinations are given below. To minimize the volt-age drop across the resistor, the R value should not bemore than 10 Ω.

2.7 Ω 33 µF

4.3 Ω 22 µF

6.8 Ω 15 µF

10 Ω 10 µF

R C

AMD

B-2 Am79C965

AVSS2 and AVDD2/AVDD4: These pins provide powerand ground for the AUI and twisted pair receive circuitry.In addition, as mentioned earlier, AVSS2 and AVDD2provide power and ground for the phase-lock loop por-tion of the chip. Except for the filter circuit alreadymentioned, no specific decoupling is necessary onthese pins.

AVDD1: AVDD1 provides power for the control and in-terface logic in the PLL. Ground for this logic is providedby digital ground pins. No specific decoupling is neces-sary on this pin.

Special Note for Adapter Cards: In adapter card de-signs, it is important to utilize all available power andground pins available on the bus edge connector. In ad-dition, the connection from the bus edge connector tothe power or ground plane should be made throughmore than one via and with wide traces (15 mils desir-able) wherever possible. Following these recommenda-tions results in minimal inductance in the power andground paths. By minimizing this inductance, groundbounce is minimized.

C-1Appendix C

APPENDIX C

Alternative Methodfor Initialization

The PCnet-32 controller may be initialized by perform-ing I/O writes only. That is, data can be written directly tothe appropriate control and status registers (CSR)instead of reading from the Initialization Block inmemory. The registers that must be written are shown inthe table below. These books are followed by writing theSTART bit in CSR0.

Control and Status Register Comment

CSR8 LADRF[15:0]

CSR9 LADRF[31:16]

CSR10 LADRF[47:32]

CSR11 LADRF[63:48]

CSR12 PADR[15:0]

CSR13 PADR[31:16]

CSR14 PADR[47:32]

CSR15 Mode

CSR24-25 BADR

CSR30-31 BADX

CSR47 POLLINT

CSR76 RCVRL

CSR78 XMTRL

Note: The INIT bit must not be set or the initialization block willbe accessed instead.

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Introduction of the Look-Ahead Packet Processing (LAPP) Concept

APPENDIX D

A driver for the PCnet-32 controller would normally re-quire that the CPU copy receive frame data from thecontroller’s buffer space to the application’s bufferspace after the entire frame has been received by thecontroller. For applications that use a ping-pong win-dowing style, the traffic on the network will be halteduntil the current frame has been completely processedby the entire application stack. This means that the timebetween last byte of a receive frame arriving at theclient’s Ethernet controller and the client’s transmissionof the first byte of the next outgoing frame will be sepa-rated by:

1) the time that it takes the client’s CPU’s interruptprocedure to pass software control from the currenttask to the driver

2) plus the time that it takes the client driver to passthe header data to the application and request anapplication buffer

3) plus the time that it takes the application to gener-ate the buffer pointer and then return the bufferpointer to the driver

4) plus the time that it takes the client driver to transferall of the frame data from the controller’s bufferspace into the application’s buffer space and thencall the application again to process the completeframe

5) plus the time that it takes the application to processthe frame and generate the next outgoing frame

6) plus the time that it takes the client driver to set upthe descriptor for the controller and then write aTDMD bit to CSR0

The sum of these times can often be about the same asthe time taken to actually transmit the frames on thewire, thereby yielding a network utilization rate of lessthan 50%.

An important thing to note is that the PCnet-32 control-ler’s data transfers to its buffer space are such that thesystem bus is needed by the PCnet-32 controller forapproximately 4% of the time. This leaves 96% of thesytem bus bandwidth for the CPU to perform some ofthe inter–frame operations in advance of the completionof network receive activity, if possible. The questionthen becomes: how much of the tasks that need to beperformed between reception of a frame andtransmission of the next frame can be performed before

the reception of the frame actually ends at the network,and how can the CPU be instructed to perform thesetasks during the network reception time?

The answer depends upon exactly what is happening inthe driver and application code, but the steps that can beperformed at the same time as the receive dataare arriving include as much as the first three steps andpart of the fourth step shown in the sequenceabove. By performing these steps before the entireframe has arrived, the frame throughput can be sub-stantially increased.

A good increase in performance can be expected whenthe first three steps are performed before the end of thenetwork receive operation. A much more significant per-formance increase could be realized if the PCnet-32controller could place the frame data directly into theapplication’s buffer space; (i.e. eliminate the need forstep four.) In order to make this work, it is necessarythat the application buffer pointer be determined beforethe frame has completely arrived, then the buffer pointerin the next desriptor for the receive frame would need tobe modified in order to direct the PCnet-32 controller towrite directly to the application buffer. More details onthis operation will be given later.

An alternative modification to the existing system cangain a smaller, but still significant improvement in per-formance. This alternative leaves step four unchangedin that the CPU is still required to perform the copyoperation, but it allows a large portion of the copy opera-tion to be done before the frame has been completelyreceived by the controller, (i.e. the CPU can perform thecopy operation of the receive data from the PCnet-32controller’s buffer space into the application bufferspace before the frame data has completely arrivedfrom the network.) This allows the copy operation ofstep four to be performed concurrently with the arrival ofnetwork data, rather than sequentially, following the endof network receive activity.

Outline of the LAPP Flow:This section gives a suggested outline for a driver thatutilizes the LAPP feature of the PCnet-32 controller.

Note: The labels in the following text are used as refer-ences in the timeline diagram that follows.

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SETUP:The driver should set up descriptors in groups of 3, withthe OWN and STP bits of each set of three descriptors toread as follows: 11b, 10b, 00b.

An option bit (LAPPEN) exists in CSR3, bit position 5.The software should set this bit. When set, the LAPPENbit directs the PCnet-32 controller to generate anINTERRUPT when STP has been written to a receivedescriptor by the PCnet-32 controller.

FLOW:The PCnet-32 controller polls the current receive de-scriptor at some point in time before a message arrives.The PCnet-32 controller determines that this receivebuffer is OWNed by the PCnet-32 controller and it storesthe descriptor information to be used when a messagedoes arrive.

N0: Frame preamble appears on the wire, followed bySFD and destination address.

N1: The 64th byte of frame data arrives from the wire.This causes the PCnet-32 controller to begin framedata DMA operations to the first buffer.

C0: When the 64th byte of the message arrives, thePCnet-32 controller performs a lookahead opera-tion to the next receive descriptor. This descriptorshould be owned by the PCnet-32 controller.

C1: The PCnet-32 controller intermittently requests thebus to transfer frame data to the first buffer as it ar-rives on the wire.

S0: The driver remains idle.

C2: When the PCnet-32 controller has completely filledthe first buffer, it writes status to the first descriptor.

C3: When the first descriptor for the frame has beenwritten, changing ownership from the PCnet-32controller to the CPU, the PCnet-32 controller willgenerate an SRP INTERRUPT. (This interrupt ap-pears as a RINT interrupt in CSR0.)

S1: The SRP INTERRUPT causes the CPU to switchtasks to allow the PCnet-32 controller’s driver torun.

C4: During the CPU interrupt–generated task switch-ing, the PCnet-32 controller is performing alookahead operation to the third descriptor. At thispoint in time, the third descriptor is owned by theCPU. [Note: Even though the third buffer is notowned by the PCnet-32 controller, existing AMDEthernet controllers will continue to perform dataDMA into the buffer space that the controller al-ready owns (i.e. buffer number 2). The controllerdoes not know if buffer space in buffer number 2will be sufficient or not, for this frame, but it has noway to tell except by trying to move the entire mes-sage into that space. Only when the message

does not fit will it signal a buffer error condition –there is no need to panic at the point that it discov-ers that it does not yet own descriptor number 3.]

S2: The first task of the driver’s interrupt service routineis to collect the header information from thePCnet-32 controller’s first buffer and pass it to theapplication.

S3: The application will return an application bufferpointer to the driver. The driver will add an offset tothe application data buffer pointer, since thePCnet-32 controller will be placing the first portionof the message into the first and second buffers.(The modified application data buffer pointer willonly be directly used by the PCnet-32 controllerwhen it reaches the third buffer.) The driver willplace the modified data buffer pointer into the finaldescriptor of the group (#3) and will grant owner-ship of this descriptor to the PCnet-32 controller.

C5: Interleaved with S2, S3 and S4 driver activity, thePCnet-32 controller will write frame data to buffernumber 2.

S4: The driver will next proceed to copy the contents ofthe PCnet-32 controller’s first buffer to the begin-ning of the application space. This copy will be tothe exact (unmodified) buffer pointer that waspassed by the application.

S5: After copying all of the data from the first buffer intothe beginning of the application data buffer, thedriver will begin to poll the ownership bit of the sec-ond descriptor. The driver is waiting for thePCnet-32 controller to finish filling the secondbuffer.

C6: At this point, knowing that it had not previouslyowned the third descriptor, and knowing that thecurrent message has not ended (there is more datain the fifo), the PCnet-32 controller will make a “lastditch lookahead” to the final (third) descriptor; Thistime, the ownership will be TRUE (i.e. the descrip-tor belongs to the controller), because the driverwrote the application pointer into this descriptorand then changed the ownership to give the de-scriptor to the PCnet-32 controller back at S3. Notethat if steps S1, S2 and S3 have not completed atthis time, a BUFF error will result.

C7: After filling the second buffer and performing thelast chance lookahead to the next descriptor, thePCnet-32 controller will write the status andchange the ownership bit of descriptor number 2.

S6: After the ownership of descriptor number 2 hasbeen changed by the PCnet-32 controller, the nextdriver poll of the 2nd descriptor will show owner-ship granted to the CPU. The driver now copies thedata from buffer number 2 into the “middle section”

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of the application buffer space. This operation is in-terleaved with the C7 and C8 operations.

C8: The PCnet-32 controller will perform data DMA tothe last buffer, whose pointer is pointing to applica-tion space. Data entering the last buffer will notneed the infamous “double copy” that is required byexisting drivers, since it is being placed directly intothe application buffer space.

N2: The message on the wire ends.

S7: When the driver completes the copy of buffer num-ber 2 data to the application buffer space, it beginspolling descriptor number 3.

C9: When the PCnet-32 controller has finished all dataDMA operations, it writes status and changes own-ership of descriptor number 3.

S8: The driver sees that the ownership of descriptornumber 3 has changed, and it calls the applicationto tell the application that a frame has arrived.

S9: The application processes the received frame andgenerates the next TX frame, placing it into a TXbuffer.

S10:The driver sets up the TX descriptor for thePCnet-32 controller.

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Buffer#1

EthernetControlleractivity:

Softwareactivity:

Buffer#2

Buffer#3

S0: Driver is idle.

C1: Controller is performing intermittent bursts of DMA to fill data buffer #1.

EthernetWire

activity:

N0: Packet preamble, SFD and destination address are arriving.

C3: SRP interrupt is generated.


S1: Interrupt latency.

S3: Driver writes modified application pointer to descriptor #3.


N1: 64th byte of packet data arrives.

S4: Driver copies data from buffer #1 to the application buffer.

S5: Driver polls descriptor #2.

S7: Driver polls descriptor of buffer #3.

S8: Driver calls application to tell application that packet has arrived.


C9: Controller writes descriptor #3.

C0: Lookahead to descriptor #2.


S2: Driver call to application to get application buffer pointer.

S9: Application processes packet, generates TX packet.

S10: Driver sets up TX descriptor.

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C4: Lookahead to descriptor #3 (OWN).

C6: "Last chance" lookahead to descriptor #3 (OWN).


N2: EOM

Figure 1. LAPP Timeline

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LAPP Software RequirementsSoftware needs to set up a receive ring with descriptorsformed into groups of 3. The first descriptor of eachgroup should have OWN = 1 and STP = 1, the seconddescriptor of each group should have OWN = 1 and STP= 0. The third descriptor of each group should haveOWN = 0 and STP = 0. The size of the first buffer (asindicated in the first descriptor), should be at least equalto the largest expected header size; However, for maxi-mum efficiency of CPU utilization, the first buffer sizeshould be larger than the header size. It should be equalto the expected number of message bytes, minus thetime needed for Interrupt latency and minus the applica-tion call latency, minus the time needed for the driver towrite to the third descriptor, minus the time needed forthe driver to copy data from buffer #1 to the applicationbuffer space, and minus the time needed for the driver tocopy data from buffer #2 to the application buffer space.Note that the time needed for the copies performed bythe driver depends upon the sizes of the 2nd and 3rdbuffers, and that the sizes of the second and third buff-ers need to be set accoring to the time needed for thedata copy operations! This means that an iterative self–adjusting mechanism needs to be placed into the soft-ware to determine the correct buffer sizing for optimaloperation. Fixed values for buffer sizes may be used; Insuch a case, the LAPP method will still provide a signifi-cant performance increase, but the performance in-crease will not be maximized.

The following diagram illustrates this setup for a receivering size of 9:

LAPP Rules for Parsing of DescriptorsWhen using the LAPP method, software must use amodified form of descriptor parsing as follows:

Software will examine OWN and STP to determinewhere a RCV frame begins. RCV frames will only beginin buffers that have OWN = 0 and STP = 1.

Software shall assume that a frame continues until itfinds either ENP = 1 or ERR= 1.

Software must discard all descriptors with OWN = 0 andSTP = 0 and move to the next descriptor when searchingfor the beginning of a new frame; ENP and ERR shouldbe ignored by software during this search.

Software cannot change an STP value in the receivedescriptor ring after the initial setup of the ring is com-plete, even if software has ownership of the STP de-scriptor unless the previous STP descriptor in the ring isalso OWNED by the software.

When LAPPEN = 1, then hardware will use a modifiedform of descriptor parsing as follows:

The controller will examine OWN and STP to determinewhere to begin placing a RCV frame. A new RCV framewill only begin in a buffer that has OWN = 1 and STP = 1.

The controller will always obey the OWN bit for deter-mining whether or not it may use the next buffer for achain.

The controller will always mark the end of a frame witheither ENP = 1 or ERR= 1.

OWN = 1 STP = 1SIZE = A-(S1+S2+S3+S4+S6)

Descriptor#1

OWN = 1 STP = 0SIZE = S1+S2+S3+S4

Descriptor#2

OWN = 0 STP = 0SIZE = S6

Descriptor#3

OWN = 1 STP = 1Descriptor#4

OWN = 1Descriptor#5

Descriptor#6


OWN = 1Descriptor#8

Descriptor#9

OWN = 0 STP = 0

OWN = 0 STP = 0

STP = 0

STP = 0

A = Expected message size in bytesS1 = Interrupt latencyS2 = Application call latencyS3 =Time needed for driver to write to third descriptorS4 = Time needed for driver to copy data from buffer #1 to application buffer spaceS6 = Time needed for driver to copy data from buffer #2 to application buffer space

Note that the times needed for tasks S1,S2, S3, S4, and S6 should be divided by0.8 microseconds to yield an equivalentnumber of network byte times beforesubtracting these quantities from theexpected message size A.

SIZE = A-(S1+S2+S3+S4+S6)

SIZE = S1+S2+S3+S4

SIZE = S6

SIZE = A-(S1+S2+S3+S4+S6)

SIZE = S1+S2+S3+S4

SIZE = S6

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Figure 2. LAPP 3 Buffer Grouping

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The controller will discard all descriptors with OWN = 1and STP = 0 and move to the next descriptor whensearching for a place to begin a new frame . It dis-cards these desciptors by simply changing the owner-ship bit from OWN=1 to OWN = 0. Such a descriptor isunused for receive purposes by the controller, and thedriver must recognize this. (The driver will recognizethis if it follows the software rules.)

The controller will ignore all descriptors with OWN = 0and STP = 0 and move to the next descriptor whensearching for a place to begin a new frame . In otherwords, the controller is allowed to skip entries in the ringthat it does not own, but only when it is looking for aplace to begin a new frame.

Some Examples of LAPP DescriptorInteractionChoose an expected frame size of 1060 bytes.

Choose buffer sizes of 800, 200 and 200 bytes.

1) Assume that a 1060 byte frame arrives correctly,and that the timing of the early interrupt and thesoftware is smooth. The descriptors will havechanged from:

Before the After theDescriptor Frame Arrived Frame has Arrived Comments

Number OWN STP ENP* OWN STP ENP* (After Frame Arrival)

1 1 1 X 0 1 0 Bytes 1–800

2 1 0 X 0 0 0 Bytes 801–1000

3 0 0 X 0 0 1 Bytes 1001–1060

4 1 1 X 1 1 X Controller’s current location

5 1 0 X 1 0 X Not yet used


etc. 1 1 X 1 1 X Not yet used

*ENP or ERR

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2) Assume that instead of the expected 1060 byteframe, a 900 byte frame arrives, either becausethere was an error in the network, or because this isthe last frame in a file transmission sequence.



1 1 1 X 0 1 0 Bytes 1–800

2 1 0 X 0 0 1 Bytes 801–900

3 0 0 X 0 0 ?** Discarded buffer





*ENP or ERR

** Note that the PCnet-32 controller might write a ZERO to ENP location in the 3rd descriptor. Here are the two possibilities:

1) If the controller finishes the data transfers into buffer number 2 after the driver writes the application’s modified buffer pointerinto the third descriptor, then the controller will write a ZERO to ENP for this buffer and will write a ZERO to OWN and STP.

2) If the controller finishes the data transfers into buffer number 2 before the driver writes the application’s modified bufferpointer into the third descriptor, then the controller will complete the frame in buffer number two and then skip the then un-owned third buffer. In this case, the PCnet-32 controller will not have had the opportunity to RESET the ENP bit in this de-scriptor, and it is possible that the software left this bit as ENP=1 from the last time through the ring. Therefore, the softwaremust treat the location as a don’t care; The rule is, after finding ENP=1 (or ERR=1) in descriptor number 2, the software mustignore ENP bits until it finds the next STP=1.

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3) Assume that instead of the expected 1060 byteframe, a 100 byte frame arrives, because therewas an error in the network, or because this is thelast frame in a file transmission sequence, or per-haps because it is an acknowledge frame.



1 1 1 X 0 1 1 Bytes 1–100

2 1 0 X 0 0 0*** Discarded buffer

3 0 0 X 0 0 ?** Discarded buffer





*ENP or ERR

** Same as note in case 2 above, except that in this case, it is very unlikely that the driver can respond to the interrupt and get thepointer from the application before the PCnet-32 controller has completed its poll of the next descriptors. This means that foralmost all occurrences of this case, the PCnet-32 controller will not find the OWN bit set for this descriptor and therefore, theENP bit will almost always contain the old value, since the PCnet-32 controller will not have had an opportunity to modify it.

*** Note that even though the PCnet-32 controller will write a ZERO to this ENP location, the software should treat the location asa don’t care, since after finding the ENP=1 in descriptor number 2, the software should ignore ENP bits until it finds the nextSTP=1.

Buffer Size TuningFor maximum performance, buffer sizes should be ad-justed depending upon the expected frame size and thevalues of the interrupt latency and application call la-tency. The best driver code will minimize the CPU utili-zation while also minimizing the latency from frame endon the network to frame sent to application from driver(frame latency). These objectives are aimed at increas-ing throughput on the network while decreasing CPUutilization.

Note that the buffer sizes in the ring may be altered atany time that the CPU has ownership of the correspond-ing descriptor. The best choice for buffer sizes willmaximize the time that the driver is swapped out, whileminimizing the time from the last byte written by thePCnet-32 controller to the time that the data is passedfrom the driver to the application. In the diagram, thiscorresponds to maximizing S0, while minimizing thetime between C9 and S8. (The timeline happens toshow a minimal time from C9 to S8.)

Note that by increasing the size of buffer number 1, weincrease the value of S0. However, when we increasethe size of buffer number 1, we also increase the valueof S4. If the size of buffer number 1 is too large, then thedriver will not have enough time to perform tasks S2, S3,S4, S5 and S6. The result is that there will be delay fromthe execution of task C9 until the execution of task S8. A

perfectly timed system will have the values for S5 andS7 at a minimum.

An average increase in performance can be achieved ifthe general guidelines of buffer sizes in figure 2 is fol-lowed. However, as was noted earlier, the correct sizingfor buffers will depend upon the expected message size.There are two problems with relating expected messagesize with the correct buffer sizing:

1) Message sizes cannot always be accurately pre-dicted, since a single application may expect differ-ent message sizes at different times, therefore, thebuffer sizes chosen will not always maximizethroughput.

2) Within a single application, message sizes mightbe somewhat predicatable, but when the samedriver is to be shared with multiple applications,there may not be a common predictable messagesize.

Additional problems occur when trying to define the cor-rect sizing because the correct size also depends uponthe interrupt latency, which may vary from system tosystem, depending upon both the hardware and thesoftware installed in each system.

In order to deal with the unpredictable nature of themessage size, the driver can implement a self tuning

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mechanism that examines the amount of time spent intasks S5 and S7 as such: While the driver is polling foreach descriptor, it could count the number of poll opera-tions performed and then adjust the number 1 buffersize to a larger value, by adding “t” bytes to the buffercount, if the number of poll operations was greater than“x”. If fewer than “x” poll operations were needed foreach of S5 and S7, then the software should adjust thebuffer size to a smaller value by, subtracting “y” bytesfrom the buffer count. Experiments with such a tuningmechanism must be performed to determine the bestvalues for “X” and “y.”

Note whenever the size of buffer number 1 is adjusted,buffer sizes for buffer number 2 and buffer 3 should alsobe adjusted.

In some systems the typical mix of receive frames on anetwork for a client application consists mostly of largedata frames, with very few small frames. In this case, formaximum efficiency of buffer sizing, when a frame ar-rives under a certain size limit, the driver should notadjust the buffer sizes in response to the short frame.

An Alternative LAPP Flow – the TWO InterruptMethodAn alternative to the above suggested flow is to use twointerrupts, one at the start of the Receive frame and theother at the end of the receive frame, instead of justlooking for the SRP interupt as was described above.This alternative attempts to reduce the amount of timethat the software “wastes” while polling for descriptorown bits. This time would then be available for otherCPU tasks. It also minimizes the amount of time theCPU needs for data copying. This savings can be ap-plied to other CPU tasks.

The time from the end of frame arrival on the wire todelivery of the frame to the application is labeled asframe latency. For the one-interrupt method, frame la-tency is minimized, while CPU utilization increases. Forthe two-interrupt method, frame latency becomesgreater, while CPU utilization decreases.

Note that some of the CPU time that can be applied tonon-Ethernet tasks is used for task switching in theCPU. One task switch is required to swap a non-Ethernet task into the CPU (after S7A) and a secondtask switch is needed to swap the Ethernet driver back inagain (at S8A). If the time needed to perform these taskswitches exceeds the time saved by not polling descrip-tors, then there is a net loss in performance with thismethod. Therefore, the SPRINT method implementedshould be carefully chosen.

Figure 3 shows the event flow for the two-interruptmethod.

Figure 4 shows the buffer sizing for the two-interruptmethod. Note that the second buffer size will be aboutthe same for each method.

There is another alternative which is a marriage of thetwo previous methods. This third possibility would usethe buffer sizes set by the two-interrupt method, butwould use the polling method of determining frame end.This will give good frame latency but at the price of veryhigh CPU utilization.

And still, there are even more compromise positions thatuse various fixed buffer sizes and effectively, the flow ofthe one-interrupt method. All of these compromises willreduce the complexity of the one-interrupt method byremoving the heuristic buffer sizing code, but they allbecome less efficient than heuristic code would allow.

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Buffer#1

EthernetControlleractivity:

Softwareactivity:

Buffer#2

Buffer#3

S0: Driver is idle.


EthernetWire

activity:

N0: Packet preamble, SFD and destination address are arriving.

C3: SRP interrupt is generated.


S1: Interrupt latency.

S3: Driver writes modified application pointer to descriptor #3.


N1: 64th byte of packet data arrives.


S5: Driver polls descriptor #2.

S7: Driver is swapped out, allowing a non-Etherenet application to run.

S8: Driver calls application to tell application that packet has arrived.



C0: Lookahead to descriptor #2.


S2: Driver call to application to get application buffer pointer.

S9: Application processes packet, generates TX packet.

S10: Driver sets up TX descriptor.

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C4: Lookahead to descriptor #3 (OWN).

C6: "Last chance" lookahead to descriptor #3 (OWN).


N2: EOM

C10: ERP interrupt is generated.

S8A: Interrupt latency.

S7A: Driver Interrupt Service Routine executes RETURN.

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Figure 3. LAPP Timeline for TWO-INTERRUPT Method

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OWN = 1 STP = 1SIZE = HEADER_SIZE (minimum 64 bytes)

Descriptor#1

OWN = 1 STP = 0SIZE = S1+S2+S3+S4

Descriptor#2

OWN = 0 STP = 0SIZE = 1518 - (S1+S2+S3+S4+HEADER_SIZE)

Descriptor#3


OWN = 1Descriptor#5

Descriptor#6


OWN = 1Descriptor#8

Descriptor#9

OWN = 0 STP = 0

OWN = 0 STP = 0

STP = 0

STP = 0

A = Expected message size in bytesS1 = Interrupt latencyS2 = Application call latencyS3 =Time needed for driver to write to third descriptorS4 = Time needed for driver to copy data from buffer #1 to application buffer spaceS6 = Time needed for driver to copy data from buffer #2 to application buffer space

Note that the times needed for tasks S1,S2, S3, S4, and S6 should be divided by0.8 microseconds to yield an equivalentnumber of network byte times beforesubtracting these quantities from theexpected message size A.

SIZE = S1+S2+S3+S4

SIZE = S1+S2+S3+S4

SIZE = 1518 - (S1+S2+S3+S4+HEADER_SIZE)

SIZE = 1518 - (S1+S2+S3+S4+HEADER_SIZE)

SIZE = HEADER_SIZE (minimum 64 bytes)

SIZE = HEADER_SIZE (minimum 64 bytes)

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Figure 4. LAPP 3 Buffer Grouping for TWO-INTERRUPT Method

distinctive characteristics · am7990 local area network controller for ethernet (lance) am79c90...

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