dlc new model exam

7/28/2019 DLC NEW Model Exam

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Reg. No.

ARUNAI COLLEGE OF ENGINEERING, THIRUVANNAMALAI

MODEL EXAM

Fourth Semester

DEPARTMENT OF EEE

131405 Digital logic circuit

Answer ALL Questions

Time: Three hours Max. Marks: 100

Date: 7/4/12 PART A ( )10 2 20 =

1. Name the two cononical forms for Boolean Algebra.

2. Draw the truth table and logic circuit of half adder.

3. Draw the circuit of SR flip flop.

4. What are synchronous sequential circuits?

5. Give the characteristic equation and state diagram of JK FF.

6. What is a salf-starting counter?

7. What is the advantage of PLA over ROM?

8. Which IC family offers i) Low propagation delay, ii) Low power dissipation?

9. Write HDL for half adder.10. What are the various modelling techniques in HDL?

PART B(5 X 16 =80)

11. a) Reduce the following using tabulation method and verify with K-maps

F( A,B,C,D) = (0,1,2,3,4,6,8,10,12,14)

OR

b) i) Explain and convert binary to gray code .

ii) implement the following function with a multiplexer.

F(A,B,C,D) = (0,1,3,4,8,9,15)


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12. a) Design a counter with the sequence 0,1,3,7,6,4,0.

OR

b) The following sequence is to be realized by a counter consisting of 3 JK FFs

A1: 0 0 0 0 1 1 0

A2: 0 1 1 0 0 1 0

A3: 0 1 0 1 1 0 0

13. a) List and explain the steps used for analying an asynchronous sequential circuit.

OR

b) When do you get the critical and non-critical races? How will you obtain race free

conditions?

14. a) Implement the combinational circuit with a PLA having 3 inputs, 4 product terms

and 2 outputs for the functions

F1 = ( 3,5,6,7), F2= (0,2,4,7).

OR

b) i) Explain TTL

ii) Explain FPGA


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15. a) Write VHDL program for Flip Flop

OR

b) Write VHDL program for FSM.

.

Reg. No.

ARUNAI COLLEGE OF ENGINEERING, THIRUVANNAMALAI

MODEL EXAM

Fourth Semester

DEPARTMENT OF EEE

131405 Digital logic circuit

Answer ALL Questions

Time: Three hours. Max. Marks: 100

Date: 7/4/12 PART A ( )10 2 20 =


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1. Show that Excess-3 code is self complementing.

2. Add the hexadecimal numbers ; 93 and DE.

3. Convert JK FF to T FF.

4. Mention the major application of Master slave FF.

5. Draw the state diagram of SR FF

6. Define asynchronous sequential machine.

7. State the important characteristics of TTL family.

8. In which type of TTL gate wired AND logic is possible.

9. Write the VHDL code for AND gate.

10. List the operators available in VHDL.

PART B (5 X 16 = 80)

11. a) Obtain the minimum SOP using QMM and Verify using K-map.

F= M0+M2+M4+M8+M9+M10+M11+M12+M13.

OR

b) i) Realize the function given in i) using decoder and external gates.

F (w,x,y,z) = (0,1,2,4,5,7,8,9,12,13)

ii) Construct a BCD-XS3 code converter using fulladders.

12. a) A sequential circuit has four FFs ABCD and input X is described by the following

state equations.


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A(t+1) = (CD + CD) x + ( CD + CD) x, B(t+1) = A, C(t+1) = B, D(t+1) = C

i) Obtain the sequence of states when X= 1 starting from state ABCD= 0001

ii) Obtain the sequence of states when X= 0 starting from state ABCD= 0000

OR

b) Analyze the synchronous Moore machine to obtain its state diagram

JA=Y2X ; KA = Y2; JB= X; KB =X ; Z= Y1,Y2

13. a) Design an asynchronous sequential circuit that has two inputs X2 and X1 and one

output Z. When X1 = 0, the output Z is 0. The first change in X2 that occurs while

X1 is 1 will cause output Z to be 1. The output Z will remain 1 until X1 returns to 0.

OR

b) How do you get output specifications from a flow table in asyn.seq. circuit

operating in fundamental mode.

14)a)Implement the given function using PAL.

A= (0,2,6,7,8,9,12,13), B= (0,2,6,7,8,9,12,13,14), C= (1,3,4,6,10,12,13),

D= (1,3,4,6,9,12,14)

OR

b) Explain ECL

15) a) write VHDL program for full subractor and 4-bit MUX

OR

b) write VHDL program for Counters


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dlc new model exam

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