dma modules
DESCRIPTION
DMA Modules. The STM32 has two DMA peripherals each of which has multiple inde - pendently configurable “channels” (7 for DMA1 and 5 for DMA2). A channel is roughly the hardware realization of a transaction. - PowerPoint PPT PresentationTRANSCRIPT
DMA Modules• The STM32 has two DMA peripherals each of which
has multiple inde- pendently configurable “channels” (7 for DMA1 and 5 for DMA2). A channel is roughly the hardware realization of a transaction.
• To initialize DMA be- tween a peripheral and memory it is necessary to configure the appropriate channel. For example, DMA1 channel 2 (3) can be used to receive (transmit) data from (to) SPI1.
DMA Settings
• Prior to utilizing the DMA peripherals, remember to enable their clocks
• Configuring a channel consists of setting appropriate parameters through a DMA_InitTypeDef structure
The parameters include the peripheral base address (e.g. ADC1->DR), the
memory address buffer, the transfer direction, the buffer size, etc. Once the
DMA channel is initialized, it must be enabled. The STM32 firmware provides
peripheral specific commands to enable a DMA transaction.
• DMA module must be activated in the module which uses DMA:
ADC_DMACmd(ADC1, ENABLE);ADC_DMARequestAfterLastTransferCmd(ADC1,ENABLE);Or
The DMA channels provided by the STM32 are each associated with
specific peripherals (See reference manual for complete documentation).
For example DMA1 channel 1 supports ADC1, TIM2_CH3, and TIM4_CH1.
DAC Module• The DAC module is a 12-bit, voltage output digital-to-
analog converter. • The DAC can be configured in 8- or 12-bit mode and
may be used in conjunction with the DMA controller. • The DAC has two output channels, each with its own
converter– DAC1 (pin PA4) and DAC2 (pin PA5) • In dual DAC channel mode, conversions could be done
independently or simultaneously when both channels are grouped together for synchronous update operations. An
• input reference pin, Vref+(shared with ADC) is available for better resolution.
Each channel has separate control
logic which is configured through a
single control register (CR). Data to be
converted by channel x are written to
data holding register (DHRx). In
response to a trigger event, DHRx is
transferred to the data output
register (DORx) and, after a settling
time, the corresponding analog value
appears at the output.
DAC Settings• The clock sources must be activated and the DAC (PA4 or
PA5) pin must be configured as “analog ”.•
• Once a DAC is initialized, data may be written using the following commands
DAC Functions (CMSIS)
Pulse Width Modulation
• PWM signal• Duty Cycle, freq.• Sinosoidal signal• Applications:– Servo driver– SMPS– etc.
Timer PWM Settings
The pulse- width pw (0..999) can be set with the following command.
The pulse- width pw (0..999) can be set with the
following command.
Test_dma_adc
• Configure ADC1 and ADC2 in simultaneous mode, Set the DMA2 to transfer the ADC results to a mem. region
• Configure TIM2-> update at 50 KHz• Configure the TIM2 output trigger so that it occurs on update
events: TIM_SelectOutputTrigger(TIM2,TIM_TRGOSource_Update);• Change the trigger in the ADC initialization code: ADC_InitStructure.ADC_ExternalTrigConv=ADC_ExternalTrigConv_T2_TRGO;
• Configure the NVIC to enable interrupt channel DMA_IRQn with the highest priority
• Write a suitable interrupt handler.
Test_dac
• Enable DAC_Channel_1• Set TIM2 interrupt 150 KHz• Configure the NVIC to enable interrupt
channel TIM2_IRQn with the highest priority• Write a suitable interrupt handler.
Test_dac_speech
• Homework