doc.:1900.7-13-0070-01-CNTR

Submission Slide 1

06/05/23

Slide 1

Simulation result for Preliminary PHY proposal and alternative proposed set of Guard Chip

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Date: 2013-2-04

Name Company Address Phone Email Xin Zhang NICT

Hiroshi Harada NICT

Authors:

doc.:1900.7-13-0070-01-CNTR

Submission Slide 2

Abstract This contribution presents the revised simulation results

supported for the Preliminary PHY Proposal for IEEE 1900.7 System (doc.:1900.7-13-0054-00-CNTR )

Also it presents a revised method to determine the optimum values of guard chip for multi-code DSSS based PHY design.

06/05/2306/05/23

Slide 2

doc.:1900.7-13-0070-01-CNTR

Submission

PHY Design (1/2)06/05/23

Slide 3

Items Spec 1 Spec 2Modulation Scheme QPSK QPSK

Symbol Rate 50ksps 25 ksps

Data Rate 100 kbps 50 kbps

Number of Sequence 31 63

Sequence 5- stage M-Sequence 6 Stage M-Sequence

Guard chip 5 9

Length of extended sequence 36 72

Chip rate 1.8 MHz 1.8 MHz

Cyclic shift interval 5 9

Number of cyclic shifted code 6 7

Number of pilot channel 1 1

Number of data channel 5 6

Max transmission rate 500 kbps 300 kbps

doc.:1900.7-13-0070-01-CNTR

Submission

PHY Design (2/2)06/05/23

Slide 4

Items Spec 3 Spec 4Modulation Scheme QPSK QPSK

Symbol Rate 50ksps 25 ksps

Data Rate 100 kbps 50 kbps

Number of Sequence 31 63

Sequence 5- stage M-Sequence 6 Stage M-Sequence

Guard chip 5 9

Length of extended sequence 36 72

Chip rate 1.8 MHz 1.8 MHz

Cyclic shift interval 1 1

Number of cyclic shifted code 31 63

Number of pilot channel 1 1

Number of data channneel 30 62

Max transmission rate 3 Mbps 3.1 Mbps

doc.:1900.7-13-0070-01-CNTR

Submission

Outdoor Channel Model

•Table 1 shows the calculated RMS Delay Spread based on VHF band measurement results for Japan Public broadband network [1].The average RMS delay spread highly depends on the environment such as terrain type.

[1] M. OODO, N. SOMA, R. FUNADA and H. HARADA, “Channel Model for Broadband Wireless Communication in the VHF-band”, IEICE Technical Report

Index of Measured Points

P16 P5 P4 P1 P3 P6 P15 P2 P7 P14 P8 P13 P12 P11 P10 P9

Distance (km) 1.4 1.5 1.6 1.8 1.8 2.7 2.8 3.2 4.7 6.1 7.7 9.6 12.3 13.6 15.6 16

RMS Delay Spread (µs)

0.61 029 0.45 0.4 1.4 0.82 0.29 7.9 0.74 1.79 20.6 12.2 10.9 8.4 6.5 17.8

•Measure frequency 200MHz

•Hb=45m

•Hm=2m

•BS Power 20W

Slide 5

doc.:1900.7-13-0070-01-CNTR

Submission

Indoor channel Model06/05/23

Slide 6

•[2] Theodore S. Rappaport, Wireless Communications: Principles and Practice (2nd Edition), Prentice Hall, ISBN: 0130422320 Publish Date: Dec 31, 2007

[2]

doc.:1900.7-13-0070-01-CNTR

Submission

Delay Spread used in the simulation

Indoor delay spread < 270 ns (2.7e-7)

Outdoor delay spread < 0.5 us (5 e-7)

06/05/23

Slide 7

doc.:1900.7-13-0070-01-CNTR

Submission

06/05/23

Slide 8

54 MHz 806 MHz

Fd=400 Hz 7992 km/hr 536 km/hr

Fd=100 Hz 1998 km/hr 134 km/hr

Fd=40 Hz 799.2 km/hr 53.6 km/hr

Speed of airplane: 885 km/hr

Speed of bullet train: 300 km/hr

20 22 24 26 28 30 32 34 36 38 4010

-5

10-4

10-3

10-2

10-1

SNR (dB)

BE

R

Spec 1, fd=400 HzSpec 2, fd=400 HzSpec 3, fd=400 HzSpec 4, fd=400 HzSpec 1, fd=100 HzSpec 2, fd=100 Hzspec 3, fd=100 HzSpec 4, fd=100 HzSpec 1, fd=40 HzSpec 2, fd=40 Hzspec 3, fd=40 HzSpec 4, fd=40 Hz

Performance for 2 path Rayleigh Fading

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Submission

DETERMINATION OF OPTIMUM GUARD CHIP

06/05/23

Slide 9

doc.:1900.7-13-0070-01-CNTR

Submission

Guard chips calculation (Spec 3)06/05/23

Slide 10

Modulation QPSK 16 QAM 64 QAM Unit

Chip Rate 1.8 1.8 1.8 Mcps

Guard Chip x x x chips

Length of chips per symbol 31 + x 31+x 31+x chips

Cyclic shift interval 1 1 1 chips

Symbol Rate 1.8/(31+x) 1.8/(31+x) 1.8/(31+x) Msps

Max transmission data rate 1.8 *30*2/(31+x) 1.8*30*4/(31+x) 1.8*30*8/(31+x) Mbps

Expected data rate for M2M 10 10 10 Mbps

X 5 11 17 5 11 17 5 11 17 chips

Transmission data rate 3 2.6 2.3 6 5.1 4.6 12 10.2 9.2 Mbps

doc.:1900.7-13-0070-01-CNTR

Submission

Data throughput vs. different number of guard chips (Spec 3)

06/05/23

Slide 11

4 6 8 10 12 14 16 182.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3

Guard Chip (bits)

Dat

a T

hrou

ghpu

t (m

bps)

SNR=20SNR=25SNR=30

Guard chip (bits) 5 11 17

SNR=20, error (mbps) 0.0336 0.03328 0.03285

SNR=25, error (mbps) 0.0114 0.01066 0.0108

SNR=30, error (mbps) 0.0033 0.00312 0.00315

• These table and chart are based on QPSK modulation scheme.

• From simulations and calculations, larger number of guard chips obtained fewer number of error shown in the table.

• However, due to the larger overhead incurred,the effective data throughput is reduced as thethe number of guard chip increases as shown on the left.

doc.:1900.7-13-0070-01-CNTR

Submission

Summary

From the above simulations and calculations, we find that larger number of guard chip though obtain few number of the error, the effective data throughput is reduced as more overhead bits are involved.

Hence, I would like to revised that guard chip 5 and guard chip 9 are better for spec 3 and 4.

06/05/23

Slide 12

doc.:1900.7-13-0070-01-CNTR

Submission

Conclusion

In this presentation, a revised simulation results are presented, as well as a revised method of determining the optimum number of guard chip.

From the calculations and simulations, we would like to propose to have 5 guardchips for spec 3 and 9 guardchips for spec 4.

06/05/23

Slide 13

doc.:1900.7-13-0070-01-CNTR

Submission

Appendix06/05/23

Slide 14

Modulation QPSK 16 QAM 64 QAM Unit

Chip Rate 1.8 1.8 1.8 Mcps

Guard Chip x x x chips

Length of chips per symbol 63 + x 63+x 63+x chips

Cyclic shift interval 1 1 1 chips

Symbol Rate 1.8/(63+x) 1.8/(63+x) 1.8/(63+x) Msps

Max transmission data rate 1.8 *62*2/(63+x) 1.8*62*4/(63+x) 1.8*62*8/(63+x) Mbps

Expected data rate for M2M 10 10 10 Mbps

X 9 21 33 9 21 33 9 21 33 chips

Transmission data rate 3.1 2.65 2.325 6.2 5.3 4.65 12.4 10.6 9.3 Mbps

Guard chips calculation (Spec 4)