final report - university of portlandteaching.up.edu/.../documents/steelhead_finalreport095.doc ·...

University of Portland School of Engineering Phone 503 943 73145000 N. Willamette Blvd. Fax 503 943 7316Portland, OR 97203-5798

Final Report

Project Steelhead: A CMOS 4-bit x 4-bit Multiplier

Contributors:

Ross Yoshioka

Scott Sato

ApprovalsName Date Name Date

Dr. Osterberg Dr. LillevikInsert checkmark (√) next to name when approved.

UNIVERSITY OF PORTLAND SCHOOL OF ENGINEERING CONTACT: ROSS YOSHIOKA

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FINAL REPORT REV. 0.95 PAGE IIPROJECT STEELHEAD UP-EE-TR-04-02

Revision HistoryRev. Date Author Reason for Changes

0.9 04/16/04 R. Yoshioka & S. Sato

Initial draft

0.95 04/20/04 R. Yoshioka & S. Sato

Updated budget table, inserted Block diagram in “Results”


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FINAL REPORT REV. 0.95 PAGE IIIPROJECT STEELHEAD UP-EE-TR-04-02

Acknowledgements- Dr. Peter M. Osterberg:

First, thank you for giving us the idea of creating a 4-bit x 4-bit multiplier. Thanks also for teaching us how to break down our design into different levels (Top-Level Schematic, Chip Block Diagram, Output Decoder Diagram, B²Logic Simulation, TPR file, etc.) This helped a lot in our monthly Program Reviews. Thanks also for teaching us how to use the correct wording in all of our documents.

- Dr. Sigurd L. Lillevik

Thank you for teaching us how to properly document our ideas. We truly were able to narrow down our ideas from such document as the Functional Specifications and the Project Plan. The documentation brought the professional aspect of designing a project in the real working world to our project.

- Mr. Michael M. DeSmith

Thank you for helping us to break down the step by step process of what the user will see when he or she uses of device. Thanks also for your advice on our 8-bit binary to BCD conversion.

- Sandra A. Ressel

Thank you for your willingness to always get us the parts that we needed.

- Dr. Wayne Lu

Thank you for your advice on using the rotary devices instead of the keypad. Thanks also for your help on designing our GAL’s (Gate Array Logic) chips.


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FINAL REPORT REV. 0.95 PAGE IVPROJECT STEELHEAD UP-EE-TR-04-02

Table of ContentsSummary..............................................................................................................1

Introduction..........................................................................................................3

Background..........................................................................................................4

Methodology.........................................................................................................5

Results................................................................................................................13

Technical................................................................................................................................. 13

Process................................................................................................................................... 13

Conclusions........................................................................................................15

Appendices..........................................................................................................16


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FINAL REPORT REV. 0.95 PAGE VPROJECT STEELHEAD UP-EE-TR-04-02

List of FiguresFigure 1. Project Steelhead Top Level Block Diagram........................................................................5

Figure 2. Steelhead schedule..........................................................................................................10

Figure 3. Project Steelhead Block Diagram......................................................................................13

Figure 4. Project Steelhead Chip Block Diagram..............................................................................14

Figure 5. Project Steelhead Output Decoder Block Diagram.............................................................14

Figure 6. Project Steelhead B2Logic Simulation................................................................................15

Figure 7. Project Steelhead TPR File Snippet...................................................................................16

Figure 8. Project Steelhead Chip Layout..........................................................................................17


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FINAL REPORT REV. 0.95 PAGE VIPROJECT STEELHEAD UP-EE-TR-04-02

List of TablesTable 1. Steelhead Deliverables........................................................................................................6

Table 2. Key Steelhead milestones....................................................................................................8

Table 3. Overall Steelhead Budget………………………………………………………………………….11


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FINAL REPORT REV. 0.95 PAGE 1PROJECT STEELHEAD UP-EE-TR-04-02

Chapter

Summary1Project Steelhead is a CMOS 4-bit x 4-bit Serial Multiplication chip implemented with a

MOSIS VLSI (very large-scale integration) chip. Project Steelhead will likely be used as a

classroom demonstration project at the University of Portland. This document covers the

introduction, background, methodology, results, and conclusion of project Steelhead.

The input to project Steelhead comes as two 4-bit binary numbers through two rotary

devices. The 4-bit binary numbers are then converted into its decimal equivalent and then

displayed on two red seven-segment LED displays. At the same time, the two 4-bit

numbers are also fed to the chip to be multiplied. The output from the chip will be one 8-

bit binary number which will then be displayed on a green seven-segment LED display.

The necessary off-chip binary to decimal decoding for both the input and output displays

was done using GAL (Gate Array Logic) chips.

The development process of Project Steelhead is shown in our schedule. The design

of the chip (using B²Logic), the implementation of the tpr file, and the ordering of the parts

was completed in the fall 2003 semester. In the spring 2004 semester, we built and tested

both the macro-model (which is a discrete representation of our MOSIS chip) and our

system model (which includes both our input and output sections). We planned on

replacing our macro-model with our MOSIS chip but we were unable to do this, which will

be explained in our results section.

In terms of budget, this project was mainly sponsored through funding by the

University of Portland. MOSIS provided the fabrication services for the CMOS VLSI chip

via NSF funding. B²LOGIC and Tanner LEDIT were used to design the VLSI chip. All

other necessary parts were purchased by the project team using money provided by the

University of Portland. These parts included, but are not limited to, 74xx chips (macro


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model), two rotary devices, seven segment LED displays, power supply, display case,

GAL’s, 555 series clock chip, and a R-S Latch.

Any further questions or concerns may be directed to Scott Sato or Ross Yoshioka.


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Chapter

Introduction2The purpose of this document is to inform our EE/CS 481 classmates; our advisor, Dr. Osterberg; our

industry representative, Mr. Michael M. DeSmith; and our EE/CS 481 instructor, Dr. Lillevik about the

background, methodology, results, and conclusion of project Steelhead. From reading this document,

the reader will gain insight on the development process and the results of project Steelhead. The

reader will also gain an understanding of the risks, as well as the conclusions the project team has

made so far.

Also included in the Final Report are the following:

• Background: Includes the major components of the project, as well as its uses in the

present technologies.

• Methodology: Describes how we designed and created our project.

• Results: Describes both the technical and process sections of our results.

• Conclusion: Recaps the key points of this document.


PROJECT PLAN REV. 0.95 PAGE 4PROJECT STEELHEAD

Chapter

Background3This project consists of a multiplier implemented with a CMOS VLSI chip. The chip is

provided by MOSIS and is the most vital part of our design. The most integral part in

designing the MOSIS chip is the tpr file, which is then used to automatically place and

route the chip in the Tanner LEDIT CAD tool. According to Dr. Peter Osterberg, a CMOS

VLSI multiplier has never yet been attempted at the University of Portland. The key

technology of this project can be used in digital signal processing for such applications as

audio and video compression, and wireless communication.


FUNCTIONAL SPECIFICATION REV. 0.95 PAGE 5PROJECT STEELHEAD

Chapter

Methodology4General Description

Figure 1 shows the overall block diagram of the Project. The input to this project will

come as two 4-bit binary numbers from two rotary devices. These inputs will then be

converted into decimal form using GAL’s (gate array logic) and BCD to seven-segment

decoders to display the inputs (the multiplier and the multiplicand) on seven-segment LED

displays. At the same time the two 4-bit numbers are fed to the chip to be multiplied. The

output from the chip will be one 8-bit binary number which will then be displayed on

another set of seven-segment LED displays. Figure 1. shows our top level diagram,

breaking the project down into three parts which are further explained in figure 3.

Figure 1. Project Steelhead Top Level Block Diagram



Deliverables

Table 1. Steelhead Deliverables.

Number Deliverable Date1 Chip Design and Simulation 10/28/032 Chip tpr file completed 11/11/033 Macro Model 3/23/044 I/O system 4/01/045 Prototype Assembly and

debugging with Macro Model 4/01/04

6 Receive MOSIS chip and Plug-In 4/01/04

7 Build Display Unit 4/3/048 Final Functional Prototype

Demonstration (Founder’s Day)

4/13/04

Chip Design and Simulation

This involved breaking Project Steelhead’s Multiplier Chip into smaller blocks of logic. Each block was then designed and simulated in B2Logic using only the standard cells provided in the L-Edit Suite.

Chip tpr file completed

Completed tpr file (checked, re-checked, and re-re-checked) for the chip in order to be programmed by L-Edit’s Place and Route software.

Macro Model

Built a Macro Model of the Project Steelhead Multiplier Chip as a backup for the MOSIS CMOS chip.

I/O System

Built and tested the I/O system for Project Steelhead.

Prototype Assembly and Debugging

Put together all pieces of Project Steelhead and test for functionality. Project worked perfectly with Macro Model in place of chip.



Receive Mosis Chip and Plug-in

Take Macro Model out and replace with MOSIS Chip. MOSIS chip didn’t work.

Build Display Unit

Once the Project is working properly, a suitable display case will need to be constructed. Building material was built out of Plexi-glass.

Final Functional Prototype Presentation

Completed and Fully tested prototype of Project Steelhead.

General Approach

The primary goal of the day to day operations of Project Steelhead was to stay on

schedule. The first step in Project Steelhead was researching Binary Multiplication

Methods. The most desirable method was one that was easy to understand, implement,

and was considered to be fast. The next step was to design and simulate this multiplier in

B2Logic and to obtain a design that would ensure success. After B2Logic design and

simulation was complete, extensive testing was needed to help ensure that the design

was accurate. We then took this schematic and used it to write the tpr file which was

needed to automatically place and route the chip. While one team member worked on

this, the other worked on figuring out exactly what parts were need to be ordered. Before

going on winter break, we ordered all parts necessary to build the Macro Model, as well as

the remainder of the project. Once these parts were received in the spring, we began

building the Macro Model. At the same time, we also built the System Model. The next

step was to put the pieces together and get the project working with the Macro Model.

After the project was working correctly and we receive the chip from MOSIS, we replaced

the Macro Model with the Chip. Unfortunately, we had an error in our tpr file, which led to

the CMOS chip not working. The last step was to build a display case, the materials for

which were mostly salvaged from past projects.

Milestones



Table 2. Key Steelhead milestones.

Number Description OriginalDate

PreviousDate

PresentDate

1 Product Approval 9/22/03 9/30/03 10/07/032 Project Plan

Approval11/04/03 11/04/03 11/06/03

3 TPR File Completed

11/26/03 11/26/03 11/26/03

4 Design Release 12/02/03 12/02/03 12/02/035 Macro Model

Complete02/09/04 02/09/04 02/09/04

6 TOP’s Approval 02/10/04 02/10/04 02/10/047 Prototype

Functional with Macro Model

03/07/04 03/31/04 04/01/04

8 Receive MOSIS chip

03/17/04 03/31/04 04/01/04

9 Prototype Release

04/06/04 04/09/04 04/09/04

10 Founder’s Day Presentation

04/13/04 04/13/04 04/13/04

11 Final Report Approval

04/20/04 04/20/04 04/22/04

12 Post Mortem Presentation

04/22/04 04/22/04 04/22/04

Table 2 lists Project Steelhead’s key milestones. The first milestone, Product

Approval, has already been completed. The Project Plan Approval has already been

approved from both our advisor and Industry Representative. We completed the creation

of our tpr file. We got our Design Release approved. This marked the end to Fall

Semester.

Spring Semester opened far more relaxed, with most design milestones well spaced

out. The completion of the Macro Model was the first milestone of the semester. The

second milestone was the Approval Meeting for the “Theory of Operation” document. The

next milestone, Prototype functional with Macro Model, was another important design UNIVERSITY OF PORTLAND SCHOOL OF ENGINEERING CONTACT: ROSS YOSHIOKA


milestone. It was the point where our project worked with the Macro Model. The next

milestone was replacing the MOSIS chip with the macro-model. Unfortunately, we were

not able to do this since our tpr file had an error in it. The next milestone, Prototype

Release, was the time at which our Prototype was fully functional. Project Steelhead

came together at the next milestone. Founder’s Day was the final presentation done on

the project. This was a time to talk about the design process and show the success of the

project, which was completely functional with the macro-model.

The Final Report is the second to the last item on the list. It is the last document done

by the team, and will bring together all that was learned through the life of the project. The

last milestone is the Post Mortem presentation/discussion held with the junior class. This

serves to help the upcoming seniors gain a grasp on what lies ahead for them.



Schedule

Figure 2. Steelhead schedule.

Schedule Overview

The most critical work came in the month of November. This was when the design of the entire project came together to create a stable design for the MOSIS Chip. Once this was done, the project’s timeline eased up somewhat. The building of the Macro Model and I/O section of the project was by far more stressful in comparison to the design of the MOSIS chip and I/O sections since many problems arose.

Critical Path

The critical path included the design and simulation of the chip in the Fall Semester. It also included the creation of the tpr file. The ordering of parts, along with the necessary lead time to receive them was the next item on the critical path. In the spring semester, the creation of the macro model, along with the building of the I/O section of the Project was the next items located on the critical path. After this, the delivery of the MOSIS Chip was the next item on the critical path. After the Chip was received, testing also needed to be done before the final Prototype Release was completed.



Resources

Personnel

Scott Sato: Team Leader for Fall Semester; Design and Simulation of Chip in B2Logic, writing of tpr file, website, build macro model, testing.

Ross Yoshioka: Team Leader for Spring Semester; Verification of tpr file, Choosing parts, B2Logic simulation of I/O section, build system model, testing.

Budget

Table 3. Overall Steelhead budget.

Equipment

Power Supply: Used to power the Chip / Macro Model, I/O Section, and Display. Salvaged from a past Senior Design Prototype.

Ribbon Cables: Used to connect the various parts of the project.

Prototyping Board: Used to put the bulk of the project together.

Wire: Used to connect discrete components of the project.

Wire Wrapping Gun: Used to connect pins and wires in Macro Model and Overall Project. Provided by the University of Portland.

Logic Gates: Used to build Macro Model and Combinational Logic for I/O Section.



Resistors: Used to regulate voltage in project (I/O section).

Seven-Segment LED Displays: Used to create an attractive display for the User.

Push Buttons: Used for the “Clear” and “Equal” keys.

Rotary Devices: Used to send out the input in BCD form.

Case Material: Used to build an attractive and appropriate case for display.

Facilities

The University of Portland, School of Engineering Electrical Circuits laboratory, ENG 2001 was primarily used when constructing and testing Project Steelhead.



Chapter

Results5Technical

Block Diagram

Figure 3. Project Steelhead Block Diagram

This is a diagram breaks down our top level diagram, figure 1. It covers the same scope as figure 1., but goes into more detail regarding what each block is comprised of.



Chip Block Diagram

Figure 4. Project Steelhead Chip Block Diagram

This diagram shows the algorithm employed in our Chip and Macro Model. It is a “Shift and Add” type of multiplier. In short, this block diagram shows what the “MOSIS Chip” block is made of (in figure 3.).

Output Decoder Block Diagram

Figure 5. Project Steelhead Output Decoder Block Diagram

This diagram shows the method we employed to convert from the 8-bit binary output from the Chip/Macro Model to the three digit decimal number the user would see. Since no 8-



bit binary to BCD decoders were readily available commercially, we decided to implement this decoding using Gate Array Logic, or GALs for short.

Process

The first step we took in designing our prototype was to gather our thoughts and try to come up with a design on paper. We used knowledge from various classes we have taken to do this. The next step was to simulate this design in B2Logic. Figure 6. shows the simulation for our Chip/Macro Model.

Figure 6. Project Steelhead B2Logic Simulation

After this simulation was tested exhaustively, the next step was to take this simulation and create a tpr file. This tpr file is a net list used by L-EDIT’s Place and Route software. A snippet of this code is shown in figure 7. After fabrication, it was discovered that an error was made in the creation of the tpr file. Through due diligence/error analysis, we were able to find the exact location of the error within the file.



Figure 7. Project Steelhead TPR File Snippet

The TPR file, which turned out to be nearly six pages long, was then sent to Dr. Osterberg who ran it through the L-EDIT software to get our chip layout which is shown in figure 8.



Figure 8. Project Steelhead Chip Layout

One major assumption we made was that we understood how the keypad we intended to use operated. We did not have a backup plan in the event this assumption proved wrong. Instead, we were forced to create a solution “on the fly”. Luckily, a solution even more practical than our original one presented itself. Another assumption we made that proved to be false was the assumption that our MOSIS Chip would work. However, the other two assumptions we made did prove to be true. They were: (1) assuming our multiplier design was valid; (2) and also assuming we would be able to get all the parts we needed.

There were a few instances where we did fall behind the dates projected in our milestones table. One major instance of this was in the event labeled “Prototype Working with Macro Model.” This also caused us to fall behind on our next milestone, which was to receive and test our MOSIS Chip. Because both of these events were located along the critical path of our plan, they did have some affect on our timeline. However, since there was some extra time built into the schedule, the delays did not affect our ability to complete our prototype in time for Founder’s Day.

One risk which proved risky was the risk of our MOSIS Chip not working. Although there was a backup plan (the Macro Model), there is no real substitute for having the chip actually working. That backup plan ended up being the savior of our project, since without it, we would not have a functioning prototype. Another risk we considered that ended up manifesting itself was the risk of a keypad failure. Although a failure did not happen in the usual sense of the word, our failure to correctly assess the workings of the keypad was a cause for worry when the problem arose. Luckily, a good solution was found. The final risk we mentioned was the “Prototype not functioning properly.” Although we listed



this as a medium risk, the outfall of such a failure would be tremendous. Luckily, we did not have the misfortune of experiencing the fallout of this risk.

As mentioned earlier in the discussion of our Milestones table, the time required to build and debug our Macro Model and System Model were underestimated. Having never worked on a project of this scope before, this was probably just a function of not knowing was to expect. Our budget, equipment, and facilities proved adequate. Our advising resources proved to be excellent. Without the help of all those listed in our acknowledgment section, we would have surely struggled, possibly even failed.

In the section of contingency plans, the contingency plan for the MOSIS Chip not working was invoked, the reasons for which are self-explanatory. There was also a secondary contingency plan for the keypad not working properly. This was the actualization of our “Input Interface” using rotary keys. This contingency plan was not included in our Project Plan because we were not aware of such a possibility at that time.

There was one change request made during the design sequence. This was the request to change our design from using a keypad to two rotary switches as discussed above. It was submitted on April 4, 2004.



Chapter

Conclusions6In this document, we covered the summary, introduction, background, methodology, and

results of Project Steelhead. Overall, we accomplished most of our objectives. We successfully

designed and created a 4-bit x 4-bit multiplier using the macro-model instead of the MOSIS chip. Also

all of our input and output devices like our rotary devices, binary to seven-segment decoders, and our

LED displays worked perfectly. The only problem that we had was our MOSIS chip not working

correctly. On a positive note, though, we discovered that the root of the problem occurred in the

counter section of our tpr. File. The value should have said P1 instead of P0. This problem was the

difference between our MOSIS chip working and not working.

Some possible areas of improvement would be keeping on schedule during the design

process and also checking and rechecking the tpr file until it is absolutely correct. Maybe in the future

groups could also use the B²Logic to L-Edit Translator.

Overall, we really learned a lot from this Senior Design Project. We learned that keeping on

Schedule was extremely important to the success of our design. We also learned how to properly

document the design process. Finally, we discovered that the engineering teachers at the University

of Portland are extremely helpful and supportive!


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