Download - 02_Mierzwinski_MOS-AK_SF08
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
1/44
Developing andReleasing CompactModels Using Verilog-A
Marek Mierzwinski, PatrickO'Halloran, and Boris Troyanovsky
Tiburon Design AutomationSanta Rosa, CA
1st International MOS-AK MeetingDec 13, 2008, San Francisco
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
2/44
Tiburon Design Automationwww.tiburon-da.com
Outline
Some motivation and backgroundhistory
Implementation issues
Performance
Debugging
Practical considerations in distributing
models Future directions/Conclusions
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
3/44
Tiburon Design Automationwww.tiburon-da.com
Compact Model Distribution
Foundry
Designer
Vendors
Modeldeveloper
Model extracted
Independentimplementations
Model and simulationflow verified
Design verified
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
4/44
Tiburon Design Automationwww.tiburon-da.com
Motivation
Compact model development ischallenging
Adding new models to circuitsimulators can prove just aschallenging
Proprietary (non-portable) interfaces
Limited capabilities
Burden on model developer to hand-calculate derivatives
write analysis-specific code
handle software engineering details
4
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
5/44
Tiburon Design Automationwww.tiburon-da.com
Motivation (cont.)
Analog Hardware DescriptionLanguages (AHDLs) can provideimportant benefits:
Ease of development
Model portability
Across different simulators
Across various analysis types
Suitable for full range of model types Behavioral level down to transistor level
5
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
6/44
Tiburon Design Automationwww.tiburon-da.com
Why Verilog-A
Natural language for compact modeldevelopment
Succinct
derivatives, loads all handled by compiler
simple parameter support
Standard
Implemented in most simulators
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
7/44
Tiburon Design Automationwww.tiburon-da.com
History
Verilog-A is a precisely defined subsetof the Hardware DescriptionLanguage, Verilog-AMS
Development overseen by OVI/Accellera late 1990s
Active effort to merge with
SystemVerilog
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
8/44
Tiburon Design Automationwww.tiburon-da.com
Barriers to Adoption
Performance Important for transistor-level models
Must eventually be comparable w/ built-ins
Compact modeling constructs
Greatly improved with v2.2 languagestandard
8
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
9/44
Tiburon Design Automationwww.tiburon-da.com
Barriers to Adoption (Cont.)
Inertia
Misconceptions regarding languagecapabilities
Existing code base of non-AHDL-baseddevice models
Lack of familiarity within modeldevelopment community
Lack of comprehensivedebugging/development methodology
9
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
10/44
Tiburon Design Automationwww.tiburon-da.com
Overcoming the Barriers
Performance No theoretical reason for Verilog-A to be
inferior in performance to built-ins
Availability
Verilog-A now supported by virtually all majorcommercial vendors
Support for all analysis types, e.g. transient,harmonic balance, shooting, nonlinear noise.
Advanced features
noise
paramsets
10
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
11/44
Tiburon Design Automationwww.tiburon-da.com
Overcoming the Barriers
For the user
End user experience must be as goodas or better than using existing model
distribution method
11
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
12/44
Tiburon Design Automationwww.tiburon-da.com
Existing Models
Most compact transistor models havebeen implemented in Verilog-A:
BSIM3, BSIM4, BSIM5
SPICE Gummel-Poon, diode, MOS1, MOS3,pTFT, aTFT
NXP MEXTRAM 504, MOS Model 9/11
PSP (Penn State/NXP MOSFET)
EKV HiCUM Level 0/Level 2, VBIC, VBIC, FBHBT
Parker-Skellern, Angelov, Curtice, TOMMESFET *implemented by developers
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
13/44
Tiburon Design Automationwww.tiburon-da.com
Writing Compact Models
www.bmas-conf.org/2004/papers/bmas04-coram.pdf
Excellentprimer on
implementingcompact devicemodels inVerilog-A
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
14/44
Tiburon Design Automationwww.tiburon-da.com
Performance
Model can have a big influence
execution speed
memory use
Choice of particular constructs canresult in performance degradation
Avoidable state variables
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
15/44
Tiburon Design Automationwww.tiburon-da.com
Nodal Analysis
=> resistive
=> reactive (inductors, capacitors)
=> current sources
For a hypothetical circuit with current sources,resistors, capacitors:
is vector of voltages, all the equations are
standard KCL, and so PURE NODALANALYSIS.
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
16/44
Tiburon Design Automationwww.tiburon-da.com
Voltage Sources in Verilog-A
However, if we have a voltage source
V(a, b)
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
17/44
Tiburon Design Automationwww.tiburon-da.com
Inductances
Similarly, inductances in Verilog-A alsoadd an additional state variable:
V(a, b)
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
18/44
Tiburon Design Automationwww.tiburon-da.com
Performance Impact
Extra equations introduced from
Voltage contributions on the left-hand-side, or
Current access on the right-hand side Result: extra state variables impact
efficiency for compact models.
Work-around: Use currentcontributions, avoid unnecessarycurrent probes
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
19/44
Tiburon Design Automationwww.tiburon-da.com
Branch-ddt Equations
Branch-ddt equations are statevariables related to implementingddt() equations
How they arise:
From the basic nodal KCL
Note that it does not support terms of theform
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
20/44
Tiburon Design Automationwww.tiburon-da.com
Branch-ddt (cont)
The Verilog-A code
x = V(a, b);
I(a, b)
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
21/44
Tiburon Design Automationwww.tiburon-da.com
Branches from Conditionals
When variablesthat depend onddt() are used in
conditionals, the
compiler mustcreate extrabranch equations
if (Vds < 0.0)Mode = -1; // Inverse mode
elseMode = 1;
Qbd_ddt = ddt(Qbd);Qbs_ddt = ddt(Qbs);
if (Mode == 1)begint0 = TYPE * Ibd + Qbd_ddt;
t1 = TYPE * Ibs + Qbs_ddt;
endelse begin
t1 = TYPE * Ibd + Qbd_ddt;
t0 = TYPE * Ibs + Qbs_ddt;
endI(b,di)
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
22/44
Tiburon Design Automationwww.tiburon-da.com
Avoiding Branches fromConditionals
Place thearguments toddt() in the
conditionals
if (Mode == 1)begint0 = TYPE * Ibd;
arg0 = Qbd;
t1 = TYPE * Ibs;
arg1 = Qbs;
endelsebegin
t1 = TYPE * Ibd;
arg1 = Qbd;t0 = TYPE * Ibs;
arg0 = Qbs;end
I(b,di)
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
23/44
Tiburon Design Automationwww.tiburon-da.com
Probing Mistakes
Common mistake when probing port current:
$strobe(I(port_name));
Introduces unnamed branch
Effectively shortsport_name to ground
Adds additional state variable
Instead use
$strobe(I());
Easily detected at compile-time
23
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
24/44
Tiburon Design Automationwww.tiburon-da.com
Superfluous Assignments
Consider:
(10) x = V(a, b)/R;(11) if(type == 1)(12) x = V(a, b)/R1;(13) else(14) x = V(b, a)/R2;
Diagnostic message from compiler:Warning: Assignment to x may be superfluous.
[ filename.va, line 10 ]
24
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
25/44
Tiburon Design Automationwww.tiburon-da.com
Memory States
Variables are initialized to zero onfirst call to module
The simulator retains the valuebetween calls to module
If used in assignment before it isassigned, it will have the value of theprevious iteration
Also known as hidden states Compact models should not use them
could cause unexpected behavior
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
26/44
Tiburon Design Automationwww.tiburon-da.com
Collapsible Nodes
Native models can remove or collapse unneedednodes
Common idiom for collapsible nodes:if(Rc > 0.0)
I(c, ci)
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
27/44
Tiburon Design Automationwww.tiburon-da.com
Performance Summary
Be aware of what causes extraequations
Collapse nodes when possible
Watch out for
memory states
superfluous equations
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
28/44
Tiburon Design Automationwww.tiburon-da.com
Debugging
Basic
$strobe outputs every converged iteration
$debug outputs every call to module
Use macros to disable in general use`ifdef DEBUG
Compile time diagnostics
Compiler flags for runtime
Too expensive for production code Very useful during development phase
Iteractive debugging
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
29/44
Tiburon Design Automationwww.tiburon-da.com
Compile-Time Diagnostics
List of state variables
List of branch types
Voltage- / Current- / Switch- Branches
Collapsible nodes
Memory states
Superfluous assignments
Unused variables
Floating nodes
29
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
30/44
Tiburon Design Automationwww.tiburon-da.com
Diagnostics (cont.)
Check for addition of extra statevariables
Probing current through a branch
Voltage branches Switch branches
In many cases, not necessary/desiredfor compact modeling
Invisible to developer unlessdiagnostics are issued
30
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
31/44
Tiburon Design Automationwww.tiburon-da.com
Diagnostics (cont.)
Compiler output=== Summary information for module 'mos3_va':
Branch information:
(b, di) : Current Branch (implicit)
(b, si) : Current Branch (implicit)
(di, d) : Statically shorted branch
(di, si) : Current Branch (implicit)
(g, di) : Current Branch (implicit)
(g, si) : Current Branch (implicit)
(si, s) : Statically shorted branch
Branch ddt operators:
[ line 685, col 15 ]
[ line 686, col 15 ]
Potential memory states:
'Arga'
'Argb'
'Beta_T'
'CdOnCo'
'CsOnCo'
'Delta_L'
'Fermig''Fermis'
'Kappa'
'Vgst'
'Wkfng'
'Wkfngs'
=== End of summary information for module 'mos3_va':
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
32/44
Tiburon Design Automationwww.tiburon-da.com
Compiler Flag Example
1. Compile with flag2. Simulate3. Simulator runs until floating point
exception occurs
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
33/44
Tiburon Design Automationwww.tiburon-da.com
Interactive Debugging
Allows quick iterative investigation ofmodule
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
34/44
Tiburon Design Automationwww.tiburon-da.com
Portability Across AnalysisTypes Certain language constructs are not
supported by RF analyses (e.g, HarmonicBalance, Shooting, Envelope)
Should be avoided for reasons of
portability
consistency across analyses
efficiency
Typically not required (or desired) forcompact models
34
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
35/44
Tiburon Design Automationwww.tiburon-da.com
Additional RF Restrictions
Explicit use of time $abstime
Analog Operators
Allowed:
Differentiation ddt(), ddx()
Delay absdelay()
Laplace laplace()
Integration idt()without
initial conditions Others are:
Not safe for RF analysis
Not (typically) useful for compact modeling
35
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
36/44
Tiburon Design Automationwww.tiburon-da.com
Model Distribution
Complete model support requires
model version control
schematic capture information
simulator dependent
End-user experience
easy installation
look and feel of native device instance/modelcard
multiplicity
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
37/44
Tiburon Design Automationwww.tiburon-da.com
Parameter Case
Verilog-A is case sensitive
Some simulators are case sensitive,others are not
Provide aliases
aliasparam AREA=Area;
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
38/44
Tiburon Design Automationwww.tiburon-da.com
IP Protection
Compiled libraries effectively hidessource code as well as built-in models
Model parameters can be hidden in
source code by assigning them asdefault values
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
39/44
Tiburon Design Automationwww.tiburon-da.com
Example ADS
Design Kits provide a convenientmechanism for distributing completemodel package
End user opens a zipped file
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
40/44
Tiburon Design Automationwww.tiburon-da.com
Example
Users have aone-step processto install model
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
41/44
Tiburon Design Automationwww.tiburon-da.com
Example
Users see nodifference when
using Verilog-Aimplementedmodels
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
42/44
Tiburon Design Automationwww.tiburon-da.com
Future Directions
Tools for improved modeldevelopment
Automatic checking of smoothness,
continuity, etc. Automated checks for passivity / stability
/ etc. where appropriate
42
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
43/44
Tiburon Design Automationwww.tiburon-da.com
Conclusion
Continued growth and adoption ofVerilog-A presents numerous benefitsfor
Compact model developers
Circuit designers
Tool vendors
Benefits include
Portable, robust compact models
Ease of development
Fast model distribution and modification
43
-
7/31/2019 02_Mierzwinski_MOS-AK_SF08
44/44