![Page 1: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/1.jpg)
1
ECNG1014 Digital Electronics
Sequential Logic: FSMs
![Page 2: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/2.jpg)
2
Synchronous Sequential Networks
• The block diagram of figure 4 can be modified to represent a synchronous network by replacing all the memory elements by Flip-flops which are controlled by the same clock signal (figure 6).
Figure 6: Synchronous sequential network
![Page 3: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/3.jpg)
3
• All flip-lop changes are assumed to be synchronized by a single clocking signal and change their state following the same edge of the clock. Activity in the network is cyclic with the clock signal. That activity consists of the following.
• 1. Following the synchronizing clock edge:
• (a) primary input variables W1, W2…….Wn may change value,
• (b) flip-flop output variables y1, y2, ……yn may change value.
![Page 4: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/4.jpg)
4
• But all the changes must take place within a finite, know interval Tf, usually Tf is the maximum of the flip-flop propagation delays.
• 2. Then the new input symbol to the combinational logic, the (n +p)-tuple (W1, W2….Wn, y1, y2…..yp), propagates through that logic to form the m output Z1, Z2, …..Zm and the flip-flop input signals. All these changes must take place within a finite interval, known as interval Tg. Tg is the maximum propagation delay through the combinational logic block.
![Page 5: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/5.jpg)
5
• 3. Then all the flip-flop input signals must be held at their final values for an interval equal to or greater than the setup time Tsu for the flip-flops. Only after this interval it is safe to another synchronizing edge to occur. The clock period T must therefore satisfy T > Tf + Tg + Tsu for reliable behaviour in the network.
![Page 6: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/6.jpg)
6
State Model
Figure 7: State Model
![Page 7: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/7.jpg)
7
A synchronous sequential network can be represented in two different ways (Moore and Mealy)
![Page 8: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/8.jpg)
8
State-machine structure (Mealy)
typically edge-triggered D flip-flops
output depends onstate and input
![Page 9: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/9.jpg)
9
State-machine structure (Moore)
output dependson state only
typically edge-triggered D flip-flops
![Page 10: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/10.jpg)
10
State-machine structure (pipelined)
• Often used in PLD-based state machines.– Outputs taken directly from flip-flops, valid
sooner after clock edge.– But the “output logic” must determine output
value one clock tick sooner (“pipelined”).
![Page 11: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/11.jpg)
11
State Diagram
• A state diagram is a directed graph used to represent the transition and output function in a sequential system. Each state is represented by a node and each transition by an arc.
• An arc from node Sk to node Sj and labelled x/z specifies that, for a present state Sk and an input x, the next state is Sj and the output is z (figure 9).
![Page 12: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/12.jpg)
12
State
Sk
Sj
x/z
Figure 9: State Diagram (Mealy)
State
Sk/zk
Sj/zj
x
Figure 10: State diagram (equivalent Moore)
![Page 13: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/13.jpg)
13
A finite state machine can be represented using a state diagram or a state table. Figure 11 shows different modes of representation of a Mealy Machine
0/1
0/0
0/0p
1/1
1/0
S0 S1 S2
1/1
a) State diagram
![Page 14: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/14.jpg)
14
Current State S(t) Input x(t)
0 1
S0 S1,1 S2,1
S1 S1,0 S0,1
S2 S1,0 S2,1
S(t+1),z(t)
b) State stable
![Page 15: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/15.jpg)
15
Present Sate A B
Inputx
Next State NA NB
Output z
0 0: S0 0 0 1: S1 1
0 0: S0 1 1 0: S2 1
0 1: S1 0 0 1: S1 0
0 1: S1 1 0 0: S0 1
1 0: S2 0 0 1: S1 0
1 0: S2 1 1 0: S2 1
b) State transition table
Figure 12: Different modes of representations of a finite state
machine
![Page 16: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/16.jpg)
16
State-machine analysis steps
• Assumption: Starting point is a logic diagram.1. Determine next-state function F and output
function G.2a. Construct state table
– For each state/input combination, determine the excitation value.
– Using the characteristic equation, determine the corresponding next-state values (trivial with D f-f’s).
2b. Construct output table– For each state/input combination, determine the
output value. (Can be combined with state table.)
3. (Optional) Draw state diagram
![Page 17: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/17.jpg)
17
Example state machine
![Page 18: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/18.jpg)
18
Excitation equations
![Page 19: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/19.jpg)
19
Transition equations• Excitation equations
• Characteristic equations
• Substitute excitation equations into characteristic equations
![Page 20: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/20.jpg)
20
Transition and state tables
transitiontable
state table state/outputtable
(transitionequations)
(output equation)
another name for this function?
![Page 21: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/21.jpg)
21
State diagram
• Circles for states• Arrows for transitions (note output info)
![Page 22: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/22.jpg)
22
Modified state machine
• Moore machine
MAXS = Q0 Q1
MAXS
![Page 23: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/23.jpg)
23
Updated state/output table, state
diagram
![Page 24: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/24.jpg)
24
Timing diagram for state machine
• Not a complete description of machine behavior
![Page 25: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/25.jpg)
25
c) Specification of different types of sequential systems.
We will present two examples of specification of sequential systems. Additional systems are described in subsequent chapters.
Modulo-p Counter: A modulo-p counter is a sequential system whose input is a binary variable and whose output has integer values from the set {0,1, 2, ……,p-1}. Its time behaviour is described as follows:
![Page 26: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/26.jpg)
26
A state description requires p states. Assigning the integers 0 to p-1 as the state labels, the following description is obtained:
Input: x(t) {0,1}
Output: z(t) {0,1, 2,……,p-1}
State: s(t) {0,1, 2,……,p-1}
Initial state: s(0) = 0
Function: the transition and output functions are: s(t+1) = [s(t) + x(t)] mod p and z(t) = s(t)
Figure 13 shows the state diagram of a modulo-5 counter.
![Page 27: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/27.jpg)
27
Figure 13. State diagram of a modulo-5 counter.
Pattern Recognizer: A pattern recognizer is a sequential system whose binary output at time t indicates whether the input subsequence ending at time t corresponds to the particular pattern recognized by the system. Consequently, a pattern recognizer is a finite memory system – A sequential system has finite memory of length m if its output z(t) depends only on the last input values, that is z(t) = F(x(t-m+1,t)).
![Page 28: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/28.jpg)
28
A sequential system that recognizes the pattern P = (p0,p1,….,pm-1) has the following description:
Input: x(t) I
Output: z(t) {0,1}
Function :
otherwise 0
1 if 1)(
P)x(t-mtz
![Page 29: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/29.jpg)
29
Algorithmic State Machine (ASM)
• Why State diagrams are not Enough ?– Not flexible enough for describing very complex
finite state machines– Not suitable for gradual refinement of finite
state machine– Do not obviously describe an algorithm: that is,
well specifiedsequence of actions based on input data:
• algorithm = sequencing + data manipulation• separation of control and data
• Gradual shift towards program-like representation:– Algorithm State Machine (ASM) Notation– Hardware Description Languages (e.g., ABEL,
VHDL or Verilog)
![Page 30: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/30.jpg)
30
![Page 31: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/31.jpg)
31
![Page 32: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/32.jpg)
32
![Page 33: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/33.jpg)
33
![Page 34: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/34.jpg)
34
![Page 35: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/35.jpg)
35Figure 14: a) State machine; b) its equivalent ASM diagram
![Page 36: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/36.jpg)
36
Example: Odd Parity Checker
Even [0]
Odd [1]
Reset
0
0
1 1
Assert output whenever input bit stream has odd # of 1's
StateDiagram
Present State Even Even Odd Odd
Input 0 1 0 1
Next State Even Odd Odd Even
Output 0 0 1 1
Symbolic State Transition Table
Output 0 0 1 1
Next State 0 1 1 0
Input 0 1 0 1
Present State 0 0 1 1
Encoded State Transition Table
FSMs and ASMs
![Page 37: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/37.jpg)
37
Example: Odd Parity Checker Next State/Output FunctionsNS = PS xor PI; OUT = PS
D
R
Q
Q
Input
CLK PS/Output
\Reset
NS
D FF Implementation
T
R
Q
Q
Input
CLK
Output
\Reset
T FF Implementation
Timing Behavior: Input 1 0 0 1 1 0 1 0 1 1 1 0
Clk
Output
Input 1 0 0 1 1 0 1 0 1 1 1 0
1 1 0 1 0 0 1 1 0 1 1 1
![Page 38: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/38.jpg)
38
S0
S1
IN
IN
S2
IN
10
01
00
H.OUT
S0
S1
IN
IN
1
0
H.OUT
1
1
0
1
2
0
0
[0]
[0]
[1]
1/0
0
1
0/0
0/0
1/1
1
0
FSM Diagrams
ASM Diagrams
FSMs/ASMs (Moore and Mealy) of the odd Parity Detector
![Page 39: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/39.jpg)
39
Concept of the Synchronous Sequential Circuit
Timing: When are inputs sampled, next state computed, outputs asserted?
State Time: Time between clocking events
• Clocking event causes state/outputs to transition, based on inputs
• For set-up/hold time considerations:
Inputs should be stable before clocking event
• After propagation delay, Next State entered, Outputs are stable
NOTE: Asynchronous signals take effect immediately Synchronous signals take effect at the next clocking event
E.g., tri-state enable: effective immediately sync. counter clear: effective at next clock event
![Page 40: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/40.jpg)
40
Example: Positive Edge Triggered Synchronous System
• On rising edge, inputs sampled; outputs, next state computed
• After propagation delay, outputs and next state are stable
• Immediate Outputs:– affect datapath immediately– could cause inputs from datapath
to change• Delayed Outputs:
– take effect on next clock edge– propagation delays must exceed
hold times
Outputs
State T ime
Clock
Inputs
![Page 41: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/41.jpg)
41
Example: Vending Machine SSC
General Machine Concept:deliver package of gum after 15 cents deposited
single coin slot for dimes, nickels
no change
Block Diagram
Step 1. Understand the problem:
Vending Machine
SSC
N
D
Reset
Clk
OpenCoin
SensorGum
Release Mechanism
Draw a picture!
![Page 42: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/42.jpg)
42
Tabulate typical input sequences:three nickelsnickel, dimedime, nickeltwo dimestwo nickels, dime
Draw state diagram:
Inputs: N, D, reset
Output: open
Step 2. Map into more suitable abstract representation
Reset
N
N
N
D
D
N D
[open]
[open] [open] [open]
S0
S1 S2
S3 S4 S5 S6
S8
[open]
S7
D
Vending Machine Example
![Page 43: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/43.jpg)
43
Step 3: State Minimization
Reset
N
N
N, D
[open]
15¢
0¢
5¢
10¢
D
D
reuse stateswheneverpossible
Symbolic State Table
Present State
0¢
5¢
10¢
15¢
D
0 0 1 1 0 0 1 1 0 0 1 1 X
N
0 1 0 1 0 1 0 1 0 1 0 1 X
Inputs Next State
0¢ 5¢ 10¢ X 5¢ 10¢ 15¢ X
10¢ 15¢ 15¢ X
15¢
Output Open
0 0 0 X 0 0 0 X 0 0 0 X 1
![Page 44: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/44.jpg)
44
Step 4: State Encoding
Next State D 1 D 0
0 0 0 1 1 0 X X 0 1 1 0 1 1 X X 1 0 1 1 1 1 X X 1 1 1 1 1 1 X X
Present State Q 1 Q 0
0 0
0 1
1 0
1 1
D
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
N
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Inputs Output Open
0 0 0 X 0 0 0 X 0 0 0 X 1 1 1 X
![Page 45: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/45.jpg)
45
Step 5. Choose FFs for implementation D FF easiest to use
D1 = Q1 + D + Q0 N
D0 = N Q0 + Q0 N + Q1 N + Q1 D
OPEN = Q1 Q08 Gates
CLK
OPEN
CLK
Q 0
D
R
Q
Q
D
R
Q
Q
\ Q 1
\reset
\reset
\ Q 0
\ Q 0
Q 0
Q 0
Q 1
Q 1
Q 1
Q 1
D
D
N
N
N
\ N
D 1
D 0
Parity Checker Example
Q1 Q0 00
D
D N
Q1
N
Q0
0 0 1 1
0 1 1 1
X X X X
1 1 1 1
01 11 10
00
01
11
10
Q1 Q0 00
D
D N
Q1
N
Q0
0 1 1 0
1 0 1 1
X X X X
0 1 1 1
01 11 10
00
01
11
10
Q1 Q0 00
D
D N
Q1
N
Q0
0 0 1 0
0 0 1 0
X X X X
0 0 1 0
01 11 10
00
01
11
10
![Page 46: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/46.jpg)
46
Step 5. Choosing FF for Implementation
J-K FF
Remapped encoded state transition table
Next State D 1 D 0
0 0 0 1 1 0 X X 0 1 1 0 1 1 X X 1 0 1 1 1 1 X X 1 1 1 1 1 1 X X
Present State Q 1 Q 0
0 0
0 1
1 0
1 1
D
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
N
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Inputs K 1
X X X X X X X X 0 0 0 X 0 0 0 X
K 0
X X X X 0 1 0 X X X X X 0 0 0 X
J 1
0 0 1 X 0 1 1 X X X X X X X X X
J 0
0 1 0 X X X X X 0 1 1 X X X X X
Parity Checker Example
![Page 47: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/47.jpg)
47
State Diagram Equivalents
Outputs are associated with State
Outputs are associated with Transitions
Reset/0
N/0
N/0
N+D/1
15¢
0¢
5¢
10¢
D/0
D/1
(N D + Reset)/0
Reset/0
Reset/1
N D/0
N D/0
MooreMachine Reset
N
N
N+D
[1]
15¢
0¢
5¢
10¢
D
[0]
[0]
[0]
D
N D + Reset
Reset
Reset
N D
N D
MealyMachine
Moore and Mealy Machines
![Page 48: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/48.jpg)
48
ASM Chart for Vending Machine
0¢
15¢
H.Open
D
Reset
00
1 1
T
T
F
N F
T
F
10¢
D
10
T
N F
T
F
5¢
D
01
T N
F T
F
0¢
![Page 49: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/49.jpg)
49
Another design example (from text: pp. 564 - 576)
• Design a machine with inputs A and B and output Z that is 1 if:– A had the same value at the two previous ticks– B has been 1 since the last time the above was true
![Page 50: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/50.jpg)
50
State assignment
• There are 6,720 different state assignments of 5 states to 3 variables.– And there are even more using 4 or more
variables
• Here are a few “obvious” or “interesting” ones:
![Page 51: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/51.jpg)
51
Transition/output table (decomposed assignment)
• Simple textual substitution• With D flip-flops, excitation table is identical
to transition table.
![Page 52: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/52.jpg)
52
VHDL Coding: One "State" Process
FSM_FF: process (CLK, RESET)begin if RESET='1' then STATE <= START ; elsif CLK'event and CLK='1' then case STATE is when START => if X=GO_MID then STATE <= MIDDLE ; end if ; when MIDDLE => if X=GO_STOP then STATE <= STOP ; end if ; when STOP => if X=GO_START then STATE <= START ; end if ; when others => STATE <= START ; end case ; end if ;end process FSM_FF ;
![Page 53: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/53.jpg)
53
VHDL Coding: Two "State" Processes
FSM_FF: process (CLK, RESET) begin if RESET='1' then STATE <= START ; elsif CLK'event and CLK='1' then STATE <= NEXT_STATE ; end if;end process FSM_FF ;
FSM_LOGIC: process ( STATE , X)begin NEXT_STATE <= STATE ; case STATE is when START => if X=GO_MID then NEXT_STATE <= MIDDLE ; end if ; when MIDDLE => ... when others => NEXT_STATE <= START ; end case ;end process FSM_LOGIC ;
![Page 54: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/54.jpg)
54
Finite State Machine Word Problems
Mapping English Language Description to Formal Specifications
Four Case Studies:
Finite String Pattern Recognizer
Complex Counter with Decision Making
Traffic Light Controller
Digital Combination Lock
T-bird tail-lights example
We will use state diagrams and ASM Charts
Sept. 2005 EE37E Adv. Digital Electronics
2. Two "State" Processes
FSM_FF: process (CLK, RESET) beginif RESET='1' then
STATE <= START ;elsif CLK'event and CLK='1' then
STATE <= NEXT_STATE ;end if;
end process FSM_FF ;
FSM_LOGIC: process ( STATE , X)begin
NEXT_STATE <= STATE ;case STATE is
when START => if X=GO_MID thenNEXT_STATE <= MIDDLE ;
end if ;when MIDDLE => ...when others => NEXT_STATE <= START ;
end case ;end process FSM_LOGIC ;
![Page 55: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/55.jpg)
55
Develop excitation equations
• Assume unused states have next-state = 000
![Page 56: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/56.jpg)
56
Finite String Pattern Recognizer
A finite string recognizer has one input (X) and one output (Z).The output is asserted whenever the input sequence …010…has been observed, as long as the sequence 100 has never beenseen.
Step 1. Understanding the problem statement
Sample input/output behavior:
X: 00101010010Z: 00010101000
X: 11011010010Z: 00000001000
![Page 57: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/57.jpg)
57
Finite String Recognizer
Step 2. Draw State Diagrams/ASM Charts for the strings that must be recognized. I.e., 010 and 100.
Moore State DiagramReset signal places FSM in S0
Outputs 1 Loops in State
The output is asserted whenever the input sequence ..010… has been observed, as long as the sequence 100 has never been seen.
![Page 58: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/58.jpg)
58
Finite String Recognizer
Exit conditions from state S3: if next input is 0 then have …0100 (state S6) if next input is 1 then have …0101 (state S2)
![Page 59: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/59.jpg)
59
Finite String Recognizer
Exit conditions from S1: recognizes strings of form …0 (no 1 seen) loop back to S1 if input is 0
Exit conditions from S4: recognizes strings of form …1 (no 0 seen) loop back to S4 if input is 1
![Page 60: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/60.jpg)
60
Finite String RecognizerS2, S5 with incomplete transitions
S2 = …01; If next input is 1, then string could be prefix of (01)1(00) S4 handles just this case!
S5 = …10; If next input is 1, then string could be prefix of (10)1(0) S2 handles just this case!
Final State Diagram
![Page 61: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/61.jpg)
61
Finite String RecognizerReview of Process:
Write down sample inputs and outputs to understand specification
Write down sequences of states and transitions for the sequences to be recognized
Add missing transitions; reuse states as much as possible
Verify I/O behavior of your state diagram to insure it functions like the specification
![Page 62: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/62.jpg)
62
Complex Counter
A sync. 3 bit counter has a mode control M. When M = 0, the countercounts up in the binary sequence. When M = 1, the counter advancesthrough the Gray code sequence.
Binary: 000, 001, 010, 011, 100, 101, 110, 111Gray: 000, 001, 011, 010, 110, 111, 101, 100
Valid I/O behavior:
Mode Input M0011100
Current State000001010110111101110
Next State (Z2 Z1 Z0)001010110111101110111
![Page 63: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/63.jpg)
63
Complex Counter
One state for each output combinationAdd appropriate arcs for the mode control
S 0 000
S 1 001 H. Z 0
M
S 3 01 1 H. Z 1 H. Z 0
H. Z 1
S 2 010
M M
S 6 1 10 H. Z 2 H. Z 1
H. Z 2 H. Z 1 H. Z 0
S 4 100
M
H. Z 2
H. Z 2 H. Z 0
M
S 5 101
M
S 7 1 1 1
0 1
0 1
0
1
0
1 0
1
0 1
![Page 64: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/64.jpg)
64
Traffic Light Controller
A busy highway is intersected by a little used farmroad. DetectorsC sense the presence of cars waiting on the farmroad. With no caron farmroad, light remain green in highway direction. If vehicle on farmroad, highway lights go from Green to Yellow to Red, allowing the farmroad lights to become green. These stay green only as long as a farmroad car is detected but never longer than a set interval. When these are met, farm lights transition from Green to Yellow to Red, allowing highway to return to green. Even if farmroad vehicles are waiting, highway gets at least a set interval as green.
Assume you have an interval timer that generates a short time pulse(TS) and a long time pulse (TL) in response to a set (ST) signal. TSis to be used for timing yellow lights and TL for green lights.
![Page 65: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/65.jpg)
65
Traffic Light ControllerPicture of Highway/Farmroad Intersection:
Highway
Highway
Farmroad
Farmroad
HL
HL
FL
FL
C
C
![Page 66: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/66.jpg)
66
Traffic Light Controller
Tabulation of Inputs and Outputs:
Input SignalresetCTSTL
Output SignalHG, HY, HRFG, FY, FRST
Descriptionplace FSM in initial statedetect vehicle on farmroadshort time interval expiredlong time interval expired
Descriptionassert green/yellow/red highway lightsassert green/yellow/red farmroad lightsstart timing a short or long interval
Tabulation of Unique States: Some light configuration imply others
StateS0S1S2S3
DescriptionHighway green (farmroad red)Highway yellow (farmroad red)Farmroad green (highway red)Farmroad yellow (highway red)
![Page 67: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/67.jpg)
67
Traffic Light Controller
Refinement of ASM Chart:
Start with basic sequencing and outputs:
S 0 S 3
S 1 S 2
H.HG H.FR
H.HR H.FY
H.HR H.FG
H.HY H.FR
![Page 68: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/68.jpg)
68
Traffic Light ControllerDetermine Exit Conditions for S0: Car waiting and Long Time Interval Expired- C · TL
Equivalent ASM Chart Fragments
S 0 S 0
H.HG H.FR
H.HG H.FR
TL TL • C
H.ST C
H.ST S 1
H.HY H.FR
S 1
H.HY H.FR
0
0
1
1
0
1
C · TL
![Page 69: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/69.jpg)
69
Traffic Light Controller
S1 to S2 Transition: Set ST on exit from S0 Stay in S1 until TS asserted Similar situation for S3 to S4 transition
S 1
H.HY H.FR
TS
H.ST
S 2
H.HR H.FG
0 1
![Page 70: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/70.jpg)
70
Traffic Light Controller
S2 Exit Condition: no car waiting OR long time interval expired
Complete ASM Chart for Traffic Light Controller
S 0 S 3
H.HG H.FR H.ST
H.HR H.FY
TS TL • C
H.ST H.ST
S 1 S 2
H.HY H.FR
H.ST H.HR H.FG
TS TL + C
0 0 1
1
1 0
1
0
![Page 71: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/71.jpg)
71
Traffic Light ControllerCompare with state diagram:
Advantages of ASM Charts:
Concentrates on paths and conditions for exiting a state
Exit conditions built up incrementally, later combined into single Boolean condition for exit
Easier to understand the design as an algorithm
S0: HG
S1: HY
S2: FG
S3: FY
Reset
TL + C
S0TL•C/ST
TS
S1 S3
S2
TS/ST
TS/ST
TL + C/ST
TS
TL • C
![Page 72: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/72.jpg)
72
Digital Combination Lock
"3 bit serial lock controls entry to locked room. Inputs are RESET,ENTER, 2 position switch for bit of key data. Locks generates anUNLOCK signal when key matches internal combination. ERRORlight illuminated if key does not match combination. Sequence is:(1) Press RESET, (2) enter key bit, (3) Press ENTER, (4) repeat (2) &(3) two more times."
Problem specification is incomplete:
how do you set the internal combination?
exactly when is the ERROR light asserted?
Make reasonable assumptions:
hardwired into next state logic vs. stored in internal register
assert as soon as error is detected vs. wait until full combination has been entered
Our design: registered combination plus error after full combination
![Page 73: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/73.jpg)
73
Digital Combination Lock
Understanding the problem: draw a block diagram
InternalCombination
Operator Data
Inputs:ResetEnterKey-InL0, L1, L2
Outputs:UnlockError
UNLOCK
ERROR
RESET
ENTER
KEY -IN
L 0
L 1
L 2
Combination Lock FSM
![Page 74: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/74.jpg)
74
Digital Combination Lock
Enumeration of states:
what sequences lead to opening the door? error conditions on a second pass
START state plus three key COMParison states
START entered on RESET
Exit START when ENTER is pressed
Continue on if Key-In matches L0
ST ART
Reset
Enter
COMP0
KI = L 0
N
Y
1
0
0
1
![Page 75: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/75.jpg)
75
Digital Combination Lock
Path to unlock:
Wait for Enter Key press
Compare Key-IN
COMP0
N KI = L 0
Y IDLE0
Enter
COMP1
N
Y
KI = L 1
IDLE1
COMP2
Enter
N KI = L 2
Y DONE
H.Unlock
Reset
ST ART
1
0
0
1
0
1
![Page 76: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/76.jpg)
76
Digital Combination Lock
Now consider error paths
Should follow a similar sequence as UNLOCK path, except asserting ERROR at the end:
COMP0 error exits to IDLE0'
COMP1 error exits to IDLE1'
COMP2 error exits to ERROR3
IDLE0'
Enter
ERROR1
IDLE1'
Enter
ERROR2
ERROR3
H.Error
Reset
ST ART
0 0 0
1 1 1
![Page 77: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/77.jpg)
77
Digital Combination Lock
Equivalent State Diagram
Reset
Reset + Enter
Reset • Enter
Start
Comp0
KI = L0 KI ° L0
Enter
Enter
Enter
Enter
Idle0 Idle0'
Comp1 Error1
KI ° L1KI = L1Enter
Enter
EnterEnter
Idle1 Idle1'
Comp2 Error2
KI ° L2KI = L2
Done [Unlock]
Error3 [Error]
Reset
Reset Reset
Reset
StartStart
![Page 78: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/78.jpg)
78
T-bird tail-lights (text, pp585 – 591)
![Page 79: 1 ECNG1014 Digital Electronics Sequential Logic: FSMs](https://reader036.vdocument.in/reader036/viewer/2022062314/56649ed35503460f94be2e23/html5/thumbnails/79.jpg)
79
Statediagra
m
Inputs:LEFT, RIGHT, HAZ
Outputs:Six lamps(function of state only