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Performance Analysis
(Clock Signal)
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Unbalanced delays
Logic with unbalanced delays leads to inefficient use of logic:
long clock periodshort clock period
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Flip-flop-based system performance analysis
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Flip-flop-based system model
• Clock signal is perfect (no rise/fall), period P• Clock event on rising edge• Setup time s
– Time from arrival of combinational logic event to clock event
• Propagation time p– Time for value to go from input to output (tco?)
• Worst-case combinational delay C– Time from output of flip-flop to input
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Clock period constraint
• P >= p + C + s. s p C
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Clock parameters
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Clock with rise/fall
• tr is large because the clock wire is long and has high capacitance.
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Rise/fall clock period constraint
• P >= tr + p + C + s s p Ctr
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Skew
• Skew: relative delay between events.
• Clock skew: can harm any sequential system.
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Clock skew
Clock must arrive at all memory elements in time to load data.
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Clock skew in system
D Q
D Q
logic
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Clock skew and qualified (gated) clocks
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Clock skew analysis model
s12 = 1 – 2s21 = 2 – 1
• Assume 1 > 2 (s12 > 0)φ
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Skew and clock period
• Assume that each flip-flop operates instantaneously:
• If clock arrives at FF1 after FF2, then there is less time for the signal to propagate through the combinational logic.
• Given clock period, determine allowable skew:P >= 2 + s12
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Clock distribution
• Often one of the hardest problems in clock design.– Fast edges.
– Minimum skew.
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Clock skew example
10 ps 10 ps
20 ps 20 ps
30 ps 30 ps
D Q D QD Q
D Q
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Clock H-Tree
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Digital Clock Manager (DCM)
• A hard block in FPGAs– Gets clock input– Generates daughter clocks
• FPGA can have multiple DCMs
• Provides clocks to – internal circuitry– external devices on board
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DCM
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DCM Functions
• Jitter removal
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DCM Functions• Frequency synthesis:
– Clock frequency generated outside ≠ frequency needed in our FPGA multiplies/divides it to generate daughter clocks
• Can generate even other ratios (3/4, 4/5 of original)– In Spartan 6: n times or n/2 times (n ∈ [1,16])
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DCM Functions• Phase shifting:
– Some designs need phased-shifted clocks• Some DCMs allow common values
– 120, 240: for 3-phase clocking scheme
– 90, 180, 270: for 4-phase clocking scheme
• Some DCMs allow to set exact values
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DCM Functions• Clock deskewing:
– DCM gets a special input – DCM compares the two signals– Adds additional delay to the daughter clock to align
with the main clock
• Two types:– PLL (phase-locked loop): analogue– DLL (digital-delay locked loop): digital
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DCM Functions• Auto skew correction:
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DCM
• You can enter DCM parameters in tools:– Frequency– Duty cycle– Phase shift– …
• See Xilinx ISE In-Depth Tutorial, UG695 (v 14.1), 2012
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Case Study
• 16 x 16 multiplier example.
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The FPGA design process
• Xilinx ISE (Integrated Synthesis Environment)– Translation from HDL
– Logic synthesis
– Placement and routing
– Configuration generation
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Design experiments
• Synthesize with no constraints.• Synthesize with timing constraint.
– Tighten timing constraint.
• Synthesize with placement constraints.• Power:
– Many tools don’t allow us to directly specify power consumption
– Some tools allow us to specify power as an objective– May need to rewrite our h/w description for better power
consumption characteristics.
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Commercial Tools
• XST “-power” option reduces dynamic power consumption.
• Xilinx MAP and PAR“-power” option reduces dynamic power– But increases runtime and decreases design
performance.
• Quartus-II has Power-Driven Synthesis and Place & Route.
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Post-translation simulation model
• No timing or area constraints• HDL model in terms of FPGA primitives.• Example: X_LUT4 \p12_Madd__n0015_Mxor_Result_Xo<1>1
( .ADR0(x_7_IBUF), .ADR1(y_13_IBUF), .ADR2(c12[7]), .ADR3(row12[8]), .O(row13[7]) );
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Mapping report
Design Summary--------------Number of errors: 0Number of warnings: 0Logic Utilization: Number of 4 input LUTs: 501 out of 1,024 48%Logic Distribution: Number of occupied Slices: 255 out of 512 49% Number of Slices containing only related logic: 255 out of 255 100% Number of Slices containing unrelated logic: 0 out of 255 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs: 501 out of 1,024 48%
Number of bonded IOBs: 64 out of 92 69%
Total equivalent gate count for design: 3,006Additional JTAG gate count for IOBs: 3,072Peak Memory Usage: 64 MB
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Static timing analysis report
Timing constraint: TS_P2P = MAXDELAY FROM TIMEGRP "PADS" TO TIMEGRP "PADS" 99.999 uS ;
20135312 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Maximum delay is 20.916ns.--------------------------------------------------------------------------------
After Mapping: estimated delays (no information about interconnects)
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Static timing report: delays along paths
Data Sheet report:-----------------All values displayed in nanoseconds (ns)
Pad to Pad------------------+----------------------+-----------+Source Pad |Destination Pad| Delay |------------------+----------------------+-----------+x<0> |p<0> | 5.824|x<0> |p<10> | 10.675|x<0> |p<11> | 11.214|x<0> |p<12> | 11.753|
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Routing reportPhase 1: 1975 unrouted; REAL time: 11 secs
Phase 2: 1975 unrouted; REAL time: 11 secs
Phase 3: 619 unrouted; REAL time: 12 secs
Phase 4: 619 unrouted; (0) REAL time: 12 secs
Phase 5: 619 unrouted; (0) REAL time: 12 secs
Phase 6: 619 unrouted; (0) REAL time: 12 secs
Phase 7: 0 unrouted; (0) REAL time: 12 secs
The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0
• REAL time: Routing algorithm run time.
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Static timing after routing
Timing constraint: TS_P2P = MAXDELAY FROM TIMEGRP "PADS" TO TIMEGRP "PADS" 99.999 uS ;
20135312 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Maximum delay is 38.424ns.
-------------------------------------------------------------------
• (vs. 20.916 ns in mapping report) Because of interconnect delays.
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Timing constraint
• Use timing constraint editor:
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Post-map static timing report
Timing constraint: TS_P2P = MAXDELAY FROM
TIMEGRP "PADS" TO TIMEGRP "PADS" 32 nS ;
20135312 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Maximum delay is 20.916ns.
Pad to pad
Hasn’t changed since this design has limited opportunities for logic synthesis to change delays by restructuring logic.
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Post-routing static timing report
Timing constraint: TS_P2P = MAXDELAY FROM
TIMEGRP "PADS" TO TIMEGRP "PADS" 32 nS ;
20135312 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Maximum delay is 31.984ns.
Tools generally try to meet the delay goal as closely as possible to minimize area.
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Tighter timing constraints
• Tighten requirement to 25 ns.• Post-place-route timing report:
Timing constraint: TS_P2P = MAXDELAY FROM TIMEGRP "PADS" TO TIMEGRP "PADS" 25 nS ;
20135312 items analyzed, 11 timing errors detected. (11 setup errors, 0 hold errors)
Maximum delay is 31.128ns.
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Report on a violated path
Slack: -6.128ns (requirement - data path) Source: y<0> (PAD) Destination: p<30> (PAD) Requirement: 25.000ns Data Path Delay: 31.128ns (Levels of Logic = 31)
Modify the logic and/or physical design to improve the delay.
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Power report
Power summary: I(mA) P(mW)----------------------------------------------------------------Total estimated power consumption: 333 --- Vccint 1.50V: 0 0 Vccaux 3.30V: 100 330 Vcco33 3.30V: 1 3 --- Inputs: 0 0 Logic: 0 0 Outputs: Vcco33 0 0 Signals: 0 0 --- Quiescent Vccaux 3.30V: 100 330 Quiescent Vcco33 3.30V: 1 3
Thermal summary:---------------------------------------------------------------- Estimated junction temperature: 36C Ambient temp: 25C Case temp: 35C Theta J-A: 34C/W
Helps us determine whether we need additional cooling.
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Improving area• Floorplanner window:
– Floorplanner View/edit placed design
LEs
Chipfloorplan
• Green rectangles: mapped components to CLBs
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Rat’s nest wiring• If you click on a component in the deign hierarchy window, its
rat’s nest is shown.
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Routing editor view• FPGA Editor View/Edit Routed Design
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Editing constraints• Use constraints editor to place constraints:
– This tool allws you to constrain 1. placement of logic 2. assignment of chip I/Os to IOBs (e.g useful for PCB design)
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Design browser pane
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Drag and drop constraints
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Change the shape of constraints
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Full set of placement constraints
• We place the rows of the multiplier one below the other to create the row structure of the floorplan.
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Placement results
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New timing report
• After placement constraints: 19742142 items analyzed, 0 timing errors
detected. (0 setup errors, 0 hold errors)
Maximum delay is 29.934ns.
• Compares to 31.128 ns for unconstrained placement.